llvm.org GIT mirror llvm / 22a8753
X86 Tests: Add AVX512BW config to CodeGenPrepare test. NFC Case points out that we don't consider shifts supported by AVX512BW in isVectorShiftByScalarCheap() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323242 91177308-0d34-0410-b5e6-96231b3b80d8 Zvi Rackover 1 year, 9 months ago
1 changed file(s) with 10 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
None ; RUN: opt -S -codegenprepare -mcpu=core-avx2 %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AVX2
0 ; RUN: opt -S -codegenprepare -mcpu=skylake-avx512 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX512BW
1 ; RUN: opt -S -codegenprepare -mcpu=core-avx2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX2
12 ; RUN: opt -S -codegenprepare -mcpu=corei7 %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SSE2
23
34 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
6162 }
6263
6364 define <4 x i32> @test_32bit(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) {
64 ; CHECK-AVX2-LABEL: @test_32bit
65 ; CHECK-AVX2: if_false:
66 ; CHECK-AVX2-NOT: shufflevector
67 ; CHECK-AVX2: ashr <4 x i32> %lhs, %mask
65 ; CHECK-AVX-LABEL: @test_32bit
66 ; CHECK-AVX: if_false:
67 ; CHECK-AVX-NOT: shufflevector
68 ; CHECK-AVX: ashr <4 x i32> %lhs, %mask
6869
6970 ; CHECK-SSE2-LABEL: @test_32bit
7071 ; CHECK-SSE2: if_false:
8283 }
8384
8485 define <2 x i64> @test_64bit(<2 x i64> %lhs, <2 x i64> %tmp, i1 %tst) {
85 ; CHECK-AVX2-LABEL: @test_64bit
86 ; CHECK-AVX2: if_false:
87 ; CHECK-AVX2-NOT: shufflevector
88 ; CHECK-AVX2: lshr <2 x i64> %lhs, %mask
86 ; CHECK-AVX-LABEL: @test_64bit
87 ; CHECK-AVX: if_false:
88 ; CHECK-AVX-NOT: shufflevector
89 ; CHECK-AVX: lshr <2 x i64> %lhs, %mask
8990
9091 ; CHECK-SSE2-LABEL: @test_64bit
9192 ; CHECK-SSE2: if_false: