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[SDAG] Avoid deleted SDNodes PromoteIntBinOp Reorder work in PromoteIntBinOp to prevent stale (deleted) nodes from being used. Fixes PR32340 and PR32345. Reviewers: hfinkel, dbabokin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31148 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298923 91177308-0d34-0410-b5e6-96231b3b80d8 Nirav Dave 3 years ago
3 changed file(s) with 268 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
10861086 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
10871087 assert(PVT != VT && "Don't know what type to promote to!");
10881088
1089 DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG));
1090
10891091 bool Replace0 = false;
10901092 SDValue N0 = Op.getOperand(0);
10911093 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1092 if (!NN0.getNode())
1093 return SDValue();
10941094
10951095 bool Replace1 = false;
10961096 SDValue N1 = Op.getOperand(1);
1097 SDValue NN1;
1098 if (N0 == N1)
1099 NN1 = NN0;
1100 else {
1101 NN1 = PromoteOperand(N1, PVT, Replace1);
1102 if (!NN1.getNode())
1103 return SDValue();
1104 }
1105
1106 AddToWorklist(NN0.getNode());
1107 if (NN1.getNode())
1097 SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
1098 SDLoc DL(Op);
1099
1100 SDValue RV =
1101 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
1102
1103 // New replace instances of N0 and N1
1104 if (Replace0 && N0 && N0.getOpcode() != ISD::DELETED_NODE && NN0 &&
1105 NN0.getOpcode() != ISD::DELETED_NODE) {
1106 AddToWorklist(NN0.getNode());
1107 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1108 }
1109
1110 if (Replace1 && N1 && N1.getOpcode() != ISD::DELETED_NODE && NN1 &&
1111 NN1.getOpcode() != ISD::DELETED_NODE) {
11081112 AddToWorklist(NN1.getNode());
1109
1110 if (Replace0)
1111 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1112 if (Replace1)
11131113 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1114
1115 DEBUG(dbgs() << "\nPromoting ";
1116 Op.getNode()->dump(&DAG));
1117 SDLoc DL(Op);
1118 return DAG.getNode(ISD::TRUNCATE, DL, VT,
1119 DAG.getNode(Opc, DL, PVT, NN0, NN1));
1114 }
1115
1116 // Deal with Op being deleted.
1117 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1118 return RV;
11201119 }
11211120 return SDValue();
11221121 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu -o - %s | FileCheck %s -check-prefix=X64
2
3 @var_825 = external global i16, align 2
4 @var_32 = external global i16, align 2
5 @var_901 = external global i16, align 2
6 @var_826 = external global i64, align 8
7 @var_57 = external global i64, align 8
8 @var_900 = external global i16, align 2
9 @var_28 = external constant i64, align 8
10 @var_827 = external global i16, align 2
11
12 define void @foo() {
13 ; X64-LABEL: foo:
14 ; X64: # BB#0: # %entry
15 ; X64-NEXT: movw $0, {{.*}}(%rip)
16 ; X64-NEXT: movzwl {{.*}}(%rip), %eax
17 ; X64-NEXT: movw %ax, %cx
18 ; X64-NEXT: movw {{.*}}(%rip), %dx
19 ; X64-NEXT: xorw %dx, %cx
20 ; X64-NEXT: # implicit-def: %ESI
21 ; X64-NEXT: movw %cx, %si
22 ; X64-NEXT: movl %eax, %edi
23 ; X64-NEXT: xorl %esi, %edi
24 ; X64-NEXT: movw %di, %cx
25 ; X64-NEXT: movzwl %cx, %esi
26 ; X64-NEXT: movl %esi, %edi
27 ; X64-NEXT: addl %eax, %edi
28 ; X64-NEXT: movl %edi, %r8d
29 ; X64-NEXT: movq %r8, {{.*}}(%rip)
30 ; X64-NEXT: xorl $-772157262, %esi # imm = 0xD1F9D0B2
31 ; X64-NEXT: movl {{.*}}(%rip), %eax
32 ; X64-NEXT: movl %esi, %edi
33 ; X64-NEXT: orl %eax, %edi
34 ; X64-NEXT: orl %edi, %esi
35 ; X64-NEXT: movw %si, %cx
36 ; X64-NEXT: movw %cx, {{.*}}(%rip)
37 ; X64-NEXT: movq {{.*}}(%rip), %r8
38 ; X64-NEXT: testq %r8, %r8
39 ; X64-NEXT: setne %r9b
40 ; X64-NEXT: movzbl %r9b, %eax
41 ; X64-NEXT: movw %ax, %cx
42 ; X64-NEXT: movw %cx, var_827
43 ; X64-NEXT: retq
44 entry:
45 store i16 0, i16* @var_825, align 2
46 %v0 = load i16, i16* @var_32, align 2
47 %conv = zext i16 %v0 to i32
48 %v2 = load i16, i16* @var_901, align 2
49 %conv2 = zext i16 %v2 to i32
50 %xor = xor i32 %conv, %conv2
51 %xor3 = xor i32 %conv, %xor
52 %add = add nsw i32 %xor3, %conv
53 %conv5 = sext i32 %add to i64
54 store i64 %conv5, i64* @var_826, align 8
55 %v4 = load i16, i16* @var_32, align 2
56 %conv6 = zext i16 %v4 to i64
57 %v6 = load i16, i16* @var_901, align 2
58 %conv8 = zext i16 %v6 to i32
59 %xor9 = xor i32 51981, %conv8
60 %conv10 = sext i32 %xor9 to i64
61 %xor11 = xor i64 -1142377792914660288, %conv10
62 %xor12 = xor i64 %conv6, %xor11
63 %neg = xor i64 %xor12, -1
64 %xor13 = xor i64 %conv6, %neg
65 %v9 = load i16, i16* @var_901, align 2
66 %v10 = load i64, i64* @var_57, align 8
67 %or = or i64 %xor13, %v10
68 %or23 = or i64 %xor13, %or
69 %conv24 = trunc i64 %or23 to i16
70 store i16 %conv24, i16* @var_900, align 2
71 %v11 = load i64, i64* @var_28, align 8
72 %cmp = icmp ne i64 0, %v11
73 %conv25 = zext i1 %cmp to i16
74 store i16 %conv25, i16* @var_827, align 2
75 ret void
76 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu -o - %s | FileCheck %s -check-prefix=X640
2 ; RUN: llc -O0 -mtriple=i686-unknown -o - %s | FileCheck %s -check-prefix=6860
3 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - %s | FileCheck %s -check-prefix=X64
4 ; RUN: llc -mtriple=i686-unknown -o - %s | FileCheck %s -check-prefix=686
5
6 @var_22 = external global i16, align 2
7 @var_27 = external global i16, align 2
8
9 define void @foo() {
10 ; X640-LABEL: foo:
11 ; X640: # BB#0: # %bb
12 ; X640-NEXT: # implicit-def: %RAX
13 ; X640-NEXT: movzwl var_22, %ecx
14 ; X640-NEXT: movzwl var_27, %edx
15 ; X640-NEXT: xorl %edx, %ecx
16 ; X640-NEXT: movzwl var_27, %edx
17 ; X640-NEXT: xorl %edx, %ecx
18 ; X640-NEXT: movslq %ecx, %rsi
19 ; X640-NEXT: movq %rsi, -{{[0-9]+}}(%rsp)
20 ; X640-NEXT: movzwl var_22, %ecx
21 ; X640-NEXT: movzwl var_27, %edx
22 ; X640-NEXT: xorl %edx, %ecx
23 ; X640-NEXT: movzwl var_27, %edx
24 ; X640-NEXT: xorl %edx, %ecx
25 ; X640-NEXT: movslq %ecx, %rsi
26 ; X640-NEXT: movzwl var_27, %ecx
27 ; X640-NEXT: subl $16610, %ecx # imm = 0x40E2
28 ; X640-NEXT: movl %ecx, %ecx
29 ; X640-NEXT: # kill: %RCX %ECX
30 ; X640-NEXT: # kill: %CL %RCX
31 ; X640-NEXT: sarq %cl, %rsi
32 ; X640-NEXT: movb %sil, %cl
33 ; X640-NEXT: movb %cl, (%rax)
34 ; X640-NEXT: retq
35 ;
36 ; 6860-LABEL: foo:
37 ; 6860: # BB#0: # %bb
38 ; 6860-NEXT: pushl %ebp
39 ; 6860-NEXT: .Lcfi0:
40 ; 6860-NEXT: .cfi_def_cfa_offset 8
41 ; 6860-NEXT: .Lcfi1:
42 ; 6860-NEXT: .cfi_offset %ebp, -8
43 ; 6860-NEXT: movl %esp, %ebp
44 ; 6860-NEXT: .Lcfi2:
45 ; 6860-NEXT: .cfi_def_cfa_register %ebp
46 ; 6860-NEXT: pushl %ebx
47 ; 6860-NEXT: pushl %edi
48 ; 6860-NEXT: pushl %esi
49 ; 6860-NEXT: andl $-8, %esp
50 ; 6860-NEXT: subl $32, %esp
51 ; 6860-NEXT: .Lcfi3:
52 ; 6860-NEXT: .cfi_offset %esi, -20
53 ; 6860-NEXT: .Lcfi4:
54 ; 6860-NEXT: .cfi_offset %edi, -16
55 ; 6860-NEXT: .Lcfi5:
56 ; 6860-NEXT: .cfi_offset %ebx, -12
57 ; 6860-NEXT: # implicit-def: %EAX
58 ; 6860-NEXT: movw var_22, %cx
59 ; 6860-NEXT: movzwl var_27, %edx
60 ; 6860-NEXT: movw %dx, %si
61 ; 6860-NEXT: xorw %si, %cx
62 ; 6860-NEXT: # implicit-def: %EDI
63 ; 6860-NEXT: movw %cx, %di
64 ; 6860-NEXT: xorl %edx, %edi
65 ; 6860-NEXT: movw %di, %cx
66 ; 6860-NEXT: movzwl %cx, %edi
67 ; 6860-NEXT: movl %edi, {{[0-9]+}}(%esp)
68 ; 6860-NEXT: movl $0, {{[0-9]+}}(%esp)
69 ; 6860-NEXT: addl $-16610, %edx # imm = 0xBF1E
70 ; 6860-NEXT: movb %dl, %bl
71 ; 6860-NEXT: xorl %edx, %edx
72 ; 6860-NEXT: movb %bl, %cl
73 ; 6860-NEXT: shrdl %cl, %edx, %edi
74 ; 6860-NEXT: testb $32, %bl
75 ; 6860-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
76 ; 6860-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill
77 ; 6860-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
78 ; 6860-NEXT: jne .LBB0_2
79 ; 6860-NEXT: # BB#1: # %bb
80 ; 6860-NEXT: movl {{[0-9]+}}(%esp), %eax # 4-byte Reload
81 ; 6860-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
82 ; 6860-NEXT: .LBB0_2: # %bb
83 ; 6860-NEXT: movl {{[0-9]+}}(%esp), %eax # 4-byte Reload
84 ; 6860-NEXT: movb %al, %cl
85 ; 6860-NEXT: movl {{[0-9]+}}(%esp), %eax # 4-byte Reload
86 ; 6860-NEXT: movb %cl, (%eax)
87 ; 6860-NEXT: leal -12(%ebp), %esp
88 ; 6860-NEXT: popl %esi
89 ; 6860-NEXT: popl %edi
90 ; 6860-NEXT: popl %ebx
91 ; 6860-NEXT: popl %ebp
92 ; 6860-NEXT: retl
93 ;
94 ; X64-LABEL: foo:
95 ; X64: # BB#0: # %bb
96 ; X64-NEXT: movzwl {{.*}}(%rip), %ecx
97 ; X64-NEXT: movw {{.*}}(%rip), %ax
98 ; X64-NEXT: xorw %cx, %ax
99 ; X64-NEXT: xorl %ecx, %eax
100 ; X64-NEXT: movzwl %ax, %eax
101 ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
102 ; X64-NEXT: addl $-16610, %ecx # imm = 0xBF1E
103 ; X64-NEXT: # kill: %CL %CL %ECX
104 ; X64-NEXT: shrq %cl, %rax
105 ; X64-NEXT: movb %al, (%rax)
106 ; X64-NEXT: retq
107 ;
108 ; 686-LABEL: foo:
109 ; 686: # BB#0: # %bb
110 ; 686-NEXT: pushl %ebp
111 ; 686-NEXT: .Lcfi0:
112 ; 686-NEXT: .cfi_def_cfa_offset 8
113 ; 686-NEXT: .Lcfi1:
114 ; 686-NEXT: .cfi_offset %ebp, -8
115 ; 686-NEXT: movl %esp, %ebp
116 ; 686-NEXT: .Lcfi2:
117 ; 686-NEXT: .cfi_def_cfa_register %ebp
118 ; 686-NEXT: andl $-8, %esp
119 ; 686-NEXT: subl $8, %esp
120 ; 686-NEXT: movzwl var_27, %ecx
121 ; 686-NEXT: movw var_22, %ax
122 ; 686-NEXT: xorw %cx, %ax
123 ; 686-NEXT: xorl %ecx, %eax
124 ; 686-NEXT: movzwl %ax, %eax
125 ; 686-NEXT: movl %eax, (%esp)
126 ; 686-NEXT: movl $0, {{[0-9]+}}(%esp)
127 ; 686-NEXT: addl $-16610, %ecx # imm = 0xBF1E
128 ; 686-NEXT: xorl %edx, %edx
129 ; 686-NEXT: shrdl %cl, %edx, %eax
130 ; 686-NEXT: testb $32, %cl
131 ; 686-NEXT: jne .LBB0_2
132 ; 686-NEXT: # BB#1: # %bb
133 ; 686-NEXT: movl %eax, %edx
134 ; 686-NEXT: .LBB0_2: # %bb
135 ; 686-NEXT: movb %dl, (%eax)
136 ; 686-NEXT: movl %ebp, %esp
137 ; 686-NEXT: popl %ebp
138 ; 686-NEXT: retl
139 bb:
140 %tmp = alloca i64, align 8
141 %tmp1 = load i16, i16* @var_22, align 2
142 %tmp2 = zext i16 %tmp1 to i32
143 %tmp3 = load i16, i16* @var_27, align 2
144 %tmp4 = zext i16 %tmp3 to i32
145 %tmp5 = xor i32 %tmp2, %tmp4
146 %tmp6 = load i16, i16* @var_27, align 2
147 %tmp7 = zext i16 %tmp6 to i32
148 %tmp8 = xor i32 %tmp5, %tmp7
149 %tmp9 = sext i32 %tmp8 to i64
150 store i64 %tmp9, i64* %tmp, align 8
151 %tmp10 = load i16, i16* @var_22, align 2
152 %tmp11 = zext i16 %tmp10 to i32
153 %tmp12 = load i16, i16* @var_27, align 2
154 %tmp13 = zext i16 %tmp12 to i32
155 %tmp14 = xor i32 %tmp11, %tmp13
156 %tmp15 = load i16, i16* @var_27, align 2
157 %tmp16 = zext i16 %tmp15 to i32
158 %tmp17 = xor i32 %tmp14, %tmp16
159 %tmp18 = sext i32 %tmp17 to i64
160 %tmp19 = load i16, i16* @var_27, align 2
161 %tmp20 = zext i16 %tmp19 to i32
162 %tmp21 = sub nsw i32 %tmp20, 16610
163 %tmp22 = zext i32 %tmp21 to i64
164 %tmp23 = ashr i64 %tmp18, %tmp22
165 %tmp24 = trunc i64 %tmp23 to i8
166 store i8 %tmp24, i8* undef, align 1
167 ret void
168 }