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AMDGPU/SI: Promote i1 SETCC operations Summary: While working on uniform branching, I've hit a few cases where we emit i1 SETCC operations. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16233 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258352 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
2 changed file(s) with 21 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
102102 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
103103 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
104104
105 setOperationAction(ISD::SETCC, MVT::i1, Promote);
105106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
106107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
107108
388388 endif:
389389 ret void
390390 }
391
392 ; FUNC-LABEL: setcc-i1-and-xor
393 ; SI-DAG: v_cmp_le_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
394 ; SI-DAG: v_cmp_ge_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], 1.0, s{{[0-9]+}}
395 ; SI: s_and_b64 s[2:3], [[A]], [[B]]
396 define void @setcc-i1-and-xor(i32 addrspace(1)* %out, float %cond) #0 {
397 bb0:
398 %tmp5 = fcmp oge float %cond, 0.000000e+00
399 %tmp7 = fcmp ole float %cond, 1.000000e+00
400 %tmp9 = and i1 %tmp5, %tmp7
401 %tmp11 = xor i1 %tmp9, 1
402 br i1 %tmp11, label %bb2, label %bb1
403
404 bb1:
405 store i32 0, i32 addrspace(1)* %out
406 br label %bb2
407
408 bb2:
409 ret void
410 }