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ARM prefix asmparser operand kind enums for readability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
1 changed file(s) with 173 addition(s) and 173 deletion(s). Raw diff Collapse all Expand all
241241 /// instruction.
242242 class ARMOperand : public MCParsedAsmOperand {
243243 enum KindTy {
244 CondCode,
245 CCOut,
246 ITCondMask,
247 CoprocNum,
248 CoprocReg,
249 Immediate,
250 FPImmediate,
251 MemBarrierOpt,
252 Memory,
253 PostIndexRegister,
254 MSRMask,
255 ProcIFlags,
256 Register,
257 RegisterList,
258 DPRRegisterList,
259 SPRRegisterList,
260 ShiftedRegister,
261 ShiftedImmediate,
262 ShifterImmediate,
263 RotateImmediate,
264 BitfieldDescriptor,
265 Token
244 k_CondCode,
245 k_CCOut,
246 k_ITCondMask,
247 k_CoprocNum,
248 k_CoprocReg,
249 k_Immediate,
250 k_FPImmediate,
251 k_MemBarrierOpt,
252 k_Memory,
253 k_PostIndexRegister,
254 k_MSRMask,
255 k_ProcIFlags,
256 k_Register,
257 k_RegisterList,
258 k_DPRRegisterList,
259 k_SPRRegisterList,
260 k_ShiftedRegister,
261 k_ShiftedImmediate,
262 k_ShifterImmediate,
263 k_RotateImmediate,
264 k_BitfieldDescriptor,
265 k_Token
266266 } Kind;
267267
268268 SMLoc StartLoc, EndLoc;
360360 StartLoc = o.StartLoc;
361361 EndLoc = o.EndLoc;
362362 switch (Kind) {
363 case CondCode:
363 case k_CondCode:
364364 CC = o.CC;
365365 break;
366 case ITCondMask:
366 case k_ITCondMask:
367367 ITMask = o.ITMask;
368368 break;
369 case Token:
369 case k_Token:
370370 Tok = o.Tok;
371371 break;
372 case CCOut:
373 case Register:
372 case k_CCOut:
373 case k_Register:
374374 Reg = o.Reg;
375375 break;
376 case RegisterList:
377 case DPRRegisterList:
378 case SPRRegisterList:
376 case k_RegisterList:
377 case k_DPRRegisterList:
378 case k_SPRRegisterList:
379379 Registers = o.Registers;
380380 break;
381 case CoprocNum:
382 case CoprocReg:
381 case k_CoprocNum:
382 case k_CoprocReg:
383383 Cop = o.Cop;
384384 break;
385 case Immediate:
385 case k_Immediate:
386386 Imm = o.Imm;
387387 break;
388 case FPImmediate:
388 case k_FPImmediate:
389389 FPImm = o.FPImm;
390390 break;
391 case MemBarrierOpt:
391 case k_MemBarrierOpt:
392392 MBOpt = o.MBOpt;
393393 break;
394 case Memory:
394 case k_Memory:
395395 Mem = o.Mem;
396396 break;
397 case PostIndexRegister:
397 case k_PostIndexRegister:
398398 PostIdxReg = o.PostIdxReg;
399399 break;
400 case MSRMask:
400 case k_MSRMask:
401401 MMask = o.MMask;
402402 break;
403 case ProcIFlags:
403 case k_ProcIFlags:
404404 IFlags = o.IFlags;
405405 break;
406 case ShifterImmediate:
406 case k_ShifterImmediate:
407407 ShifterImm = o.ShifterImm;
408408 break;
409 case ShiftedRegister:
409 case k_ShiftedRegister:
410410 RegShiftedReg = o.RegShiftedReg;
411411 break;
412 case ShiftedImmediate:
412 case k_ShiftedImmediate:
413413 RegShiftedImm = o.RegShiftedImm;
414414 break;
415 case RotateImmediate:
415 case k_RotateImmediate:
416416 RotImm = o.RotImm;
417417 break;
418 case BitfieldDescriptor:
418 case k_BitfieldDescriptor:
419419 Bitfield = o.Bitfield;
420420 break;
421421 }
427427 SMLoc getEndLoc() const { return EndLoc; }
428428
429429 ARMCC::CondCodes getCondCode() const {
430 assert(Kind == CondCode && "Invalid access!");
430 assert(Kind == k_CondCode && "Invalid access!");
431431 return CC.Val;
432432 }
433433
434434 unsigned getCoproc() const {
435 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
435 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
436436 return Cop.Val;
437437 }
438438
439439 StringRef getToken() const {
440 assert(Kind == Token && "Invalid access!");
440 assert(Kind == k_Token && "Invalid access!");
441441 return StringRef(Tok.Data, Tok.Length);
442442 }
443443
444444 unsigned getReg() const {
445 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
445 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
446446 return Reg.RegNum;
447447 }
448448
449449 const SmallVectorImpl &getRegList() const {
450 assert((Kind == RegisterList || Kind == DPRRegisterList ||
451 Kind == SPRRegisterList) && "Invalid access!");
450 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
451 Kind == k_SPRRegisterList) && "Invalid access!");
452452 return Registers;
453453 }
454454
455455 const MCExpr *getImm() const {
456 assert(Kind == Immediate && "Invalid access!");
456 assert(Kind == k_Immediate && "Invalid access!");
457457 return Imm.Val;
458458 }
459459
460460 unsigned getFPImm() const {
461 assert(Kind == FPImmediate && "Invalid access!");
461 assert(Kind == k_FPImmediate && "Invalid access!");
462462 return FPImm.Val;
463463 }
464464
465465 ARM_MB::MemBOpt getMemBarrierOpt() const {
466 assert(Kind == MemBarrierOpt && "Invalid access!");
466 assert(Kind == k_MemBarrierOpt && "Invalid access!");
467467 return MBOpt.Val;
468468 }
469469
470470 ARM_PROC::IFlags getProcIFlags() const {
471 assert(Kind == ProcIFlags && "Invalid access!");
471 assert(Kind == k_ProcIFlags && "Invalid access!");
472472 return IFlags.Val;
473473 }
474474
475475 unsigned getMSRMask() const {
476 assert(Kind == MSRMask && "Invalid access!");
476 assert(Kind == k_MSRMask && "Invalid access!");
477477 return MMask.Val;
478478 }
479479
480 bool isCoprocNum() const { return Kind == CoprocNum; }
481 bool isCoprocReg() const { return Kind == CoprocReg; }
482 bool isCondCode() const { return Kind == CondCode; }
483 bool isCCOut() const { return Kind == CCOut; }
484 bool isITMask() const { return Kind == ITCondMask; }
485 bool isITCondCode() const { return Kind == CondCode; }
486 bool isImm() const { return Kind == Immediate; }
487 bool isFPImm() const { return Kind == FPImmediate; }
480 bool isCoprocNum() const { return Kind == k_CoprocNum; }
481 bool isCoprocReg() const { return Kind == k_CoprocReg; }
482 bool isCondCode() const { return Kind == k_CondCode; }
483 bool isCCOut() const { return Kind == k_CCOut; }
484 bool isITMask() const { return Kind == k_ITCondMask; }
485 bool isITCondCode() const { return Kind == k_CondCode; }
486 bool isImm() const { return Kind == k_Immediate; }
487 bool isFPImm() const { return Kind == k_FPImmediate; }
488488 bool isImm8s4() const {
489 if (Kind != Immediate)
489 if (Kind != k_Immediate)
490490 return false;
491491 const MCConstantExpr *CE = dyn_cast(getImm());
492492 if (!CE) return false;
494494 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
495495 }
496496 bool isImm0_1020s4() const {
497 if (Kind != Immediate)
497 if (Kind != k_Immediate)
498498 return false;
499499 const MCConstantExpr *CE = dyn_cast(getImm());
500500 if (!CE) return false;
502502 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
503503 }
504504 bool isImm0_508s4() const {
505 if (Kind != Immediate)
505 if (Kind != k_Immediate)
506506 return false;
507507 const MCConstantExpr *CE = dyn_cast(getImm());
508508 if (!CE) return false;
510510 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
511511 }
512512 bool isImm0_255() const {
513 if (Kind != Immediate)
513 if (Kind != k_Immediate)
514514 return false;
515515 const MCConstantExpr *CE = dyn_cast(getImm());
516516 if (!CE) return false;
518518 return Value >= 0 && Value < 256;
519519 }
520520 bool isImm0_7() const {
521 if (Kind != Immediate)
521 if (Kind != k_Immediate)
522522 return false;
523523 const MCConstantExpr *CE = dyn_cast(getImm());
524524 if (!CE) return false;
526526 return Value >= 0 && Value < 8;
527527 }
528528 bool isImm0_15() const {
529 if (Kind != Immediate)
529 if (Kind != k_Immediate)
530530 return false;
531531 const MCConstantExpr *CE = dyn_cast(getImm());
532532 if (!CE) return false;
534534 return Value >= 0 && Value < 16;
535535 }
536536 bool isImm0_31() const {
537 if (Kind != Immediate)
537 if (Kind != k_Immediate)
538538 return false;
539539 const MCConstantExpr *CE = dyn_cast(getImm());
540540 if (!CE) return false;
542542 return Value >= 0 && Value < 32;
543543 }
544544 bool isImm1_16() const {
545 if (Kind != Immediate)
545 if (Kind != k_Immediate)
546546 return false;
547547 const MCConstantExpr *CE = dyn_cast(getImm());
548548 if (!CE) return false;
550550 return Value > 0 && Value < 17;
551551 }
552552 bool isImm1_32() const {
553 if (Kind != Immediate)
553 if (Kind != k_Immediate)
554554 return false;
555555 const MCConstantExpr *CE = dyn_cast(getImm());
556556 if (!CE) return false;
558558 return Value > 0 && Value < 33;
559559 }
560560 bool isImm0_65535() const {
561 if (Kind != Immediate)
561 if (Kind != k_Immediate)
562562 return false;
563563 const MCConstantExpr *CE = dyn_cast(getImm());
564564 if (!CE) return false;
566566 return Value >= 0 && Value < 65536;
567567 }
568568 bool isImm0_65535Expr() const {
569 if (Kind != Immediate)
569 if (Kind != k_Immediate)
570570 return false;
571571 const MCConstantExpr *CE = dyn_cast(getImm());
572572 // If it's not a constant expression, it'll generate a fixup and be
576576 return Value >= 0 && Value < 65536;
577577 }
578578 bool isImm24bit() const {
579 if (Kind != Immediate)
579 if (Kind != k_Immediate)
580580 return false;
581581 const MCConstantExpr *CE = dyn_cast(getImm());
582582 if (!CE) return false;
584584 return Value >= 0 && Value <= 0xffffff;
585585 }
586586 bool isImmThumbSR() const {
587 if (Kind != Immediate)
587 if (Kind != k_Immediate)
588588 return false;
589589 const MCConstantExpr *CE = dyn_cast(getImm());
590590 if (!CE) return false;
592592 return Value > 0 && Value < 33;
593593 }
594594 bool isPKHLSLImm() const {
595 if (Kind != Immediate)
595 if (Kind != k_Immediate)
596596 return false;
597597 const MCConstantExpr *CE = dyn_cast(getImm());
598598 if (!CE) return false;
600600 return Value >= 0 && Value < 32;
601601 }
602602 bool isPKHASRImm() const {
603 if (Kind != Immediate)
603 if (Kind != k_Immediate)
604604 return false;
605605 const MCConstantExpr *CE = dyn_cast(getImm());
606606 if (!CE) return false;
608608 return Value > 0 && Value <= 32;
609609 }
610610 bool isARMSOImm() const {
611 if (Kind != Immediate)
611 if (Kind != k_Immediate)
612612 return false;
613613 const MCConstantExpr *CE = dyn_cast(getImm());
614614 if (!CE) return false;
616616 return ARM_AM::getSOImmVal(Value) != -1;
617617 }
618618 bool isT2SOImm() const {
619 if (Kind != Immediate)
619 if (Kind != k_Immediate)
620620 return false;
621621 const MCConstantExpr *CE = dyn_cast(getImm());
622622 if (!CE) return false;
624624 return ARM_AM::getT2SOImmVal(Value) != -1;
625625 }
626626 bool isSetEndImm() const {
627 if (Kind != Immediate)
627 if (Kind != k_Immediate)
628628 return false;
629629 const MCConstantExpr *CE = dyn_cast(getImm());
630630 if (!CE) return false;
631631 int64_t Value = CE->getValue();
632632 return Value == 1 || Value == 0;
633633 }
634 bool isReg() const { return Kind == Register; }
635 bool isRegList() const { return Kind == RegisterList; }
636 bool isDPRRegList() const { return Kind == DPRRegisterList; }
637 bool isSPRRegList() const { return Kind == SPRRegisterList; }
638 bool isToken() const { return Kind == Token; }
639 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
640 bool isMemory() const { return Kind == Memory; }
641 bool isShifterImm() const { return Kind == ShifterImmediate; }
642 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
643 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
644 bool isRotImm() const { return Kind == RotateImmediate; }
645 bool isBitfield() const { return Kind == BitfieldDescriptor; }
646 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
634 bool isReg() const { return Kind == k_Register; }
635 bool isRegList() const { return Kind == k_RegisterList; }
636 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
637 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
638 bool isToken() const { return Kind == k_Token; }
639 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
640 bool isMemory() const { return Kind == k_Memory; }
641 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
642 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
643 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
644 bool isRotImm() const { return Kind == k_RotateImmediate; }
645 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
646 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
647647 bool isPostIdxReg() const {
648 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
648 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
649649 }
650650 bool isMemNoOffset() const {
651 if (Kind != Memory)
651 if (Kind != k_Memory)
652652 return false;
653653 // No offset of any kind.
654654 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
655655 }
656656 bool isAddrMode2() const {
657 if (Kind != Memory)
657 if (Kind != k_Memory)
658658 return false;
659659 // Check for register offset.
660660 if (Mem.OffsetRegNum) return true;
664664 return Val > -4096 && Val < 4096;
665665 }
666666 bool isAM2OffsetImm() const {
667 if (Kind != Immediate)
667 if (Kind != k_Immediate)
668668 return false;
669669 // Immediate offset in range [-4095, 4095].
670670 const MCConstantExpr *CE = dyn_cast(getImm());
673673 return Val > -4096 && Val < 4096;
674674 }
675675 bool isAddrMode3() const {
676 if (Kind != Memory)
676 if (Kind != k_Memory)
677677 return false;
678678 // No shifts are legal for AM3.
679679 if (Mem.ShiftType != ARM_AM::no_shift) return false;
685685 return Val > -256 && Val < 256;
686686 }
687687 bool isAM3Offset() const {
688 if (Kind != Immediate && Kind != PostIndexRegister)
689 return false;
690 if (Kind == PostIndexRegister)
688 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
689 return false;
690 if (Kind == k_PostIndexRegister)
691691 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
692692 // Immediate offset in range [-255, 255].
693693 const MCConstantExpr *CE = dyn_cast(getImm());
697697 return (Val > -256 && Val < 256) || Val == INT32_MIN;
698698 }
699699 bool isAddrMode5() const {
700 if (Kind != Memory)
700 if (Kind != k_Memory)
701701 return false;
702702 // Check for register offset.
703703 if (Mem.OffsetRegNum) return false;
708708 Val == INT32_MIN;
709709 }
710710 bool isMemTBB() const {
711 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
711 if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
712712 Mem.ShiftType != ARM_AM::no_shift)
713713 return false;
714714 return true;
715715 }
716716 bool isMemTBH() const {
717 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
717 if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
718718 Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm != 1)
719719 return false;
720720 return true;
721721 }
722722 bool isMemRegOffset() const {
723 if (Kind != Memory || !Mem.OffsetRegNum)
723 if (Kind != k_Memory || !Mem.OffsetRegNum)
724724 return false;
725725 return true;
726726 }
727727 bool isT2MemRegOffset() const {
728 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
728 if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative)
729729 return false;
730730 // Only lsl #{0, 1, 2, 3} allowed.
731731 if (Mem.ShiftType == ARM_AM::no_shift)
737737 bool isMemThumbRR() const {
738738 // Thumb reg+reg addressing is simple. Just two registers, a base and
739739 // an offset. No shifts, negations or any other complicating factors.
740 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
740 if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
741741 Mem.ShiftType != ARM_AM::no_shift)
742742 return false;
743743 return isARMLowRegister(Mem.BaseRegNum) &&
744744 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
745745 }
746746 bool isMemThumbRIs4() const {
747 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
747 if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
748748 !isARMLowRegister(Mem.BaseRegNum))
749749 return false;
750750 // Immediate offset, multiple of 4 in range [0, 124].
753753 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
754754 }
755755 bool isMemThumbRIs2() const {
756 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
756 if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
757757 !isARMLowRegister(Mem.BaseRegNum))
758758 return false;
759759 // Immediate offset, multiple of 4 in range [0, 62].
762762 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
763763 }
764764 bool isMemThumbRIs1() const {
765 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
765 if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
766766 !isARMLowRegister(Mem.BaseRegNum))
767767 return false;
768768 // Immediate offset in range [0, 31].
771771 return Val >= 0 && Val <= 31;
772772 }
773773 bool isMemThumbSPI() const {
774 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
774 if (Kind != k_Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
775775 return false;
776776 // Immediate offset, multiple of 4 in range [0, 1020].
777777 if (!Mem.OffsetImm) return true;
779779 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
780780 }
781781 bool isMemImm8s4Offset() const {
782 if (Kind != Memory || Mem.OffsetRegNum != 0)
782 if (Kind != k_Memory || Mem.OffsetRegNum != 0)
783783 return false;
784784 // Immediate offset a multiple of 4 in range [-1020, 1020].
785785 if (!Mem.OffsetImm) return true;
787787 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
788788 }
789789 bool isMemImm0_1020s4Offset() const {
790 if (Kind != Memory || Mem.OffsetRegNum != 0)
790 if (Kind != k_Memory || Mem.OffsetRegNum != 0)
791791 return false;
792792 // Immediate offset a multiple of 4 in range [0, 1020].
793793 if (!Mem.OffsetImm) return true;
795795 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
796796 }
797797 bool isMemImm8Offset() const {
798 if (Kind != Memory || Mem.OffsetRegNum != 0)
798 if (Kind != k_Memory || Mem.OffsetRegNum != 0)
799799 return false;
800800 // Immediate offset in range [-255, 255].
801801 if (!Mem.OffsetImm) return true;
803803 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
804804 }
805805 bool isMemPosImm8Offset() const {
806 if (Kind != Memory || Mem.OffsetRegNum != 0)
806 if (Kind != k_Memory || Mem.OffsetRegNum != 0)
807807 return false;
808808 // Immediate offset in range [0, 255].
809809 if (!Mem.OffsetImm) return true;
811811 return Val >= 0 && Val < 256;
812812 }
813813 bool isMemNegImm8Offset() const {
814 if (Kind != Memory || Mem.OffsetRegNum != 0)
814 if (Kind != k_Memory || Mem.OffsetRegNum != 0)
815815 return false;
816816 // Immediate offset in range [-255, -1].
817817 if (!Mem.OffsetImm) return true;
822822 // If we have an immediate that's not a constant, treat it as a label
823823 // reference needing a fixup. If it is a constant, it's something else
824824 // and we reject it.
825 if (Kind == Immediate && !isa(getImm()))
825 if (Kind == k_Immediate && !isa(getImm()))
826826 return true;
827827
828 if (Kind != Memory || Mem.OffsetRegNum != 0)
828 if (Kind != k_Memory || Mem.OffsetRegNum != 0)
829829 return false;
830830 // Immediate offset in range [0, 4095].
831831 if (!Mem.OffsetImm) return true;
836836 // If we have an immediate that's not a constant, treat it as a label
837837 // reference needing a fixup. If it is a constant, it's something else
838838 // and we reject it.
839 if (Kind == Immediate && !isa(getImm()))
839 if (Kind == k_Immediate && !isa(getImm()))
840840 return true;
841841
842 if (Kind != Memory || Mem.OffsetRegNum != 0)
842 if (Kind != k_Memory || Mem.OffsetRegNum != 0)
843843 return false;
844844 // Immediate offset in range [-4095, 4095].
845845 if (!Mem.OffsetImm) return true;
847847 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
848848 }
849849 bool isPostIdxImm8() const {
850 if (Kind != Immediate)
850 if (Kind != k_Immediate)
851851 return false;
852852 const MCConstantExpr *CE = dyn_cast(getImm());
853853 if (!CE) return false;
855855 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
856856 }
857857
858 bool isMSRMask() const { return Kind == MSRMask; }
859 bool isProcIFlags() const { return Kind == ProcIFlags; }
858 bool isMSRMask() const { return Kind == k_MSRMask; }
859 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
860860
861861 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
862862 // Add as immediates when possible. Null MCExpr = 0.
11491149
11501150 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
11511151 assert(N == 2 && "Invalid number of operands!");
1152 if (Kind == PostIndexRegister) {
1152 if (Kind == k_PostIndexRegister) {
11531153 int32_t Val =
11541154 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
11551155 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
12151215 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
12161216 assert(N == 2 && "Invalid number of operands!");
12171217 // If this is an immediate, it's a label reference.
1218 if (Kind == Immediate) {
1218 if (Kind == k_Immediate) {
12191219 addExpr(Inst, getImm());
12201220 Inst.addOperand(MCOperand::CreateImm(0));
12211221 return;
12301230 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
12311231 assert(N == 2 && "Invalid number of operands!");
12321232 // If this is an immediate, it's a label reference.
1233 if (Kind == Immediate) {
1233 if (Kind == k_Immediate) {
12341234 addExpr(Inst, getImm());
12351235 Inst.addOperand(MCOperand::CreateImm(0));
12361236 return;
13451345 virtual void print(raw_ostream &OS) const;
13461346
13471347 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1348 ARMOperand *Op = new ARMOperand(ITCondMask);
1348 ARMOperand *Op = new ARMOperand(k_ITCondMask);
13491349 Op->ITMask.Mask = Mask;
13501350 Op->StartLoc = S;
13511351 Op->EndLoc = S;
13531353 }
13541354
13551355 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1356 ARMOperand *Op = new ARMOperand(CondCode);
1356 ARMOperand *Op = new ARMOperand(k_CondCode);
13571357 Op->CC.Val = CC;
13581358 Op->StartLoc = S;
13591359 Op->EndLoc = S;
13611361 }
13621362
13631363 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1364 ARMOperand *Op = new ARMOperand(CoprocNum);
1364 ARMOperand *Op = new ARMOperand(k_CoprocNum);
13651365 Op->Cop.Val = CopVal;
13661366 Op->StartLoc = S;
13671367 Op->EndLoc = S;
13691369 }
13701370
13711371 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1372 ARMOperand *Op = new ARMOperand(CoprocReg);
1372 ARMOperand *Op = new ARMOperand(k_CoprocReg);
13731373 Op->Cop.Val = CopVal;
13741374 Op->StartLoc = S;
13751375 Op->EndLoc = S;
13771377 }
13781378
13791379 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1380 ARMOperand *Op = new ARMOperand(CCOut);
1380 ARMOperand *Op = new ARMOperand(k_CCOut);
13811381 Op->Reg.RegNum = RegNum;
13821382 Op->StartLoc = S;
13831383 Op->EndLoc = S;
13851385 }
13861386
13871387 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1388 ARMOperand *Op = new ARMOperand(Token);
1388 ARMOperand *Op = new ARMOperand(k_Token);
13891389 Op->Tok.Data = Str.data();
13901390 Op->Tok.Length = Str.size();
13911391 Op->StartLoc = S;
13941394 }
13951395
13961396 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1397 ARMOperand *Op = new ARMOperand(Register);
1397 ARMOperand *Op = new ARMOperand(k_Register);
13981398 Op->Reg.RegNum = RegNum;
13991399 Op->StartLoc = S;
14001400 Op->EndLoc = E;
14061406 unsigned ShiftReg,
14071407 unsigned ShiftImm,
14081408 SMLoc S, SMLoc E) {
1409 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1409 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
14101410 Op->RegShiftedReg.ShiftTy = ShTy;
14111411 Op->RegShiftedReg.SrcReg = SrcReg;
14121412 Op->RegShiftedReg.ShiftReg = ShiftReg;
14201420 unsigned SrcReg,
14211421 unsigned ShiftImm,
14221422 SMLoc S, SMLoc E) {
1423 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1423 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
14241424 Op->RegShiftedImm.ShiftTy = ShTy;
14251425 Op->RegShiftedImm.SrcReg = SrcReg;
14261426 Op->RegShiftedImm.ShiftImm = ShiftImm;
14311431
14321432 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
14331433 SMLoc S, SMLoc E) {
1434 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1434 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
14351435 Op->ShifterImm.isASR = isASR;
14361436 Op->ShifterImm.Imm = Imm;
14371437 Op->StartLoc = S;
14401440 }
14411441
14421442 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1443 ARMOperand *Op = new ARMOperand(RotateImmediate);
1443 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
14441444 Op->RotImm.Imm = Imm;
14451445 Op->StartLoc = S;
14461446 Op->EndLoc = E;
14491449
14501450 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
14511451 SMLoc S, SMLoc E) {
1452 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1452 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
14531453 Op->Bitfield.LSB = LSB;
14541454 Op->Bitfield.Width = Width;
14551455 Op->StartLoc = S;
14601460 static ARMOperand *
14611461 CreateRegList(const SmallVectorImpl > &Regs,
14621462 SMLoc StartLoc, SMLoc EndLoc) {
1463 KindTy Kind = RegisterList;
1463 KindTy Kind = k_RegisterList;
14641464
14651465 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1466 Kind = DPRRegisterList;
1466 Kind = k_DPRRegisterList;
14671467 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
14681468 contains(Regs.front().first))
1469 Kind = SPRRegisterList;
1469 Kind = k_SPRRegisterList;
14701470
14711471 ARMOperand *Op = new ARMOperand(Kind);
14721472 for (SmallVectorImpl >::const_iterator
14791479 }
14801480
14811481 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1482 ARMOperand *Op = new ARMOperand(Immediate);
1482 ARMOperand *Op = new ARMOperand(k_Immediate);
14831483 Op->Imm.Val = Val;
14841484 Op->StartLoc = S;
14851485 Op->EndLoc = E;
14871487 }
14881488
14891489 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1490 ARMOperand *Op = new ARMOperand(FPImmediate);
1490 ARMOperand *Op = new ARMOperand(k_FPImmediate);
14911491 Op->FPImm.Val = Val;
14921492 Op->StartLoc = S;
14931493 Op->EndLoc = S;
15011501 unsigned ShiftImm,
15021502 bool isNegative,
15031503 SMLoc S, SMLoc E) {
1504 ARMOperand *Op = new ARMOperand(Memory);
1504 ARMOperand *Op = new ARMOperand(k_Memory);
15051505 Op->Mem.BaseRegNum = BaseRegNum;
15061506 Op->Mem.OffsetImm = OffsetImm;
15071507 Op->Mem.OffsetRegNum = OffsetRegNum;
15171517 ARM_AM::ShiftOpc ShiftTy,
15181518 unsigned ShiftImm,
15191519 SMLoc S, SMLoc E) {
1520 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1520 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
15211521 Op->PostIdxReg.RegNum = RegNum;
15221522 Op->PostIdxReg.isAdd = isAdd;
15231523 Op->PostIdxReg.ShiftTy = ShiftTy;
15281528 }
15291529
15301530 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1531 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1531 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
15321532 Op->MBOpt.Val = Opt;
15331533 Op->StartLoc = S;
15341534 Op->EndLoc = S;
15361536 }
15371537
15381538 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1539 ARMOperand *Op = new ARMOperand(ProcIFlags);
1539 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
15401540 Op->IFlags.Val = IFlags;
15411541 Op->StartLoc = S;
15421542 Op->EndLoc = S;
15441544 }
15451545
15461546 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1547 ARMOperand *Op = new ARMOperand(MSRMask);
1547 ARMOperand *Op = new ARMOperand(k_MSRMask);
15481548 Op->MMask.Val = MMask;
15491549 Op->StartLoc = S;
15501550 Op->EndLoc = S;
15561556
15571557 void ARMOperand::print(raw_ostream &OS) const {
15581558 switch (Kind) {
1559 case FPImmediate:
1559 case k_FPImmediate:
15601560 OS << "
15611561 << ") >";
15621562 break;
1563 case CondCode:
1563 case k_CondCode:
15641564 OS << "";
15651565 break;
1566 case CCOut:
1566 case k_CCOut:
15671567 OS << "";
15681568 break;
1569 case ITCondMask: {
1569 case k_ITCondMask: {
15701570 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
15711571 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
15721572 "(tee)", "(eee)" };
15741574 OS << "";
15751575 break;
15761576 }
1577 case CoprocNum:
1577 case k_CoprocNum:
15781578 OS << "";
15791579 break;
1580 case CoprocReg:
1580 case k_CoprocReg:
15811581 OS << "";
15821582 break;
1583 case MSRMask:
1583 case k_MSRMask:
15841584 OS << "";
15851585 break;
1586 case Immediate:
1586 case k_Immediate:
15871587 getImm()->print(OS);
15881588 break;
1589 case MemBarrierOpt:
1589 case k_MemBarrierOpt:
15901590 OS << "";
15911591 break;
1592 case Memory:
1592 case k_Memory:
15931593 OS << "
15941594 << " base:" << Mem.BaseRegNum;
15951595 OS << ">";
15961596 break;
1597 case PostIndexRegister:
1597 case k_PostIndexRegister:
15981598 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
15991599 << PostIdxReg.RegNum;
16001600 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
16021602 << PostIdxReg.ShiftImm;
16031603 OS << ">";
16041604 break;
1605 case ProcIFlags: {
1605 case k_ProcIFlags: {
16061606 OS << "
16071607 unsigned IFlags = getProcIFlags();
16081608 for (int i=2; i >= 0; --i)
16111611 OS << ">";
16121612 break;
16131613 }
1614 case Register:
1614 case k_Register:
16151615 OS << "";
16161616 break;
1617 case ShifterImmediate:
1617 case k_ShifterImmediate:
16181618 OS << "
16191619 << " #" << ShifterImm.Imm << ">";
16201620 break;
1621 case ShiftedRegister:
1621 case k_ShiftedRegister:
16221622 OS << "
16231623 << RegShiftedReg.SrcReg
16241624 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
16261626 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
16271627 << ">";
16281628 break;
1629 case ShiftedImmediate:
1629 case k_ShiftedImmediate:
16301630 OS << "
16311631 << RegShiftedImm.SrcReg
16321632 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
16331633 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
16341634 << ">";
16351635 break;
1636 case RotateImmediate:
1636 case k_RotateImmediate:
16371637 OS << "";
16381638 break;
1639 case BitfieldDescriptor:
1639 case k_BitfieldDescriptor:
16401640 OS << "
16411641 << ", width: " << Bitfield.Width << ">";
16421642 break;
1643 case RegisterList:
1644 case DPRRegisterList:
1645 case SPRRegisterList: {
1643 case k_RegisterList:
1644 case k_DPRRegisterList:
1645 case k_SPRRegisterList: {
16461646 OS << "
16471647
16481648 const SmallVectorImpl &RegList = getRegList();
16551655 OS << ">";
16561656 break;
16571657 }
1658 case Token:
1658 case k_Token:
16591659 OS << "'" << getToken() << "'";
16601660 break;
16611661 }
36393639 // ARM mode 'blx' need special handling, as the register operand version
36403640 // is predicable, but the label operand version is not. So, we can't rely
36413641 // on the Mnemonic based checking to correctly figure out when to put
3642 // a CondCode operand in the list. If we're trying to match the label
3643 // version, remove the CondCode operand here.
3642 // a k_CondCode operand in the list. If we're trying to match the label
3643 // version, remove the k_CondCode operand here.
36443644 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
36453645 static_cast(Operands[2])->isImm()) {
36463646 ARMOperand *Op = static_cast(Operands[1]);