llvm.org GIT mirror llvm / 21aabda
Don't punish vectorized arithmetic instruction whose type will be split to multiple registers Currently in LLVM's cost model, a vectorized arithmetic instruction will have high cost if its type is split into multiple registers. However, this punishment is too heavy and unnecessary. The overhead of the split should not be on arithmetic instructions but instructions that implement the split. Note that during vectorization we have calculated the register pressure, and we only choose proper interleaving factor (and also vectorization factor) so that we don't use more registers than the maximum number. Here is a very simple example: if a vadd has the cost 1, and if we double VF so that we need two registers to perform it, then its cost will become 4 with the current implementation, which will prevent us to use larger VF. Differential revision: http://reviews.llvm.org/D15159 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254671 91177308-0d34-0410-b5e6-96231b3b80d8 Cong Hou 4 years ago
2 changed file(s) with 2 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
301301
302302 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
303303 // The operation is legal. Assume it costs 1.
304 // If the type is split to multiple registers, assume that there is some
305 // overhead to this.
306304 // TODO: Once we have extract/insert subvector cost we need to use them.
307 if (LT.first > 1)
308 return LT.first * 2 * OpCost;
309 return LT.first * 1 * OpCost;
305 return LT.first * OpCost;
310306 }
311307
312308 if (!TLI->isOperationExpand(ISD, LT.second)) {
3232 %bin.rdx.3 = add <8 x i32> %bin.rdx.2, %rdx.shuf.3
3333
3434 ; CHECK-LABEL: reduction_cost_int
35 ; CHECK: cost of 23 {{.*}} extractelement
35 ; CHECK: cost of 17 {{.*}} extractelement
3636
3737 %r = extractelement <8 x i32> %bin.rdx.3, i32 0
3838 ret i32 %r