llvm.org GIT mirror llvm / 21886a4
[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers. Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8 Venkatraman Govindaraju 6 years ago
3 changed file(s) with 24 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
1919 #include "llvm/CodeGen/MachineFunction.h"
2020 #include "llvm/CodeGen/MachineInstrBuilder.h"
2121 #include "llvm/IR/Type.h"
22 #include "llvm/Support/CommandLine.h"
2223 #include "llvm/Support/ErrorHandling.h"
2324 #include "llvm/Target/TargetInstrInfo.h"
2425
2627 #include "SparcGenRegisterInfo.inc"
2728
2829 using namespace llvm;
30
31 static cl::opt
32 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
33 cl::desc("Reserve application registers (%g2-%g4)"));
2934
3035 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
3136 const TargetInstrInfo &tii)
4247 BitVector Reserved(getNumRegs());
4348 // FIXME: G1 reserved for now for large imm generation by frame code.
4449 Reserved.set(SP::G1);
45 Reserved.set(SP::G2);
46 Reserved.set(SP::G3);
47 Reserved.set(SP::G4);
50
51 //G1-G4 can be used in applications.
52 if (ReserveAppRegisters) {
53 Reserved.set(SP::G2);
54 Reserved.set(SP::G3);
55 Reserved.set(SP::G4);
56 }
57 //G5 is not reserved in 64 bit mode.
58 if (!Subtarget.is64Bit())
59 Reserved.set(SP::G5);
60
4861 Reserved.set(SP::O6);
4962 Reserved.set(SP::I6);
5063 Reserved.set(SP::I7);
5164 Reserved.set(SP::G0);
52 Reserved.set(SP::G5);
5365 Reserved.set(SP::G6);
5466 Reserved.set(SP::G7);
5567 return Reserved;
143143 // register class for that. The i64 type is included here to allow i64 patterns
144144 // using the integer instructions.
145145 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
146 (add L0, L1, L2, L3, L4, L5, L6,
147 L7, I0, I1, I2, I3, I4, I5,
146 (add I0, I1, I2, I3, I4, I5,
147 G1,
148 G2, G3, G4, // OK for use only in
149 // applications, not libraries.
150 G5, // OK for use in 64 bit mode.
151 L0, L1, L2, L3, L4, L5, L6, L7,
148152 O0, O1, O2, O3, O4, O5, O7,
149 G1,
150153 // Non-allocatable regs:
151 G2, G3, G4, // FIXME: OK for use only in
152 // applications, not libraries.
153154 O6, // stack ptr
154155 I6, // frame ptr
155156 I7, // return address
156157 G0, // constant zero
157 G5, G6, G7 // reserved for kernel
158 G6, G7 // reserved for kernel
158159 )>;
159160
160161 // Register class for 64-bit mode, with a 64-bit spill slot size.
9696 ;CHECK-NEXT: nop
9797 %0 = add nsw i32 %i0, 2
9898 %1 = add nsw i32 %i0, 3
99 tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4}"(i32 %0, i32 %1)
99 tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o6},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7}"(i32 %0, i32 %1)
100100 %2 = add nsw i32 %0, %1
101101 %3 = tail call i32 @bar(i32 %2)
102102 ret i32 %3