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[ARM] Some DAG combine tests Add some more and and shift load combine tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320822 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Parker 2 years ago
2 changed file(s) with 210 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
963963 %and = and i32 %or, 65535
964964 ret i32 %and
965965 }
966
967 define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
968 ; ARM-LABEL: test6:
969 ; ARM: @ %bb.0: @ %entry
970 ; ARM-NEXT: ldrb r0, [r0]
971 ; ARM-NEXT: uxtb r2, r2
972 ; ARM-NEXT: and r0, r0, r1
973 ; ARM-NEXT: uxtb r1, r0
974 ; ARM-NEXT: mov r0, #0
975 ; ARM-NEXT: cmp r1, r2
976 ; ARM-NEXT: movweq r0, #1
977 ; ARM-NEXT: bx lr
978 ;
979 ; ARMEB-LABEL: test6:
980 ; ARMEB: @ %bb.0: @ %entry
981 ; ARMEB-NEXT: ldrb r0, [r0]
982 ; ARMEB-NEXT: uxtb r2, r2
983 ; ARMEB-NEXT: and r0, r0, r1
984 ; ARMEB-NEXT: uxtb r1, r0
985 ; ARMEB-NEXT: mov r0, #0
986 ; ARMEB-NEXT: cmp r1, r2
987 ; ARMEB-NEXT: movweq r0, #1
988 ; ARMEB-NEXT: bx lr
989 ;
990 ; THUMB1-LABEL: test6:
991 ; THUMB1: @ %bb.0: @ %entry
992 ; THUMB1-NEXT: ldrb r0, [r0]
993 ; THUMB1-NEXT: ands r0, r1
994 ; THUMB1-NEXT: uxtb r3, r0
995 ; THUMB1-NEXT: uxtb r2, r2
996 ; THUMB1-NEXT: movs r0, #1
997 ; THUMB1-NEXT: movs r1, #0
998 ; THUMB1-NEXT: cmp r3, r2
999 ; THUMB1-NEXT: beq .LBB18_2
1000 ; THUMB1-NEXT: @ %bb.1: @ %entry
1001 ; THUMB1-NEXT: mov r0, r1
1002 ; THUMB1-NEXT: .LBB18_2: @ %entry
1003 ; THUMB1-NEXT: bx lr
1004 ;
1005 ; THUMB2-LABEL: test6:
1006 ; THUMB2: @ %bb.0: @ %entry
1007 ; THUMB2-NEXT: ldrb r0, [r0]
1008 ; THUMB2-NEXT: uxtb r2, r2
1009 ; THUMB2-NEXT: ands r0, r1
1010 ; THUMB2-NEXT: uxtb r1, r0
1011 ; THUMB2-NEXT: movs r0, #0
1012 ; THUMB2-NEXT: cmp r1, r2
1013 ; THUMB2-NEXT: it eq
1014 ; THUMB2-NEXT: moveq r0, #1
1015 ; THUMB2-NEXT: bx lr
1016 entry:
1017 %0 = load i8, i8* %x, align 4
1018 %1 = and i8 %0, %y
1019 %2 = icmp eq i8 %1, %z
1020 ret i1 %2
1021 }
1022
1023 define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
1024 ; ARM-LABEL: test7:
1025 ; ARM: @ %bb.0: @ %entry
1026 ; ARM-NEXT: ldrh r0, [r0]
1027 ; ARM-NEXT: uxtb r2, r2
1028 ; ARM-NEXT: and r0, r0, r1
1029 ; ARM-NEXT: uxtb r1, r0
1030 ; ARM-NEXT: mov r0, #0
1031 ; ARM-NEXT: cmp r1, r2
1032 ; ARM-NEXT: movweq r0, #1
1033 ; ARM-NEXT: bx lr
1034 ;
1035 ; ARMEB-LABEL: test7:
1036 ; ARMEB: @ %bb.0: @ %entry
1037 ; ARMEB-NEXT: ldrh r0, [r0]
1038 ; ARMEB-NEXT: uxtb r2, r2
1039 ; ARMEB-NEXT: and r0, r0, r1
1040 ; ARMEB-NEXT: uxtb r1, r0
1041 ; ARMEB-NEXT: mov r0, #0
1042 ; ARMEB-NEXT: cmp r1, r2
1043 ; ARMEB-NEXT: movweq r0, #1
1044 ; ARMEB-NEXT: bx lr
1045 ;
1046 ; THUMB1-LABEL: test7:
1047 ; THUMB1: @ %bb.0: @ %entry
1048 ; THUMB1-NEXT: ldrh r0, [r0]
1049 ; THUMB1-NEXT: ands r0, r1
1050 ; THUMB1-NEXT: uxtb r3, r0
1051 ; THUMB1-NEXT: uxtb r2, r2
1052 ; THUMB1-NEXT: movs r0, #1
1053 ; THUMB1-NEXT: movs r1, #0
1054 ; THUMB1-NEXT: cmp r3, r2
1055 ; THUMB1-NEXT: beq .LBB19_2
1056 ; THUMB1-NEXT: @ %bb.1: @ %entry
1057 ; THUMB1-NEXT: mov r0, r1
1058 ; THUMB1-NEXT: .LBB19_2: @ %entry
1059 ; THUMB1-NEXT: bx lr
1060 ;
1061 ; THUMB2-LABEL: test7:
1062 ; THUMB2: @ %bb.0: @ %entry
1063 ; THUMB2-NEXT: ldrh r0, [r0]
1064 ; THUMB2-NEXT: uxtb r2, r2
1065 ; THUMB2-NEXT: ands r0, r1
1066 ; THUMB2-NEXT: uxtb r1, r0
1067 ; THUMB2-NEXT: movs r0, #0
1068 ; THUMB2-NEXT: cmp r1, r2
1069 ; THUMB2-NEXT: it eq
1070 ; THUMB2-NEXT: moveq r0, #1
1071 ; THUMB2-NEXT: bx lr
1072 entry:
1073 %0 = load i16, i16* %x, align 4
1074 %1 = and i16 %0, %y
1075 %2 = trunc i16 %1 to i8
1076 %3 = icmp eq i8 %2, %z
1077 ret i1 %3
1078 }
1079
1080 define arm_aapcscc void @test8(i32* nocapture %p) {
1081 ; ARM-LABEL: test8:
1082 ; ARM: @ %bb.0: @ %entry
1083 ; ARM-NEXT: ldr r1, [r0]
1084 ; ARM-NEXT: mvn r1, r1
1085 ; ARM-NEXT: uxtb r1, r1
1086 ; ARM-NEXT: str r1, [r0]
1087 ; ARM-NEXT: bx lr
1088 ;
1089 ; ARMEB-LABEL: test8:
1090 ; ARMEB: @ %bb.0: @ %entry
1091 ; ARMEB-NEXT: ldr r1, [r0]
1092 ; ARMEB-NEXT: mvn r1, r1
1093 ; ARMEB-NEXT: uxtb r1, r1
1094 ; ARMEB-NEXT: str r1, [r0]
1095 ; ARMEB-NEXT: bx lr
1096 ;
1097 ; THUMB1-LABEL: test8:
1098 ; THUMB1: @ %bb.0: @ %entry
1099 ; THUMB1-NEXT: ldr r1, [r0]
1100 ; THUMB1-NEXT: movs r2, #255
1101 ; THUMB1-NEXT: bics r2, r1
1102 ; THUMB1-NEXT: str r2, [r0]
1103 ; THUMB1-NEXT: bx lr
1104 ;
1105 ; THUMB2-LABEL: test8:
1106 ; THUMB2: @ %bb.0: @ %entry
1107 ; THUMB2-NEXT: ldr r1, [r0]
1108 ; THUMB2-NEXT: mvns r1, r1
1109 ; THUMB2-NEXT: uxtb r1, r1
1110 ; THUMB2-NEXT: str r1, [r0]
1111 ; THUMB2-NEXT: bx lr
1112 entry:
1113 %0 = load i32, i32* %p, align 4
1114 %neg = and i32 %0, 255
1115 %and = xor i32 %neg, 255
1116 store i32 %and, i32* %p, align 4
1117 ret void
1118 }
216216 ret i32 %conv
217217 }
218218
219 ; CHECK-LABEL: test_shift8_mask8
220 ; CHECK-BE: ldr r1, [r0]
221 ; CHECK-COMMON: ldr r1, [r0]
222 ; CHECK-COMMON: ubfx r1, r1, #8, #8
223 ; CHECK-COMMON: str r1, [r0]
224 define arm_aapcscc void @test_shift8_mask8(i32* nocapture %p) {
225 entry:
226 %0 = load i32, i32* %p, align 4
227 %shl = lshr i32 %0, 8
228 %and = and i32 %shl, 255
229 store i32 %and, i32* %p, align 4
230 ret void
231 }
232
233 ; CHECK-LABEL: test_shift8_mask16
234 ; CHECK-BE: ldr r1, [r0]
235 ; CHECK-COMMON: ldr r1, [r0]
236 ; CHECK-COMMON: ubfx r1, r1, #8, #16
237 ; CHECK-COMMON: str r1, [r0]
238 define arm_aapcscc void @test_shift8_mask16(i32* nocapture %p) {
239 entry:
240 %0 = load i32, i32* %p, align 4
241 %shl = lshr i32 %0, 8
242 %and = and i32 %shl, 65535
243 store i32 %and, i32* %p, align 4
244 ret void
245 }
246
247 ; CHECK-LABEL: test_shift8_mask16
248 ; CHECK-BE: ldrb r0, [r0]
249 ; CHECK-COMMON: ldrb r0, [r0, #1]
250 ; CHECK-COMMON: str r0, [r1]
251 define arm_aapcscc void @test_sext_shift8_mask8(i16* %p, i32* %q) {
252 entry:
253 %0 = load i16, i16* %p, align 4
254 %1 = sext i16 %0 to i32
255 %shl = lshr i32 %1, 8
256 %and = and i32 %shl, 255
257 store i32 %and, i32* %q, align 4
258 ret void
259 }
260
261 ; CHECK-LABEL: test_shift8_mask16
262 ; CHECK-ARM: ldrsh r0, [r0]
263 ; CHECK-BE: ldrsh r0, [r0]
264 ; CHECK-THUMB: ldrsh.w r0, [r0]
265 ; CHECK-COMMON: ubfx r0, r0, #8, #16
266 ; CHECK-COMMON: str r0, [r1]
267 define arm_aapcscc void @test_sext_shift8_mask16(i16* %p, i32* %q) {
268 entry:
269 %0 = load i16, i16* %p, align 4
270 %1 = sext i16 %0 to i32
271 %shl = lshr i32 %1, 8
272 %and = and i32 %shl, 65535
273 store i32 %and, i32* %q, align 4
274 ret void
275 }