llvm.org GIT mirror llvm / 20d1cb1
[ARM] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313823 91177308-0d34-0410-b5e6-96231b3b80d8 Eugene Zelenko 2 years ago
17 changed file(s) with 467 addition(s) and 244 deletion(s). Raw diff Collapse all Expand all
None //===-- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering -----------===//
0 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 ///
8 //
99 /// \file
1010 /// This file implements the lowering of LLVM calls to machine code calls for
1111 /// GlobalISel.
12 ///
12 //
1313 //===----------------------------------------------------------------------===//
1414
1515 #include "ARMCallLowering.h"
16
1716 #include "ARMBaseInstrInfo.h"
1817 #include "ARMISelLowering.h"
1918 #include "ARMSubtarget.h"
20
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
2121 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
2223 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2324 #include "llvm/CodeGen/GlobalISel/Utils.h"
25 #include "llvm/CodeGen/LowLevelType.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
2432 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/MachineValueType.h"
34 #include "llvm/CodeGen/ValueTypes.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/IR/Value.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/LowLevelTypeImpl.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetSubtargetInfo.h"
45 #include
46 #include
47 #include
48 #include
2549
2650 using namespace llvm;
2751
5882 }
5983
6084 namespace {
85
6186 /// Helper class for values going out through an ABI boundary (used for handling
6287 /// function return values and call parameters).
6388 struct OutgoingValueHandler : public CallLowering::ValueHandler {
6489 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
6590 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
66 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), StackSize(0) {}
91 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
6792
6893 unsigned getStackAddress(uint64_t Size, int64_t Offset,
6994 MachinePointerInfo &MPO) override {
152177 }
153178
154179 MachineInstrBuilder &MIB;
155 uint64_t StackSize;
180 uint64_t StackSize = 0;
156181 };
157 } // End anonymous namespace.
182
183 } // end anonymous namespace
158184
159185 void ARMCallLowering::splitToValueTypes(
160186 const ArgInfo &OrigArg, SmallVectorImpl &SplitArgs,
258284 }
259285
260286 namespace {
287
261288 /// Helper class for values coming in through an ABI boundary (used for handling
262289 /// formal arguments and call return values).
263290 struct IncomingValueHandler : public CallLowering::ValueHandler {
370397 MIRBuilder.getMBB().addLiveIn(PhysReg);
371398 }
372399 };
373 } // End anonymous namespace
400
401 } // end anonymous namespace
374402
375403 bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
376404 const Function &F,
428456 }
429457
430458 namespace {
459
431460 struct CallReturnHandler : public IncomingValueHandler {
432461 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
433462 MachineInstrBuilder MIB, CCAssignFn *AssignFn)
439468
440469 MachineInstrBuilder MIB;
441470 };
442 } // End anonymous namespace.
471
472 } // end anonymous namespace
443473
444474 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
445475 CallingConv::ID CallConv,
None //===-- llvm/lib/Target/ARM/ARMCallLowering.h - Call lowering -------------===//
0 //===- llvm/lib/Target/ARM/ARMCallLowering.h - Call lowering ----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 ///
8 //
99 /// \file
1010 /// This file describes how to lower LLVM calls to machine code calls.
11 ///
11 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef LLVM_LIB_TARGET_ARM_ARMCALLLOWERING
15 #define LLVM_LIB_TARGET_ARM_ARMCALLLOWERING
14 #ifndef LLVM_LIB_TARGET_ARM_ARMCALLLOWERING_H
15 #define LLVM_LIB_TARGET_ARM_ARMCALLLOWERING_H
1616
17 #include "llvm/CodeGen/CallingConvLower.h"
17 #include "llvm/ADT/ArrayRef.h"
1818 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
19 #include "llvm/CodeGen/ValueTypes.h"
19 #include "llvm/IR/CallingConv.h"
20 #include
21 #include
2022
2123 namespace llvm {
2224
2325 class ARMTargetLowering;
26 class MachineFunction;
2427 class MachineInstrBuilder;
28 class MachineIRBuilder;
29 class Value;
2530
2631 class ARMCallLowering : public CallLowering {
2732 public:
4146 bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
4247 unsigned VReg, MachineInstrBuilder &Ret) const;
4348
44 typedef std::function SplitArgTy;
49 using SplitArgTy = std::function;
4550
4651 /// Split an argument into one or more arguments that the CC lowering can cope
4752 /// with (e.g. replace pointers with integers).
5055 MachineFunction &MF,
5156 const SplitArgTy &PerformArgSplit) const;
5257 };
53 } // End of namespace llvm
54 #endif
58
59 } // end namespace llvm
60
61 #endif // LLVM_LIB_TARGET_ARM_ARMCALLLOWERING_H
None //===-- ARMConstantIslandPass.cpp - ARM constant islands ------------------===//
0 //===- ARMConstantIslandPass.cpp - ARM constant islands -------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1919 #include "ARMSubtarget.h"
2020 #include "MCTargetDesc/ARMBaseInfo.h"
2121 #include "Thumb2InstrInfo.h"
22 #include "Utils/ARMBaseInfo.h"
2223 #include "llvm/ADT/DenseMap.h"
2324 #include "llvm/ADT/STLExtras.h"
2425 #include "llvm/ADT/SmallSet.h"
3637 #include "llvm/IR/DataLayout.h"
3738 #include "llvm/IR/DebugLoc.h"
3839 #include "llvm/MC/MCInstrDesc.h"
40 #include "llvm/Pass.h"
3941 #include "llvm/Support/CommandLine.h"
4042 #include "llvm/Support/Compiler.h"
4143 #include "llvm/Support/Debug.h"
4749 #include
4850 #include
4951 #include
50 #include
5152 #include
5253 #include
5354
106107 /// previous iteration by inserting unconditional branches.
107108 SmallSet NewWaterList;
108109
109 typedef std::vector::iterator water_iterator;
110 using water_iterator = std::vector::iterator;
110111
111112 /// CPUser - One user of a constant pool, keeping the machine instruction
112113 /// pointer, the constant pool being referenced, and the max displacement
127128 unsigned MaxDisp;
128129 bool NegOk;
129130 bool IsSoImm;
130 bool KnownAlignment;
131 bool KnownAlignment = false;
131132
132133 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
133134 bool neg, bool soimm)
134 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm),
135 KnownAlignment(false) {
135 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm) {
136136 HighWaterMark = CPEMI->getParent();
137137 }
138138
194194 };
195195
196196 /// ImmBranches - Keep track of all the immediate branch instructions.
197 ///
198197 std::vector ImmBranches;
199198
200199 /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
201 ///
202200 SmallVector PushPopMIs;
203201
204202 /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
289287 }
290288 };
291289
292 char ARMConstantIslands::ID = 0;
293
294290 } // end anonymous namespace
291
292 char ARMConstantIslands::ID = 0;
295293
296294 /// verify - check BBOffsets, BBSizes, alignment of islands
297295 void ARMConstantIslands::verify() {
628626
629627 /// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
630628 /// look up the corresponding CPEntry.
631 ARMConstantIslands::CPEntry
632 *ARMConstantIslands::findConstPoolEntry(unsigned CPI,
633 const MachineInstr *CPEMI) {
629 ARMConstantIslands::CPEntry *
630 ARMConstantIslands::findConstPoolEntry(unsigned CPI,
631 const MachineInstr *CPEMI) {
634632 std::vector &CPEs = CPEntries[CPI];
635633 // Number of entries per constpool index should be small, just do a
636634 // linear search.
11251123 /// and instruction CPEMI, and decrement its refcount. If the refcount
11261124 /// becomes 0 remove the entry and instruction. Returns true if we removed
11271125 /// the entry, false if we didn't.
1128
11291126 bool ARMConstantIslands::decrementCPEReferenceCount(unsigned CPI,
11301127 MachineInstr *CPEMI) {
11311128 // Find the old entry. Eliminate it if it is no longer used.
11531150 /// 0 = no existing entry found
11541151 /// 1 = entry found, and there were no code insertions or deletions
11551152 /// 2 = entry found, and there were code insertions or deletions
1156 int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset)
1157 {
1153 int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) {
11581154 MachineInstr *UserMI = U.MI;
11591155 MachineInstr *CPEMI = U.CPEMI;
11601156
None //===-- ARMConstantPoolValue.cpp - ARM constantpool value -----------------===//
0 //===- ARMConstantPoolValue.cpp - ARM constantpool value ------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1212
1313 #include "ARMConstantPoolValue.h"
1414 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringRef.h"
1615 #include "llvm/CodeGen/MachineBasicBlock.h"
1716 #include "llvm/IR/Constant.h"
1817 #include "llvm/IR/Constants.h"
None //===-- ARMConstantPoolValue.h - ARM constantpool value ---------*- C++ -*-===//
0 //===- ARMConstantPoolValue.h - ARM constantpool value ----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1313 #ifndef LLVM_LIB_TARGET_ARM_ARMCONSTANTPOOLVALUE_H
1414 #define LLVM_LIB_TARGET_ARM_ARMCONSTANTPOOLVALUE_H
1515
16 #include "llvm/ADT/SmallPtrSet.h"
1617 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/iterator_range.h"
1819 #include "llvm/CodeGen/MachineConstantPool.h"
1920 #include "llvm/Support/Casting.h"
2021 #include
2829 class GlobalVariable;
2930 class LLVMContext;
3031 class MachineBasicBlock;
32 class raw_ostream;
33 class Type;
3134
3235 namespace ARMCP {
3336
173176 const GlobalValue *getGV() const;
174177 const BlockAddress *getBlockAddress() const;
175178
176 typedef SmallPtrSet::iterator promoted_iterator;
179 using promoted_iterator = SmallPtrSet::iterator;
180
177181 iterator_range promotedGlobals() {
178182 return iterator_range(GVars.begin(), GVars.end());
179183 }
None //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
0 //===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
2222 #include "ARMSubtarget.h"
2323 #include "MCTargetDesc/ARMAddressingModes.h"
2424 #include "MCTargetDesc/ARMBaseInfo.h"
25 #include "Utils/ARMBaseInfo.h"
2526 #include "llvm/ADT/APFloat.h"
2627 #include "llvm/ADT/APInt.h"
2728 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
2929 #include "llvm/ADT/SmallVector.h"
3030 #include "llvm/CodeGen/CallingConvLower.h"
3131 #include "llvm/CodeGen/FastISel.h"
3232 #include "llvm/CodeGen/FunctionLoweringInfo.h"
3333 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
3435 #include "llvm/CodeGen/MachineConstantPool.h"
3536 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineFunction.h"
3638 #include "llvm/CodeGen/MachineInstr.h"
3739 #include "llvm/CodeGen/MachineInstrBuilder.h"
3840 #include "llvm/CodeGen/MachineMemOperand.h"
5759 #include "llvm/IR/Instruction.h"
5860 #include "llvm/IR/Instructions.h"
5961 #include "llvm/IR/IntrinsicInst.h"
62 #include "llvm/IR/Intrinsics.h"
6063 #include "llvm/IR/Module.h"
6164 #include "llvm/IR/Operator.h"
6265 #include "llvm/IR/Type.h"
7174 #include "llvm/Target/TargetInstrInfo.h"
7275 #include "llvm/Target/TargetLowering.h"
7376 #include "llvm/Target/TargetMachine.h"
77 #include "llvm/Target/TargetOpcodes.h"
7478 #include "llvm/Target/TargetOptions.h"
79 #include "llvm/Target/TargetRegisterInfo.h"
7580 #include
7681 #include
7782 #include
8186 namespace {
8287
8388 // All possible address modes, plus some.
84 typedef struct Address {
89 struct Address {
8590 enum {
8691 RegBase,
8792 FrameIndexBase
98103 Address() {
99104 Base.Reg = 0;
100105 }
101 } Address;
106 };
102107
103108 class ARMFastISel final : public FastISel {
104109 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
28892894 return false;
28902895 }
28912896
2892 namespace {
2893
28942897 // This table describes sign- and zero-extend instructions which can be
28952898 // folded into a preceding load. All of these extends have an immediate
28962899 // (sometimes a mask and sometimes a shift) that's applied after
28972900 // extension.
2898 const struct FoldableLoadExtendsStruct {
2901 static const struct FoldableLoadExtendsStruct {
28992902 uint16_t Opc[2]; // ARM, Thumb.
29002903 uint8_t ExpectedImm;
29012904 uint8_t isZExt : 1;
29072910 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
29082911 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
29092912 };
2910
2911 } // end anonymous namespace
29122913
29132914 /// \brief The specified machine instr operand is a vreg, and that
29142915 /// vreg is being provided by the specified load instruction. If possible,
None //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
0 //===- ARMFrameLowering.cpp - ARM Frame Information -----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1818 #include "ARMSubtarget.h"
1919 #include "MCTargetDesc/ARMAddressingModes.h"
2020 #include "MCTargetDesc/ARMBaseInfo.h"
21 #include "Utils/ARMBaseInfo.h"
2122 #include "llvm/ADT/BitVector.h"
2223 #include "llvm/ADT/STLExtras.h"
2324 #include "llvm/ADT/SmallPtrSet.h"
3839 #include "llvm/IR/Function.h"
3940 #include "llvm/MC/MCContext.h"
4041 #include "llvm/MC/MCDwarf.h"
42 #include "llvm/MC/MCInstrDesc.h"
4143 #include "llvm/MC/MCRegisterInfo.h"
4244 #include "llvm/Support/CodeGen.h"
4345 #include "llvm/Support/CommandLine.h"
4850 #include "llvm/Support/raw_ostream.h"
4951 #include "llvm/Target/TargetInstrInfo.h"
5052 #include "llvm/Target/TargetMachine.h"
53 #include "llvm/Target/TargetOpcodes.h"
5154 #include "llvm/Target/TargetOptions.h"
5255 #include "llvm/Target/TargetRegisterInfo.h"
5356 #include "llvm/Target/TargetSubtargetInfo.h"
952955
953956 DebugLoc DL;
954957
955 typedef std::pair RegAndKill;
958 using RegAndKill = std::pair;
959
956960 SmallVector Regs;
957961 unsigned i = CSI.size();
958962 while (i != 0) {
15241528 // In functions that realign the stack, it can be an advantage to spill the
15251529 // callee-saved vector registers after realigning the stack. The vst1 and vld1
15261530 // instructions take alignment hints that can improve performance.
1527 //
15281531 static void
15291532 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
15301533 MF.getInfo()->setNumAlignedDPRCS2Regs(0);
None //==-- ARMTargetFrameLowering.h - Define frame lowering for ARM --*- C++ -*-==//
0 //===- ARMTargetFrameLowering.h - Define frame lowering for ARM -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
128
139 #ifndef LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
1410 #define LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
1511
12 #include "llvm/CodeGen/MachineBasicBlock.h"
1613 #include "llvm/Target/TargetFrameLowering.h"
14 #include
1715
1816 namespace llvm {
19 class ARMSubtarget;
17
18 class ARMSubtarget;
19 class CalleeSavedInfo;
20 class MachineFunction;
2021
2122 class ARMFrameLowering : public TargetFrameLowering {
2223 protected:
6162 return true;
6263 }
6364
64 private:
65 private:
6566 void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
6667 const std::vector &CSI, unsigned StmOpc,
6768 unsigned StrOpc, bool NoGap,
7980 MachineBasicBlock::iterator MI) const override;
8081 };
8182
82 } // End llvm namespace
83 } // end namespace llvm
8384
84 #endif
85 #endif // LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
None //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
0 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
2323 #include "ARMSubtarget.h"
2424 #include "MCTargetDesc/ARMAddressingModes.h"
2525 #include "MCTargetDesc/ARMBaseInfo.h"
26 #include "Utils/ARMBaseInfo.h"
2627 #include "llvm/ADT/APFloat.h"
2728 #include "llvm/ADT/APInt.h"
2829 #include "llvm/ADT/ArrayRef.h"
9394 #include "llvm/Support/MathExtras.h"
9495 #include "llvm/Support/raw_ostream.h"
9596 #include "llvm/Target/TargetInstrInfo.h"
97 #include "llvm/Target/TargetLowering.h"
9698 #include "llvm/Target/TargetMachine.h"
99 #include "llvm/Target/TargetOpcodes.h"
97100 #include "llvm/Target/TargetOptions.h"
101 #include "llvm/Target/TargetRegisterInfo.h"
102 #include "llvm/Target/TargetSubtargetInfo.h"
98103 #include
99104 #include
100105 #include
16371642 const SmallVectorImpl &Ins, const SDLoc &dl,
16381643 SelectionDAG &DAG, SmallVectorImpl &InVals, bool isThisReturn,
16391644 SDValue ThisVal) const {
1640
16411645 // Assign locations to each value returned by this call.
16421646 SmallVector RVLocs;
16431647 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
17351739 SDValue &StackPtr,
17361740 SmallVectorImpl &MemOpChains,
17371741 ISD::ArgFlagsTy Flags) const {
1738
17391742 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
17401743 DAG.getVTList(MVT::i32, MVT::i32), Arg);
17411744 unsigned id = Subtarget->isLittle() ? 0 : 1;
24432446 const SmallVectorImpl &Outs,
24442447 const SmallVectorImpl &OutVals,
24452448 const SDLoc &dl, SelectionDAG &DAG) const {
2446
24472449 // CCValAssign - represent the assignment of the return value to a location.
24482450 SmallVector RVLocs;
24492451
36933695 DAG.getIntPtrConstant(1, dl));
36943696 } else
36953697 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3696
36973698 } else {
36983699 const TargetRegisterClass *RC;
36993700
37363737 }
37373738
37383739 InVals.push_back(ArgValue);
3739
37403740 } else { // VA.isRegLoc()
37413741 // sanity check
37423742 assert(VA.isMemLoc());
40224022 // Convert the carry flag into a boolean value.
40234023 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
40244024 break;
4025 case ISD::USUBO: {
4025 case ISD::USUBO:
40264026 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
40274027 // Convert the carry flag into a boolean value.
40284028 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
40314031 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
40324032 DAG.getConstant(1, dl, MVT::i32), Overflow);
40334033 break;
4034 }
40354034 }
40364035
40374036 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
49974996 ISD::SETGE, ARMcc, DAG, dl);
49984997 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
49994998 ARMcc, CCR, CmpLo);
5000
50014999
50025000 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
50035001 SDValue HiBigShift = Opc == ISD::SRA
54335431
54345432 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
54355433 if (Opc == ARMISD::VCEQ) {
5436
54375434 SDValue AndOp;
54385435 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
54395436 AndOp = Op0;
97109707 static SDValue AddCombineTo64BitSMLAL16(SDNode *AddcNode, SDNode *AddeNode,
97119708 TargetLowering::DAGCombinerInfo &DCI,
97129709 const ARMSubtarget *Subtarget) {
9713
97149710 if (Subtarget->isThumb()) {
97159711 if (!Subtarget->hasDSP())
97169712 return SDValue();
99569952 AddeNode->getOperand(1).getNode() == UmlalNode) ||
99579953 (AddeNode->getOperand(0).getNode() == UmlalNode &&
99589954 isNullConstant(AddeNode->getOperand(1)))) {
9959
99609955 SelectionDAG &DAG = DCI.DAG;
99619956 SDValue Ops[] = { UmlalNode->getOperand(0), UmlalNode->getOperand(1),
99629957 UmlalNode->getOperand(2), AddHi };
1001510010 SDValue RHS = N->getOperand(1);
1001610011 if (ConstantSDNode *C = dyn_cast(RHS)) {
1001710012 int32_t imm = C->getSExtValue();
10018 if (imm < 0 && imm > INT_MIN) {
10013 if (imm < 0 && imm > std::numeric_limits::min()) {
1001910014 SDLoc DL(N);
1002010015 RHS = DAG.getConstant(-imm, DL, MVT::i32);
1002110016 unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
1023910234 MVT::i32)));
1024010235 Res = DAG.getNode(ISD::SUB, DL, VT,
1024110236 DAG.getConstant(0, DL, MVT::i32), Res);
10242
1024310237 } else
1024410238 return SDValue();
1024510239 }
1240712401 return -1;
1240812402 }
1240912403
12410
1241112404 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
1241212405 if (V < 0)
1241312406 return false;
1302313016 return weight;
1302413017 }
1302513018
13026 typedef std::pair RCPair;
13019 using RCPair = std::pair;
13020
1302713021 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
1302813022 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
1302913023 if (Constraint.size() == 1) {
1382513819 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
1382613820 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
1382713821 if (!Subtarget->isLittle())
13828 std::swap (Lo, Hi);
13822 std::swap(Lo, Hi);
1382913823 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
1383013824 return Builder.CreateCall(Strex, {Lo, Hi, Addr});
1383113825 }
1394713941 DenseMap> SubVecs;
1394813942
1394913943 for (unsigned LoadCount = 0; LoadCount < NumLoads; ++LoadCount) {
13950
1395113944 // If we're generating more than one load, compute the base address of
1395213945 // subsequent loads as an offset from the previous.
1395313946 if (LoadCount > 0)
1408814081 Intrinsic::arm_neon_vst4};
1408914082
1409014083 for (unsigned StoreCount = 0; StoreCount < NumStores; ++StoreCount) {
14091
1409214084 // If we generating more than one store, we compute the base address of
1409314085 // subsequent stores as an offset from the previous.
1409414086 if (StoreCount > 0)
None //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
0 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1818 #include "llvm/ADT/SmallVector.h"
1919 #include "llvm/ADT/StringRef.h"
2020 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/ISDOpcodes.h"
2122 #include "llvm/CodeGen/MachineFunction.h"
2223 #include "llvm/CodeGen/MachineValueType.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
2424 #include "llvm/CodeGen/SelectionDAGNodes.h"
2525 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/IR/Attributes.h"
2627 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
2729 #include "llvm/IR/IRBuilder.h"
2830 #include "llvm/IR/InlineAsm.h"
2931 #include "llvm/Support/CodeGen.h"
3335 namespace llvm {
3436
3537 class ARMSubtarget;
38 class DataLayout;
39 class FastISel;
40 class FunctionLoweringInfo;
41 class GlobalValue;
3642 class InstrItineraryData;
43 class Instruction;
44 class MachineBasicBlock;
45 class MachineInstr;
46 class SelectionDAG;
47 class TargetLibraryInfo;
48 class TargetMachine;
49 class TargetRegisterInfo;
50 class VectorType;
3751
3852 namespace ARMISD {
3953
263277
264278 /// ReplaceNodeResults - Replace the results of node with an illegal result
265279 /// type with new values built out of custom code.
266 ///
267280 void ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results,
268281 SelectionDAG &DAG) const override;
269282
570583 const InstrItineraryData *Itins;
571584
572585 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
573 ///
574586 unsigned ARMPCLabelIndex;
575587
576588 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
584596 void addQRTypeForNEON(MVT VT);
585597 std::pair getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
586598
587 typedef SmallVector, 8> RegsToPassVector;
599 using RegsToPassVector = SmallVector, 8>;
588600
589601 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
590602 SDValue &Arg, RegsToPassVector &RegsToPass,
None //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
0 //===- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1818 #include "ARMMachineFunctionInfo.h"
1919 #include "ARMSubtarget.h"
2020 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "ThumbRegisterInfo.h"
21 #include "MCTargetDesc/ARMBaseInfo.h"
22 #include "Utils/ARMBaseInfo.h"
23 #include "llvm/ADT/ArrayRef.h"
2224 #include "llvm/ADT/DenseMap.h"
25 #include "llvm/ADT/DenseSet.h"
2326 #include "llvm/ADT/STLExtras.h"
2427 #include "llvm/ADT/SmallPtrSet.h"
2528 #include "llvm/ADT/SmallSet.h"
2629 #include "llvm/ADT/SmallVector.h"
2730 #include "llvm/ADT/Statistic.h"
31 #include "llvm/ADT/iterator_range.h"
32 #include "llvm/Analysis/AliasAnalysis.h"
2833 #include "llvm/CodeGen/LivePhysRegs.h"
2934 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFunction.h"
3036 #include "llvm/CodeGen/MachineFunctionPass.h"
3137 #include "llvm/CodeGen/MachineInstr.h"
3238 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineMemOperand.h"
40 #include "llvm/CodeGen/MachineOperand.h"
3341 #include "llvm/CodeGen/MachineRegisterInfo.h"
3442 #include "llvm/CodeGen/RegisterClassInfo.h"
35 #include "llvm/CodeGen/SelectionDAGNodes.h"
3643 #include "llvm/IR/DataLayout.h"
3744 #include "llvm/IR/DerivedTypes.h"
3845 #include "llvm/IR/Function.h"
46 #include "llvm/IR/DebugLoc.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/MC/MCInstrDesc.h"
49 #include "llvm/Pass.h"
3950 #include "llvm/Support/Allocator.h"
51 #include "llvm/Support/CommandLine.h"
4052 #include "llvm/Support/Debug.h"
4153 #include "llvm/Support/ErrorHandling.h"
4254 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetFrameLowering.h"
4356 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetLowering.h"
4558 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include
61 #include
62 #include
63 #include
64 #include
65 #include
66 #include
67
4668 using namespace llvm;
4769
4870 #define DEBUG_TYPE "arm-ldst-opt"
7193 #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
7294
7395 namespace {
96
7497 /// Post- register allocation pass the combine load / store instructions to
7598 /// form ldm / stm instructions.
7699 struct ARMLoadStoreOpt : public MachineFunctionPass {
77100 static char ID;
78 ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
79101
80102 const MachineFunction *MF;
81103 const TargetInstrInfo *TII;
90112 bool RegClassInfoValid;
91113 bool isThumb1, isThumb2;
92114
115 ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
116
93117 bool runOnMachineFunction(MachineFunction &Fn) override;
94118
95119 MachineFunctionProperties getRequiredProperties() const override {
106130 MachineInstr *MI;
107131 int Offset; ///< Load/Store offset.
108132 unsigned Position; ///< Position as counted from end of basic block.
133
109134 MemOpQueueEntry(MachineInstr &MI, int Offset, unsigned Position)
110135 : MI(&MI), Offset(Offset), Position(Position) {}
111136 };
112 typedef SmallVector MemOpQueue;
137 using MemOpQueue = SmallVector;
113138
114139 /// A set of MachineInstrs that fulfill (nearly all) conditions to get
115140 /// merged into a LDM/STM.
116141 struct MergeCandidate {
117142 /// List of instructions ordered by load/store offset.
118143 SmallVector Instrs;
144
119145 /// Index in Instrs of the instruction being latest in the schedule.
120146 unsigned LatestMIIdx;
147
121148 /// Index in Instrs of the instruction being earliest in the schedule.
122149 unsigned EarliestMIIdx;
150
123151 /// Index into the basic block where the merged instruction will be
124152 /// inserted. (See MemOpQueueEntry.Position)
125153 unsigned InsertPos;
154
126155 /// Whether the instructions can be merged into a ldm/stm instruction.
127156 bool CanMergeToLSMulti;
157
128158 /// Whether the instructions can be merged into a ldrd/strd instruction.
129159 bool CanMergeToLSDouble;
130160 };
160190 bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
161191 bool CombineMovBx(MachineBasicBlock &MBB);
162192 };
163 char ARMLoadStoreOpt::ID = 0;
164 }
193
194 } // end anonymous namespace
195
196 char ARMLoadStoreOpt::ID = 0;
165197
166198 INITIALIZE_PASS(ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false,
167199 false)
481513 MO.setImm(Offset);
482514 else
483515 InsertSub = true;
484
485516 } else if ((Opc == ARM::tSUBi8 || Opc == ARM::tADDi8) &&
486517 !definesCPSR(*MBBI)) {
487518 // SUBS/ADDS using this register, with a dead def of the CPSR.
501532 } else {
502533 InsertSub = true;
503534 }
504
505535 } else {
506536 // Can't update the instruction.
507537 InsertSub = true;
508538 }
509
510539 } else if (definesCPSR(*MBBI) || MBBI->isCall() || MBBI->isBranch()) {
511540 // Since SUBS sets the condition flags, we can't place the base reset
512541 // after an instruction that has a live CPSR def.
774803 // Insert a sub instruction after the newly formed instruction to reset.
775804 if (!BaseKill)
776805 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
777
778806 } else {
779807 // No writeback, simply build the MachineInstr.
780808 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
852880 }
853881
854882 // Attempt the merge.
855 typedef MachineBasicBlock::iterator iterator;
883 using iterator = MachineBasicBlock::iterator;
884
856885 MachineInstr *LatestMI = Cand.Instrs[Cand.LatestMIIdx];
857886 iterator InsertBefore = std::next(iterator(LatestMI));
858887 MachineBasicBlock &MBB = *LatestMI->getParent();
969998 int Offset = MemOps[SIndex].Offset;
970999 const MachineOperand &PMO = getLoadStoreRegOp(*MI);
9711000 unsigned PReg = PMO.getReg();
972 unsigned PRegNum = PMO.isUndef() ? UINT_MAX : TRI->getEncodingValue(PReg);
1001 unsigned PRegNum = PMO.isUndef() ? std::numeric_limits::max()
1002 : TRI->getEncodingValue(PReg);
9731003 unsigned Latest = SIndex;
9741004 unsigned Earliest = SIndex;
9751005 unsigned Count = 1;
10071037 break;
10081038
10091039 // See if the current load/store may be part of a multi load/store.
1010 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
1040 unsigned RegNum = MO.isUndef() ? std::numeric_limits::max()
1041 : TRI->getEncodingValue(Reg);
10111042 bool PartOfLSMulti = CanMergeToLSMulti;
10121043 if (PartOfLSMulti) {
10131044 // Register numbers must be in ascending order.
17841815 MergeBaseCandidates.push_back(&*MBBI);
17851816 }
17861817
1787
17881818 // If we are here then the chain is broken; Extract candidates for a merge.
17891819 if (MemOps.size() > 0) {
17901820 FormCandidates(MemOps);
19441974 "ARM pre- register allocation load / store optimization pass"
19451975
19461976 namespace {
1977
19471978 /// Pre- register allocation pass that move load / stores from consecutive
19481979 /// locations close to make it more likely they will be combined later.
19491980 struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass{
19501981 static char ID;
1951 ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
19521982
19531983 AliasAnalysis *AA;
19541984 const DataLayout *TD;
19581988 MachineRegisterInfo *MRI;
19591989 MachineFunction *MF;
19601990
1991 ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
1992
19611993 bool runOnMachineFunction(MachineFunction &Fn) override;
19621994
19631995 StringRef getPassName() const override {
19641996 return ARM_PREALLOC_LOAD_STORE_OPT_NAME;
19651997 }
19661998
1967 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
1999 void getAnalysisUsage(AnalysisUsage &AU) const override {
19682000 AU.addRequired();
19692001 MachineFunctionPass::getAnalysisUsage(AU);
19702002 }
19822014 DenseMap &MI2LocMap);
19832015 bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
19842016 };
1985 char ARMPreAllocLoadStoreOpt::ID = 0;
1986 }
2017
2018 } // end anonymous namespace
2019
2020 char ARMPreAllocLoadStoreOpt::ID = 0;
19872021
19882022 INITIALIZE_PASS(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
19892023 ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false)
22922326 bool RetVal = false;
22932327
22942328 DenseMap MI2LocMap;
2295 DenseMap > Base2LdsMap;
2296 DenseMap*, 4> > Base2StsMap;
2329 DenseMap *, 4>> Base2LdsMap;
2330 DenseMap> Base2StsMap;
22972331 SmallVector LdBases;
22982332 SmallVector StBases;
22992333
23252359
23262360 bool StopHere = false;
23272361 if (isLd) {
2328 DenseMap*, 4> >::iterator BI =
2362 DenseMap *, 4>>::iterator BI =
23292363 Base2LdsMap.find(Base);
23302364 if (BI != Base2LdsMap.end()) {
23312365 for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
23412375 LdBases.push_back(Base);
23422376 }
23432377 } else {
2344 DenseMap*, 4> >::iterator BI =
2378 DenseMap *, 4>>::iterator BI =
23452379 Base2StsMap.find(Base);
23462380 if (BI != Base2StsMap.end()) {
23472381 for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
23932427 return RetVal;
23942428 }
23952429
2396
23972430 /// Returns an instance of the load / store optimization pass.
23982431 FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) {
23992432 if (PreAlloc)
None //===-- ARMTargetTransformInfo.cpp - ARM specific TTI ---------------------===//
0 //===- ARMTargetTransformInfo.cpp - ARM specific TTI ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
77 //===----------------------------------------------------------------------===//
88
99 #include "ARMTargetTransformInfo.h"
10 #include "llvm/Support/Debug.h"
10 #include "ARMSubtarget.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "llvm/ADT/APInt.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/Analysis/LoopInfo.h"
15 #include "llvm/CodeGen/ISDOpcodes.h"
16 #include "llvm/CodeGen/MachineValueType.h"
17 #include "llvm/CodeGen/ValueTypes.h"
18 #include "llvm/IR/BasicBlock.h"
19 #include "llvm/IR/CallSite.h"
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/Instruction.h"
23 #include "llvm/IR/Instructions.h"
24 #include "llvm/IR/Type.h"
25 #include "llvm/MC/SubtargetFeature.h"
26 #include "llvm/Support/Casting.h"
1127 #include "llvm/Target/CostTable.h"
12 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include
30 #include
31 #include
32 #include
33
1334 using namespace llvm;
1435
1536 #define DEBUG_TYPE "armtti"
6384 // Load from constantpool.
6485 return 3;
6586 }
66
6787
6888 // Constants smaller than 256 fit in the immediate field of
6989 // Thumb1 instructions so we return a zero cost and 1 otherwise.
107127
108128 return getIntImmCost(Imm, Ty);
109129 }
110
111130
112131 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
113132 const Instruction *I) {
330349
331350 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
332351 const Instruction *I) {
333
334352 int ISD = TLI->InstructionOpcodeToISD(Opcode);
335353 // On NEON a a vector select gets lowered to vbsl.
336354 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
454472 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo,
455473 TTI::OperandValueProperties Opd2PropInfo,
456474 ArrayRef Args) {
457
458475 int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
459476 std::pair LT = TLI->getTypeLegalizationCost(DL, Ty);
460477
None //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
0 //===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 //
89 /// \file
910 /// This file a TargetTransformInfo::Concept conforming object specific to the
1011 /// ARM target machine. It uses the target's detailed information to
1112 /// provide more precise answers to certain TTI queries, while letting the
1213 /// target independent and default TTI implementations handle the rest.
13 ///
14 //
1415 //===----------------------------------------------------------------------===//
1516
1617 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
1718 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
1819
1920 #include "ARM.h"
21 #include "ARMSubtarget.h"
2022 #include "ARMTargetMachine.h"
23 #include "llvm/ADT/ArrayRef.h"
2124 #include "llvm/Analysis/TargetTransformInfo.h"
2225 #include "llvm/CodeGen/BasicTTIImpl.h"
23 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/IR/Constant.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/SubtargetFeature.h"
2429
2530 namespace llvm {
2631
32 class APInt;
33 class ARMTargetLowering;
34 class Instruction;
35 class Loop;
36 class SCEV;
37 class ScalarEvolution;
38 class Type;
39 class Value;
40
2741 class ARMTTIImpl : public BasicTTIImplBase {
28 typedef BasicTTIImplBase BaseT;
29 typedef TargetTransformInfo TTI;
42 using BaseT = BasicTTIImplBase;
43 using TTI = TargetTransformInfo;
44
3045 friend BaseT;
3146
3247 const ARMSubtarget *ST;
174189
175190 } // end namespace llvm
176191
177 #endif
192 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
None //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
0 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1111 #include "MCTargetDesc/ARMAddressingModes.h"
1212 #include "MCTargetDesc/ARMBaseInfo.h"
1313 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "MCTargetDesc/ARMMCTargetDesc.h"
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/None.h"
1418 #include "llvm/ADT/STLExtras.h"
1519 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/ADT/StringMap.h"
21 #include "llvm/ADT/StringRef.h"
1722 #include "llvm/ADT/StringSwitch.h"
1823 #include "llvm/ADT/Triple.h"
1924 #include "llvm/ADT/Twine.h"
20 #include "llvm/BinaryFormat/COFF.h"
21 #include "llvm/BinaryFormat/ELF.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCAssembler.h"
2425 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
26 #include "llvm/MC/MCELFStreamer.h"
2726 #include "llvm/MC/MCExpr.h"
2827 #include "llvm/MC/MCInst.h"
2928 #include "llvm/MC/MCInstrDesc.h"
3130 #include "llvm/MC/MCObjectFileInfo.h"
3231 #include "llvm/MC/MCParser/MCAsmLexer.h"
3332 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
3434 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
3535 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
3636 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
3939 #include "llvm/MC/MCStreamer.h"
4040 #include "llvm/MC/MCSubtargetInfo.h"
4141 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/MC/SubtargetFeature.h"
4243 #include "llvm/Support/ARMBuildAttributes.h"
4344 #include "llvm/Support/ARMEHABI.h"
45 #include "llvm/Support/Casting.h"
4446 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/ErrorHandling.h"
4649 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
50 #include "llvm/Support/SMLoc.h"
4851 #include "llvm/Support/TargetParser.h"
4952 #include "llvm/Support/TargetRegistry.h"
5053 #include "llvm/Support/raw_ostream.h"
54 #include
55 #include
56 #include
57 #include
58 #include
59 #include
60 #include
61 #include
62 #include
63 #include
5164
5265 using namespace llvm;
5366
7083 static cl::opt AddBuildAttributes("arm-add-build-attributes",
7184 cl::init(false));
7285
73 class ARMOperand;
74
7586 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
7687
7788 class UnwindContext {
89 using Locs = SmallVector;
90
7891 MCAsmParser &Parser;
79
80 typedef SmallVector Locs;
81
8292 Locs FnStartLocs;
8393 Locs CantUnwindLocs;
8494 Locs PersonalityLocs;
92102 bool hasFnStart() const { return !FnStartLocs.empty(); }
93103 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
94104 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
105
95106 bool hasPersonality() const {
96107 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
97108 }
110121 FI != FE; ++FI)
111122 Parser.Note(*FI, ".fnstart was specified here");
112123 }
124
113125 void emitCantUnwindLocNotes() const {
114126 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
115127 UE = CantUnwindLocs.end(); UI != UE; ++UI)
116128 Parser.Note(*UI, ".cantunwind was specified here");
117129 }
130
118131 void emitHandlerDataLocNotes() const {
119132 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
120133 HE = HandlerDataLocs.end(); HI != HE; ++HI)
121134 Parser.Note(*HI, ".handlerdata was specified here");
122135 }
136
123137 void emitPersonalityLocNotes() const {
124138 for (Locs::const_iterator PI = PersonalityLocs.begin(),
125139 PE = PersonalityLocs.end(),
198212 // would be legal.
199213 } ITState;
200214
201 llvm::SmallVector PendingConditionalInsts;
215 SmallVector PendingConditionalInsts;
202216
203217 void flushPendingInstructions(MCStreamer &Out) override {
204218 if (!inImplicitITBlock()) {
229243 bool inITBlock() { return ITState.CurPosition != ~0U; }
230244 bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
231245 bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
246
232247 bool lastInITBlock() {
233248 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
234249 }
250
235251 void forwardITPosition() {
236252 if (!inITBlock()) return;
237253 // Move to the next instruction in the IT block, if there is one. If not,
260276 assert(inImplicitITBlock());
261277 assert(ITState.CurPosition == 1);
262278 ITState.CurPosition = ~0U;
263 return;
264279 }
265280
266281 // Return the low-subreg of a given Q register.
331346 ITState.Mask = 8;
332347 ITState.CurPosition = 1;
333348 ITState.IsExplicit = false;
334 return;
335349 }
336350
337351 // Create a new explicit IT block with the given condition and mask. The mask
343357 ITState.Mask = Mask;
344358 ITState.CurPosition = 0;
345359 ITState.IsExplicit = true;
346 return;
347360 }
348361
349362 void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
350363 return getParser().Note(L, Msg, Range);
351364 }
365
352366 bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
353367 return getParser().Warning(L, Msg, Range);
354368 }
369
355370 bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
356371 return getParser().Error(L, Msg, Range);
357372 }
415430 // FIXME: Can tablegen auto-generate this?
416431 return getSTI().getFeatureBits()[ARM::ModeThumb];
417432 }
433
418434 bool isThumbOne() const {
419435 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
420436 }
437
421438 bool isThumbTwo() const {
422439 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
423440 }
441
424442 bool hasThumb() const {
425443 return getSTI().getFeatureBits()[ARM::HasV4TOps];
426444 }
445
427446 bool hasThumb2() const {
428447 return getSTI().getFeatureBits()[ARM::FeatureThumb2];
429448 }
449
430450 bool hasV6Ops() const {
431451 return getSTI().getFeatureBits()[ARM::HasV6Ops];
432452 }
453
433454 bool hasV6T2Ops() const {
434455 return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
435456 }
457
436458 bool hasV6MOps() const {
437459 return getSTI().getFeatureBits()[ARM::HasV6MOps];
438460 }
461
439462 bool hasV7Ops() const {
440463 return getSTI().getFeatureBits()[ARM::HasV7Ops];
441464 }
465
442466 bool hasV8Ops() const {
443467 return getSTI().getFeatureBits()[ARM::HasV8Ops];
444468 }
469
445470 bool hasV8MBaseline() const {
446471 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
447472 }
473
448474 bool hasV8MMainline() const {
449475 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
450476 }
477
451478 bool has8MSecExt() const {
452479 return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
453480 }
481
454482 bool hasARM() const {
455483 return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
456484 }
485
457486 bool hasDSP() const {
458487 return getSTI().getFeatureBits()[ARM::FeatureDSP];
459488 }
489
460490 bool hasD16() const {
461491 return getSTI().getFeatureBits()[ARM::FeatureD16];
462492 }
493
463494 bool hasV8_1aOps() const {
464495 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
465496 }
497
466498 bool hasRAS() const {
467499 return getSTI().getFeatureBits()[ARM::FeatureRAS];
468500 }
472504 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
473505 setAvailableFeatures(FB);
474506 }
507
475508 void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
509
476510 bool isMClass() const {
477511 return getSTI().getFeatureBits()[ARM::FeatureMClass];
478512 }
577611 bool &EmitInITBlock, MCStreamer &Out);
578612 void onLabelParsed(MCSymbol *Symbol) override;
579613 };
580 } // end anonymous namespace
581
582 namespace {
583614
584615 /// ARMOperand - Instances of this class represent a parsed ARM machine
585616 /// operand.
764795
765796 /// getStartLoc - Get the location of the first token of this operand.
766797 SMLoc getStartLoc() const override { return StartLoc; }
798
767799 /// getEndLoc - Get the location of the last token of this operand.
768800 SMLoc getEndLoc() const override { return EndLoc; }
801
769802 /// getLocRange - Get the range between the first and last token of this
770803 /// operand.
771804 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
884917 }
885918 return false;
886919 }
920
887921 // checks whether this operand is an signed offset which fits is a field
888922 // of specified width and scaled by a specific number of bits
889923 template
920954 else return false;
921955 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
922956 }
957
923958 bool isFPImm() const {
924959 if (!isImm()) return false;
925960 const MCConstantExpr *CE = dyn_cast(getImm());
936971 int64_t Value = CE->getValue();
937972 return Value >= N && Value <= M;
938973 }
974
939975 template
940976 bool isImmediateS4() const {
941977 if (!isImm()) return false;
944980 int64_t Value = CE->getValue();
945981 return ((Value & 3) == 0) && Value >= N && Value <= M;
946982 }
983
947984 bool isFBits16() const {
948985 return isImmediate<0, 17>();
949986 }
9671004 // explicitly exclude zero. we want that to use the normal 0_508 version.
9681005 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
9691006 }
1007
9701008 bool isImm0_4095Neg() const {
9711009 if (!isImm()) return false;
9721010 const MCConstantExpr *CE = dyn_cast(getImm());
9741012 int64_t Value = -CE->getValue();
9751013 return Value > 0 && Value < 4096;
9761014 }
1015
9771016 bool isImm0_7() const {
9781017 return isImmediate<0, 7>();
9791018 }
1019
9801020 bool isImm1_16() const {
9811021 return isImmediate<1, 16>();
9821022 }
1023
9831024 bool isImm1_32() const {
9841025 return isImmediate<1, 32>();
9851026 }
1027
9861028 bool isImm8_255() const {
9871029 return isImmediate<8, 255>();
9881030 }
1031
9891032 bool isImm256_65535Expr() const {
9901033 if (!isImm()) return false;
9911034 const MCConstantExpr *CE = dyn_cast(getImm());
9951038 int64_t Value = CE->getValue();
9961039 return Value >= 256 && Value < 65536;
9971040 }
1041
9981042 bool isImm0_65535Expr() const {
9991043 if (!isImm()) return false;
10001044 const MCConstantExpr *CE = dyn_cast(getImm());
10041048 int64_t Value = CE->getValue();
10051049 return Value >= 0 && Value < 65536;
10061050 }
1051
10071052 bool isImm24bit() const {
10081053 return isImmediate<0, 0xffffff + 1>();
10091054 }
1055
10101056 bool isImmThumbSR() const {
10111057 return isImmediate<1, 33>();
10121058 }
1059
10131060 bool isPKHLSLImm() const {
10141061 return isImmediate<0, 32>();
10151062 }
1063
10161064 bool isPKHASRImm() const {
10171065 return isImmediate<0, 33>();
10181066 }
1067
10191068 bool isAdrLabel() const {
10201069 // If we have an immediate that's not a constant, treat it as a label
10211070 // reference needing a fixup.
10301079 return (ARM_AM::getSOImmVal(Value) != -1 ||
10311080 ARM_AM::getSOImmVal(-Value) != -1);
10321081 }
1082
10331083 bool isT2SOImm() const {
10341084 // If we have an immediate that's not a constant, treat it as an expression
10351085 // needing a fixup.
10461096 int64_t Value = CE->getValue();
10471097 return ARM_AM::getT2SOImmVal(Value) != -1;
10481098 }
1099
10491100 bool isT2SOImmNot() const {
10501101 if (!isImm()) return false;
10511102 const MCConstantExpr *CE = dyn_cast(getImm());
10541105 return ARM_AM::getT2SOImmVal(Value) == -1 &&
10551106 ARM_AM::getT2SOImmVal(~Value) != -1;
10561107 }
1108
10571109 bool isT2SOImmNeg() const {
10581110 if (!isImm()) return false;
10591111 const MCConstantExpr *CE = dyn_cast(getImm());
10631115 return ARM_AM::getT2SOImmVal(Value) == -1 &&
10641116 ARM_AM::getT2SOImmVal(-Value) != -1;
10651117 }
1118
10661119 bool isSetEndImm() const {
10671120 if (!isImm()) return false;
10681121 const MCConstantExpr *CE = dyn_cast(getImm());
10701123 int64_t Value = CE->getValue();
10711124 return Value == 1 || Value == 0;
10721125 }
1126
10731127 bool isReg() const override { return Kind == k_Register; }
10741128 bool isRegList() const { return Kind == k_RegisterList; }
10751129 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
10831137 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
10841138 bool isRotImm() const { return Kind == k_RotateImmediate; }
10851139 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1140
10861141 bool isModImmNot() const {
10871142 if (!isImm()) return false;
10881143 const MCConstantExpr *CE = dyn_cast(getImm());
10901145 int64_t Value = CE->getValue();
10911146 return ARM_AM::getSOImmVal(~Value) != -1;
10921147 }
1148
10931149 bool isModImmNeg() const {
10941150 if (!isImm()) return false;
10951151 const MCConstantExpr *CE = dyn_cast(getImm());
10981154 return ARM_AM::getSOImmVal(Value) == -1 &&
10991155 ARM_AM::getSOImmVal(-Value) != -1;
11001156 }
1157
11011158 bool isThumbModImmNeg1_7() const {
11021159 if (!isImm()) return false;
11031160 const MCConstantExpr *CE = dyn_cast(getImm());
11051162 int32_t Value = -(int32_t)CE->getValue();
11061163 return 0 < Value && Value < 8;
11071164 }
1165
11081166 bool isThumbModImmNeg8_255() const {
11091167 if (!isImm()) return false;
11101168 const MCConstantExpr *CE = dyn_cast(getImm());
11121170 int32_t Value = -(int32_t)CE->getValue();
11131171 return 7 < Value && Value < 256;
11141172 }
1173
11151174 bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
11161175 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
11171176 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
11341193 // Immediate offset in range [-4095, 4095].
11351194 if (!Memory.OffsetImm) return true;
11361195 int64_t Val = Memory.OffsetImm->getValue();
1137 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1138 }
1196 return (Val > -4096 && Val < 4096) ||
1197 (Val == std::numeric_limits::min());
1198 }
1199
11391200 bool isAlignedMemory() const {
11401201 return isMemNoOffset(true);
11411202 }
1203
11421204 bool isAlignedMemoryNone() const {
11431205 return isMemNoOffset(false, 0);
11441206 }
1207
11451208 bool isDupAlignedMemoryNone() const {
11461209 return isMemNoOffset(false, 0);
11471210 }
1211
11481212 bool isAlignedMemory16() const {
11491213 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
11501214 return true;
11511215 return isMemNoOffset(false, 0);
11521216 }
1217
11531218 bool isDupAlignedMemory16() const {
11541219 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
11551220 return true;
11561221 return isMemNoOffset(false, 0);
11571222 }
1223
11581224 bool isAlignedMemory32() const {
11591225 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
11601226 return true;
11611227 return isMemNoOffset(false, 0);
11621228 }
1229
11631230 bool isDupAlignedMemory32() const {
11641231 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
11651232 return true;
11661233 return isMemNoOffset(false, 0);
11671234 }
1235
11681236 bool isAlignedMemory64() const {
11691237 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
11701238 return true;
11711239 return isMemNoOffset(false, 0);
11721240 }
1241
11731242 bool isDupAlignedMemory64() const {
11741243 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
11751244 return true;
11761245 return isMemNoOffset(false, 0);
11771246 }
1247
11781248 bool isAlignedMemory64or128() const {
11791249 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
11801250 return true;
11821252 return true;
11831253 return isMemNoOffset(false, 0);
11841254 }
1255
11851256 bool isDupAlignedMemory64or128() const {
11861257 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
11871258 return true;
11891260 return true;
11901261 return isMemNoOffset(false, 0);
11911262 }
1263
11921264 bool isAlignedMemory64or128or256() const {
11931265 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
11941266 return true;
11981270 return true;
11991271 return isMemNoOffset(false, 0);
12001272 }
1273
12011274 bool isAddrMode2() const {
12021275 if (!isMem() || Memory.Alignment != 0) return false;
12031276 // Check for register offset.
12071280 int64_t Val = Memory.OffsetImm->getValue();
12081281 return Val > -4096 && Val < 4096;
12091282 }
1283
12101284 bool isAM2OffsetImm() const {
12111285 if (!isImm()) return false;
12121286 // Immediate offset in range [-4095, 4095].
12131287 const MCConstantExpr *CE = dyn_cast(getImm());
12141288 if (!CE) return false;
12151289 int64_t Val = CE->getValue();
1216 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1217 }
1290 return (Val == std::numeric_limits::min()) ||
1291 (Val > -4096 && Val < 4096);
1292 }
1293
12181294 bool isAddrMode3() const {
12191295 // If we have an immediate that's not a constant, treat it as a label
12201296 // reference needing a fixup. If it is a constant, it's something else
12291305 // Immediate offset in range [-255, 255].
12301306 if (!Memory.OffsetImm) return true;
12311307 int64_t Val = Memory.OffsetImm->getValue();
1232 // The #-0 offset is encoded as INT32_MIN, and we have to check
1233 // for this too.
1234 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1235 }
1308 // The #-0 offset is encoded as std::numeric_limits::min(), and we
1309 // have to check for this too.
1310 return (Val > -256 && Val < 256) ||
1311 Val == std::numeric_limits::min();
1312 }
1313
12361314 bool isAM3Offset() const {
12371315 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
12381316 return false;
12421320 const MCConstantExpr *CE = dyn_cast(getImm());
12431321 if (!CE) return false;
12441322 int64_t Val = CE->getValue();
1245 // Special case, #-0 is INT32_MIN.
1246 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1247 }
1323 // Special case, #-0 is std::numeric_limits::min().
1324 return (Val > -256 && Val < 256) ||
1325 Val == std::numeric_limits::min();
1326 }
1327
12481328 bool isAddrMode5() const {
12491329 // If we have an immediate that's not a constant, treat it as a label
12501330 // reference needing a fixup. If it is a constant, it's something else
12581338 if (!Memory.OffsetImm) return true;
12591339 int64_t Val = Memory.OffsetImm->getValue();
12601340 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1261 Val == INT32_MIN;
1262 }
1341 Val == std::numeric_limits::min();
1342 }
1343
12631344 bool isAddrMode5FP16() const {
12641345 // If we have an immediate that's not a constant, treat it as a label
12651346 // reference needing a fixup. If it is a constant, it's something else
12721353 // Immediate offset in range [-510, 510] and a multiple of 2.
12731354 if (!Memory.OffsetImm) return true;
12741355 int64_t Val = Memory.OffsetImm->getValue();
1275 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;
1276 }
1356 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1357 Val == std::numeric_limits::min();
1358 }
1359
12771360 bool isMemTBB() const {
12781361 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
12791362 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
12801363 return false;
12811364 return true;
12821365 }
1366
12831367 bool isMemTBH() const {
12841368 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
12851369 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
12871371 return false;
12881372 return true;
12891373 }
1374
12901375 bool isMemRegOffset() const {
12911376 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
12921377 return false;
12931378 return true;
12941379 }
1380
12951381 bool isT2MemRegOffset() const {
12961382 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
12971383 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
13031389 return false;
13041390 return true;
13051391 }
1392
13061393 bool isMemThumbRR() const {
13071394 // Thumb reg+reg addressing is simple. Just two registers, a base and
13081395 // an offset. No shifts, negations or any other complicating factors.
13121399 return isARMLowRegister(Memory.BaseRegNum) &&
13131400 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
13141401 }
1402
13151403 bool isMemThumbRIs4() const {
13161404 if (!isMem() || Memory.OffsetRegNum != 0 ||
13171405 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
13211409 int64_t Val = Memory.OffsetImm->getValue();
13221410 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
13231411 }
1412
13241413 bool isMemThumbRIs2() const {
13251414 if (!isMem() || Memory.OffsetRegNum != 0 ||
13261415 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
13301419 int64_t Val = Memory.OffsetImm->getValue();
13311420 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
13321421 }
1422
13331423 bool isMemThumbRIs1() const {
13341424 if (!isMem() || Memory.OffsetRegNum != 0 ||
13351425 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
13391429 int64_t Val = Memory.OffsetImm->getValue();
13401430 return Val >= 0 && Val <= 31;
13411431 }
1432
13421433 bool isMemThumbSPI() const {
13431434 if (!isMem() || Memory.OffsetRegNum != 0 ||
13441435 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
13481439 int64_t Val = Memory.OffsetImm->getValue();
13491440 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
13501441 }
1442
13511443 bool isMemImm8s4Offset() const {
13521444 // If we have an immediate that's not a constant, treat it as a label
13531445 // reference needing a fixup. If it is a constant, it's something else
13591451 // Immediate offset a multiple of 4 in range [-1020, 1020].
13601452 if (!Memory.OffsetImm) return true;
13611453 int64_t Val = Memory.OffsetImm->getValue();
1362 // Special case, #-0 is INT32_MIN.
1363 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1364 }
1454 // Special case, #-0 is std::numeric_limits::min().
1455 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1456 Val == std::numeric_limits::min();
1457 }
1458
13651459 bool isMemImm0_1020s4Offset() const {
13661460 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
13671461 return false;
13701464 int64_t Val = Memory.OffsetImm->getValue();
13711465 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
13721466 }
1467
13731468 bool isMemImm8Offset() const {
13741469 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
13751470 return false;
13781473 // Immediate offset in range [-255, 255].
13791474 if (!Memory.OffsetImm) return true;
13801475 int64_t Val = Memory.OffsetImm->getValue();
1381 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1382 }
1476 return (Val == std::numeric_limits::min()) ||
1477 (Val > -256 && Val < 256);
1478 }
1479
13831480 bool isMemPosImm8Offset() const {
13841481 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
13851482 return false;
13881485 int64_t Val = Memory.OffsetImm->getValue();
13891486 return Val >= 0 && Val < 256;
13901487 }
1488
13911489 bool isMemNegImm8Offset() const {
13921490 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
13931491 return false;
13961494 // Immediate offset in range [-255, -1].
13971495 if (!Memory.OffsetImm) return false;
13981496 int64_t Val = Memory.OffsetImm->getValue();
1399 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1400 }
1497 return (Val == std::numeric_limits::min()) ||
1498 (Val > -256 && Val < 0);
1499 }
1500
14011501 bool isMemUImm12Offset() const {
14021502 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
14031503 return false;
14061506 int64_t Val = Memory.OffsetImm->getValue();
14071507 return (Val >= 0 && Val < 4096);
14081508 }
1509
14091510 bool isMemImm12Offset() const {
14101511 // If we have an immediate that's not a constant, treat it as a label
14111512 // reference needing a fixup. If it is a constant, it's something else
14191520 // Immediate offset in range [-4095, 4095].
14201521 if (!Memory.OffsetImm) return true;
14211522 int64_t Val = Memory.OffsetImm->getValue();
1422 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1423 }
1523 return (Val > -4096 && Val < 4096) ||
1524 (Val == std::numeric_limits::min());
1525 }
1526
14241527 bool isConstPoolAsmImm() const {
14251528 // Delay processing of Constant Pool Immediate, this will turn into
14261529 // a constant. Match no other operand
14271530 return (isConstantPoolImm());
14281531 }
1532
14291533 bool isPostIdxImm8() const {
14301534 if (!isImm()) return false;
14311535 const MCConstantExpr *CE = dyn_cast(getImm());
14321536 if (!CE) return false;
14331537 int64_t Val = CE->getValue();
1434 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1435 }
1538 return (Val > -256 && Val < 256) ||
1539 (Val == std::numeric_limits::min());
1540 }
1541
14361542 bool isPostIdxImm8s4() const {
14371543 if (!isImm()) return false;
14381544 const MCConstantExpr *CE = dyn_cast(getImm());
14391545 if (!CE) return false;
14401546 int64_t Val = CE->getValue();
14411547 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1442 (Val == INT32_MIN);
1548 (Val == std::numeric_limits::min());
14431549 }
14441550
14451551 bool isMSRMask() const { return Kind == k_MSRMask; }
14501556 bool isSingleSpacedVectorList() const {
14511557 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
14521558 }
1559
14531560 bool isDoubleSpacedVectorList() const {
14541561 return Kind == k_VectorList && VectorList.isDoubleSpaced;
14551562 }
1563
14561564 bool isVecListOneD() const {
14571565 if (!isSingleSpacedVectorList()) return false;
14581566 return VectorList.Count == 1;
14941602 bool isSingleSpacedVectorAllLanes() const {
14951603 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
14961604 }
1605
14971606 bool isDoubleSpacedVectorAllLanes() const {
14981607 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
14991608 }
1609
15001610 bool isVecListOneDAllLanes() const {
15011611 if (!isSingleSpacedVectorAllLanes()) return false;
15021612 return VectorList.Count == 1;
15361646 bool isSingleSpacedVectorIndexed() const {
15371647 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
15381648 }
1649
15391650 bool isDoubleSpacedVectorIndexed() const {
15401651 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
15411652 }
1653
15421654 bool isVecListOneDByteIndexed() const {
15431655 if (!isSingleSpacedVectorIndexed()) return false;
15441656 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
16331745 if (Kind != k_VectorIndex) return false;
16341746 return VectorIndex.Val < 8;
16351747 }
1748
16361749 bool isVectorIndex16() const {
16371750 if (Kind != k_VectorIndex) return false;
16381751 return VectorIndex.Val < 4;
16391752 }
1753
16401754 bool isVectorIndex32() const {
16411755 if (Kind != k_VectorIndex) return false;
16421756 return VectorIndex.Val < 2;
17161830 }
17171831 return true;
17181832 }
1833
17191834 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
17201835 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1836
17211837 bool isNEONi32vmov() const {
17221838 if (isNEONByteReplicate(4))
17231839 return false; // Let it to be classified as byte-replicate case.
17381854 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
17391855 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
17401856 }
1857
17411858 bool isNEONi32vmovNeg() const {
17421859 if (!isImm()) return false;
17431860 const MCConstantExpr *CE = dyn_cast(getImm());
21662283 if (!Memory.OffsetRegNum) {
21672284 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
21682285 // Special case for #-0
2169 if (Val == INT32_MIN) Val = 0;
2286 if (Val == std::numeric_limits::min()) Val = 0;
21702287 if (Val < 0) Val = -Val;
21712288 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
21722289 } else {
21872304 int32_t Val = CE->getValue();
21882305 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
21892306 // Special case for #-0
2190 if (Val == INT32_MIN) Val = 0;
2307 if (Val == std::numeric_limits::min()) Val = 0;
21912308 if (Val < 0) Val = -Val;
21922309 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
21932310 Inst.addOperand(MCOperand::createReg(0));
22102327 if (!Memory.OffsetRegNum) {
22112328 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
22122329 // Special case for #-0
2213 if (Val == INT32_MIN) Val = 0;
2330 if (Val == std::numeric_limits::min()) Val = 0;
22142331 if (Val < 0) Val = -Val;
22152332 Val = ARM_AM::getAM3Opc(AddSub, Val);
22162333 } else {
22382355 int32_t Val = CE->getValue();
22392356 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
22402357 // Special case for #-0
2241 if (Val == INT32_MIN) Val = 0;
2358 if (Val == std::numeric_limits::min()) Val = 0;
22422359 if (Val < 0) Val = -Val;
22432360 Val = ARM_AM::getAM3Opc(AddSub, Val);
22442361 Inst.addOperand(MCOperand::createReg(0));
22602377 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
22612378 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
22622379 // Special case for #-0
2263 if (Val == INT32_MIN) Val = 0;
2380 if (Val == std::numeric_limits::min()) Val = 0;
22642381 if (Val < 0) Val = -Val;
22652382 Val = ARM_AM::getAM5Opc(AddSub, Val);
22662383 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
22822399 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
22832400 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
22842401 // Special case for #-0
2285 if (Val == INT32_MIN) Val = 0;
2402 if (Val == std::numeric_limits::min()) Val = 0;
22862403 if (Val < 0) Val = -Val;
22872404 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
22882405 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
24352552 assert(CE && "non-constant post-idx-imm8 operand!");
24362553 int Imm = CE->getValue();
24372554 bool isAdd = Imm >= 0;
2438 if (Imm == INT32_MIN) Imm = 0;
2555 if (Imm == std::numeric_limits::min()) Imm = 0;
24392556 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
24402557 Inst.addOperand(MCOperand::createImm(Imm));
24412558 }
24462563 assert(CE && "non-constant post-idx-imm8s4 operand!");
24472564 int Imm = CE->getValue();
24482565 bool isAdd = Imm >= 0;
2449 if (Imm == INT32_MIN) Imm = 0;
2566 if (Imm == std::numeric_limits::min()) Imm = 0;
24502567 // Immediate is scaled by 4.
24512568 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
24522569 Inst.addOperand(MCOperand::createImm(Imm));
25672684 B |= 0xe00; // cmode = 0b1110
25682685 Inst.addOperand(MCOperand::createImm(B));
25692686 }
2687
25702688 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
25712689 assert(N == 1 && "Invalid number of operands!");
25722690 // The immediate encodes the type of constant as well as the value.
25942712 B |= 0xe00; // cmode = 0b1110
25952713 Inst.addOperand(MCOperand::createImm(B));
25962714 }
2715
25972716 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
25982717 assert(N == 1 && "Invalid number of operands!");
25992718 // The immediate encodes the type of constant as well as the value.
27672886 static std::unique_ptr
27682887 CreateRegList(SmallVectorImpl> &Regs,
27692888 SMLoc StartLoc, SMLoc EndLoc) {
2770 assert (Regs.size() > 0 && "RegList contains no registers?");
2889 assert(Regs.size() > 0 && "RegList contains no registers?");
27712890 KindTy Kind = k_RegisterList;
27722891
27732892 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
27802899 array_pod_sort(Regs.begin(), Regs.end());
27812900
27822901 auto Op = make_unique(Kind);
2783 for (SmallVectorImpl >::const_iterator
2902 for (SmallVectorImpl>::const_iterator
27842903 I = Regs.begin(), E = Regs.end(); I != E; ++I)
27852904 Op->Registers.push_back(I->second);
27862905 Op->StartLoc = StartLoc;
30743193 /// Try to parse a register name. The token must be an Identifier when called,
30753194 /// and if it is a register name the token is eaten and the register number is
30763195 /// returned. Otherwise return -1.
3077 ///
30783196 int ARMAsmParser::tryParseRegister() {
30793197 MCAsmParser &Parser = getParser();
30803198 const AsmToken &Tok = Parser.getTok();
32283346 return 0;
32293347 }
32303348
3231
32323349 /// Try to parse a register name. The token must be an Identifier when called.
32333350 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
32343351 /// if there is a "writeback". 'true' if it's not a register.
38563973 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
38573974 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
38583975 }
3859
38603976 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
38613977 (Spacing == 2), S, E));
38623978 break;
46144730 Error(S, "constant expression expected");
46154731 return MatchOperand_ParseFail;
46164732 }
4617 // Negative zero is encoded as the flag value INT32_MIN.
4733 // Negative zero is encoded as the flag value
4734 // std::numeric_limits::min().
46184735 int32_t Val = CE->getValue();
46194736 if (isNegative && Val == 0)
4620 Val = INT32_MIN;
4737 Val = std::numeric_limits::min();
46214738
46224739 Operands.push_back(
46234740 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
46244741
46254742 return MatchOperand_Success;
46264743 }
4627
46284744
46294745 bool haveEaten = false;
46304746 bool isAdd = true;
48474963 if (!CE)
48484964 return Error (E, "constant expression expected");
48494965
4850 // If the constant was #-0, represent it as INT32_MIN.
4966 // If the constant was #-0, represent it as
4967 // std::numeric_limits::min().
48514968 int32_t Val = CE->getValue();
48524969 if (isNegative && Val == 0)
4853 CE = MCConstantExpr::create(INT32_MIN, getContext());
4970 CE = MCConstantExpr::create(std::numeric_limits::min(),
4971 getContext());
48544972
48554973 // Now we should have the closing ']'
48564974 if (Parser.getTok().isNot(AsmToken::RBrac))
51315249 case AsmToken::LCurly:
51325250 return parseRegisterList(Operands);
51335251 case AsmToken::Dollar:
5134 case AsmToken::Hash: {
5252 case AsmToken::Hash:
51355253 // #42 -> immediate.
51365254 S = Parser.getTok().getLoc();
51375255 Parser.Lex();
51455263 if (CE) {
51465264 int32_t Val = CE->getValue();
51475265 if (isNegative && Val == 0)
5148 ImmVal = MCConstantExpr::create(INT32_MIN, getContext());
5266 ImmVal = MCConstantExpr::create(std::numeric_limits::min(),
5267 getContext());
51495268 }
51505269 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
51515270 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
51625281 }
51635282 // w/ a ':' after the '#', it's just like a plain ':'.
51645283 LLVM_FALLTHROUGH;
5165 }
5284
51665285 case AsmToken::Colon: {
51675286 S = Parser.getTok().getLoc();
51685287 // ":lower16:" and ":upper16:" expression prefixes
56125731 !inITBlock()))
56135732 return true;
56145733
5615
5616
56175734 // Register-register 'add/sub' for thumb does not have a cc_out operand
56185735 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
56195736 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
56695786 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
56705787 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
56715788 }
5789
56725790 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
56735791 unsigned VariantID);
56745792
60086126 Inst.getOpcode() == ARM::BKPT ||
60096127 Inst.getOpcode() == ARM::tHLT ||
60106128 Inst.getOpcode() == ARM::HLT;
6011
60126129 }
60136130
60146131 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
62766393 case ARM::t2LDMIA_UPD:
62776394 case ARM::t2LDMDB_UPD:
62786395 case ARM::t2STMIA_UPD:
6279 case ARM::t2STMDB_UPD: {
6396 case ARM::t2STMDB_UPD:
62806397 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
62816398 return Error(Operands.back()->getStartLoc(),
62826399 "writeback register not allowed in register list");
62896406 return true;
62906407 }
62916408 break;
6292 }
6409
62936410 case ARM::sysLDMIA_UPD:
62946411 case ARM::sysLDMDA_UPD:
62956412 case ARM::sysLDMDB_UPD:
63056422 case ARM::sysSTMIB_UPD:
63066423 return Error(Operands[2]->getStartLoc(),
63076424 "system STM cannot have writeback register");
6308 case ARM::tMUL: {
6425 case ARM::tMUL:
63096426 // The second source operand must be the same register as the destination
63106427 // operand.
63116428 //
63226439 "destination register must match source register");
63236440 }
63246441 break;
6325 }
6442
63266443 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
63276444 // so only issue a diagnostic for thumb1. The instructions will be
63286445 // switched to the t2 encodings in processInstruction() if necessary.
63656482 return true;
63666483 break;
63676484 }
6368 case ARM::tADDrSP: {
6485 case ARM::tADDrSP:
63696486 // If the non-SP source operand and the destination operand are not the
63706487 // same, we need thumb2 (for the wide encoding), or we have an error.
63716488 if (!isThumbTwo() &&
63746491 "source register must be the same as destination");
63756492 }
63766493 break;
6377 }
6494
63786495 // Final range checking for Thumb unconditional branch instructions.
63796496 case ARM::tB:
63806497 if (!(static_cast(*Operands[2])).isSignedOffset<11, 1>())
64296546 break;
64306547 }
64316548 case ARM::HINT:
6432 case ARM::t2HINT: {
6549 case ARM::t2HINT:
64336550 if (hasRAS()) {
64346551 // ESB is not predicable (pred must be AL)
64356552 unsigned Imm8 = Inst.getOperand(0).getImm();
64416558 }
64426559 // Without the RAS extension, this behaves as any other unallocated hint.
64436560 break;
6444 }
64456561 }
64466562
64476563 return false;
79688084 // Handle encoding choice for the shift-immediate instructions.
79698085 case ARM::t2LSLri:
79708086 case ARM::t2LSRri:
7971 case ARM::t2ASRri: {
8087 case ARM::t2ASRri:
79728088 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
79738089 isARMLowRegister(Inst.getOperand(1).getReg()) &&
79748090 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
79938109 return true;
79948110 }
79958111 return false;
7996 }
79978112
79988113 // Handle the Thumb2 mode MOV complex aliases.
79998114 case ARM::t2MOVsr:
83138428 Inst = TmpInst;
83148429 return true;
83158430 }
8316 case ARM::tADDrSP: {
8431 case ARM::tADDrSP:
83178432 // If the non-SP source operand and the destination operand are not the
83188433 // same, we need to use the 32-bit encoding if it's available.
83198434 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
83228437 return true;
83238438 }
83248439 break;
8325 }
83268440 case ARM::tB:
83278441 // A Thumb conditional branch outside of an IT block is a tBcc.
83288442 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
83658479 (!listContainsBase && !hasWritebackToken) ||
83668480 (listContainsBase && hasWritebackToken)) {
83678481 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8368 assert (isThumbTwo());
8482 assert(isThumbTwo());
83698483 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
83708484 // If we're switching to the updating version, we need to insert
83718485 // the writeback tied operand.
83848498 bool listContainsBase;
83858499 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
83868500 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8387 assert (isThumbTwo());
8501 assert(isThumbTwo());
83888502 Inst.setOpcode(ARM::t2STMIA_UPD);
83898503 return true;
83908504 }
83978511 // should have generated an error in validateInstruction().
83988512 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
83998513 return false;
8400 assert (isThumbTwo());
8514 assert(isThumbTwo());
84018515 Inst.setOpcode(ARM::t2LDMIA_UPD);
84028516 // Add the base register and writeback operands.
84038517 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
84088522 bool listContainsBase;
84098523 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
84108524 return false;
8411 assert (isThumbTwo());
8525 assert(isThumbTwo());
84128526 Inst.setOpcode(ARM::t2STMDB_UPD);
84138527 // Add the base register and writeback operands.
84148528 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
84158529 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
84168530 return true;
84178531 }
8418 case ARM::t2MOVi: {
8532 case ARM::t2MOVi:
84198533 // If we can use the 16-bit encoding and the user didn't explicitly
84208534 // request the 32-bit variant, transform it here.
84218535 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
84358549 return true;
84368550 }
84378551 break;
8438 }
8439 case ARM::t2MOVr: {
8552
8553 case ARM::t2MOVr:
84408554 // If we can use the 16-bit encoding and the user didn't explicitly
84418555 // request the 32-bit variant, transform it here.
84428556 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
84558569 return true;
84568570 }
84578571 break;
8458 }
8572
84598573 case ARM::t2SXTH:
84608574 case ARM::t2SXTB:
84618575 case ARM::t2UXTH:
8462 case ARM::t2UXTB: {
8576 case ARM::t2UXTB:
84638577 // If we can use the 16-bit encoding and the user didn't explicitly
84648578 // request the 32-bit variant, transform it here.
84658579 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
84858599 return true;
84868600 }
84878601 break;
8488 }
8602
84898603 case ARM::MOVsi: {
84908604 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
84918605 // rrx shifts and asr/lsr of #32 is encoded as 0
85598673 case ARM::t2SBCrr:
85608674 case ARM::t2RORrr:
85618675 case ARM::t2BICrr:
8562 {
85638676 // Assemblers should use the narrow encodings of these instructions when permissible.
85648677 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
85658678 isARMLowRegister(Inst.getOperand(2).getReg())) &&
85888701 return true;
85898702 }
85908703 return false;
8591 }
8704
85928705 case ARM::t2ANDrr:
85938706 case ARM::t2EORrr:
85948707 case ARM::t2ADCrr:
85958708 case ARM::t2ORRrr:
8596 {
85978709 // Assemblers should use the narrow encodings of these instructions when permissible.
85988710 // These instructions are special in that they are commutable, so shorter encodings
85998711 // are available more often.
86288740 return true;
86298741 }
86308742 return false;
8631 }
86328743 }
86338744 return false;
86348745 }
87068817 }
87078818
87088819 namespace llvm {
8820
87098821 template <> inline bool IsCPSRDead(const MCInst *Instr) {
87108822 return true; // In an assembly source, no need to second-guess
87118823 }
8712 }
8824
8825 } // end namespace llvm
87138826
87148827 // Returns true if Inst is unpredictable if it is in and IT block, but is not
87158828 // the last instruction in the block.
94569569
94579570 return false;
94589571 }
9572
94599573 /// parseDirectiveFPU
94609574 /// ::= .fpu str
94619575 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
1014610260 int64_t Value;
1014710261 if (!SOExpr->evaluateAsAbsolute(Value))
1014810262 return Match_Success;
10149 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10263 assert((Value >= std::numeric_limits::min() &&
10264 Value <= std::numeric_limits::max()) &&
1015010265 "expression value must be representable in 32 bits");
1015110266 }
1015210267 break;
None //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
0 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
99 #include "MCTargetDesc/ARMAddressingModes.h"
1010 #include "MCTargetDesc/ARMBaseInfo.h"
1111 #include "MCTargetDesc/ARMMCTargetDesc.h"
12 #include "Utils/ARMBaseInfo.h"
1213 #include "llvm/MC/MCContext.h"
1314 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
1415 #include "llvm/MC/MCFixedLenDisassembler.h"
3031
3132 #define DEBUG_TYPE "arm-disassembler"
3233
33 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 using DecodeStatus = MCDisassembler::DecodeStatus;
3435
3536 namespace {
3637
116117
117118 private:
118119 mutable ITStatus ITBlock;
120
119121 DecodeStatus AddThumbPredicate(MCInst&) const;
120122 void UpdateThumbVFPPredicate(MCInst&) const;
121123 };
27582760 break;
27592761 }
27602762
2761
27622763 // First input register
27632764 switch (Inst.getOpcode()) {
27642765 case ARM::VST1q16:
38563857
38573858 return S;
38583859 }
3859
38603860
38613861 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
38623862 uint64_t Address, const void *Decoder) {
41814181
41824182 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
41834183 uint64_t Address, const void *Decoder) {
4184
41854184 unsigned R = fieldFromInstruction(Val, 5, 1);
41864185 unsigned SysM = fieldFromInstruction(Val, 0, 5);
41874186
None //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
0 //===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1515 #include "ARMBaseRegisterInfo.h"
1616 #include "ARMMachineFunctionInfo.h"
1717 #include "ARMSubtarget.h"
18 #include "MCTargetDesc/ARMBaseInfo.h"
1918 #include "Thumb1InstrInfo.h"
2019 #include "ThumbRegisterInfo.h"
20 #include "Utils/ARMBaseInfo.h"
2121 #include "llvm/ADT/BitVector.h"
2222 #include "llvm/ADT/STLExtras.h"
2323 #include "llvm/ADT/SmallVector.h"
3131 #include "llvm/CodeGen/MachineOperand.h"
3232 #include "llvm/CodeGen/MachineRegisterInfo.h"
3333 #include "llvm/IR/DebugLoc.h"
34 #include "llvm/MC/MCContext.h"
3435 #include "llvm/MC/MCDwarf.h"
36 #include "llvm/MC/MCRegisterInfo.h"
3537 #include "llvm/Support/Compiler.h"
3638 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
3740 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetOpcodes.h"
3842 #include "llvm/Target/TargetSubtargetInfo.h"
3943 #include
4044 #include
6771 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
6872 MRI, MIFlags);
6973 }
70
7174
7275 MachineBasicBlock::iterator Thumb1FrameLowering::
7376 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
642645 return true;
643646 }
644647
645 typedef std::bitset ARMRegSet;
648 using ARMRegSet = std::bitset;
646649
647650 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
648651 // or OrderEnd if no further registers are in that set. This does not advance
None //===-- Thumb1FrameLowering.h - Thumb1-specific frame info stuff --*- C++ -*-=//
0 //===- Thumb1FrameLowering.h - Thumb1-specific frame info stuff ---*- C++ -*-=//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
128
139 #ifndef LLVM_LIB_TARGET_ARM_THUMB1FRAMELOWERING_H
1410 #define LLVM_LIB_TARGET_ARM_THUMB1FRAMELOWERING_H
1511
1612 #include "ARMFrameLowering.h"
17 #include "Thumb1InstrInfo.h"
18 #include "ThumbRegisterInfo.h"
19 #include "llvm/Target/TargetFrameLowering.h"
2013
2114 namespace llvm {
15
16 class ARMSubtarget;
17 class MachineFunction;
2218
2319 class Thumb1FrameLowering : public ARMFrameLowering {
2420 public:
8783 bool emitPopSpecialFixUp(MachineBasicBlock &MBB, bool DoIt) const;
8884 };
8985
90 } // End llvm namespace
86 } // end namespace llvm
9187
92 #endif
88 #endif // LLVM_LIB_TARGET_ARM_THUMB1FRAMELOWERING_H