llvm.org GIT mirror llvm / 20b529b
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore. Loads and stores can have different pipeline behavior, especially on embedded chips. This change allows those differences to be expressed. Except for the 440 scheduler, there are no functionality changes. On the 440, the latency adjustment is only by one cycle, and so this probably does not affect much. Nevertheless, it will make a larger difference in the future and this removes a FIXME from the 440 itin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 8 years ago
9 changed file(s) with 140 addition(s) and 107 deletion(s). Raw diff Collapse all Expand all
523523 let mayLoad = 1 in
524524 def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
525525 ptr_rc:$rA),
526 "lhau $rD, $disp($rA)", LdStGeneral,
526 "lhau $rD, $disp($rA)", LdStLoad,
527527 []>, RegConstraint<"$rA = $ea_result">,
528528 NoEncode<"$ea_result">;
529529 // NO LWAU!
533533 // Zero extending loads.
534534 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
535535 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
536 "lbz $rD, $src", LdStGeneral,
536 "lbz $rD, $src", LdStLoad,
537537 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
538538 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
539 "lhz $rD, $src", LdStGeneral,
539 "lhz $rD, $src", LdStLoad,
540540 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
541541 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
542 "lwz $rD, $src", LdStGeneral,
542 "lwz $rD, $src", LdStLoad,
543543 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
544544
545545 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
546 "lbzx $rD, $src", LdStGeneral,
546 "lbzx $rD, $src", LdStLoad,
547547 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
548548 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
549 "lhzx $rD, $src", LdStGeneral,
549 "lhzx $rD, $src", LdStLoad,
550550 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
551551 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
552 "lwzx $rD, $src", LdStGeneral,
552 "lwzx $rD, $src", LdStLoad,
553553 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
554554
555555
556556 // Update forms.
557557 let mayLoad = 1 in {
558558 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
559 "lbzu $rD, $addr", LdStGeneral,
559 "lbzu $rD, $addr", LdStLoad,
560560 []>, RegConstraint<"$addr.reg = $ea_result">,
561561 NoEncode<"$ea_result">;
562562 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
563 "lhzu $rD, $addr", LdStGeneral,
563 "lhzu $rD, $addr", LdStLoad,
564564 []>, RegConstraint<"$addr.reg = $ea_result">,
565565 NoEncode<"$ea_result">;
566566 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
567 "lwzu $rD, $addr", LdStGeneral,
567 "lwzu $rD, $addr", LdStLoad,
568568 []>, RegConstraint<"$addr.reg = $ea_result">,
569569 NoEncode<"$ea_result">;
570570 }
612612 let PPC970_Unit = 2 in {
613613 // Truncating stores.
614614 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
615 "stb $rS, $src", LdStGeneral,
615 "stb $rS, $src", LdStStore,
616616 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
617617 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
618 "sth $rS, $src", LdStGeneral,
618 "sth $rS, $src", LdStStore,
619619 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
620620 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
621 "stw $rS, $src", LdStGeneral,
621 "stw $rS, $src", LdStStore,
622622 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
623623 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
624 "stbx $rS, $dst", LdStGeneral,
624 "stbx $rS, $dst", LdStStore,
625625 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
626626 PPC970_DGroup_Cracked;
627627 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
628 "sthx $rS, $dst", LdStGeneral,
628 "sthx $rS, $dst", LdStStore,
629629 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
630630 PPC970_DGroup_Cracked;
631631 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
632 "stwx $rS, $dst", LdStGeneral,
632 "stwx $rS, $dst", LdStStore,
633633 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
634634 PPC970_DGroup_Cracked;
635635 // Normal 8-byte stores.
646646
647647 def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
648648 symbolLo:$ptroff, ptr_rc:$ptrreg),
649 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
649 "stbu $rS, $ptroff($ptrreg)", LdStStore,
650650 [(set ptr_rc:$ea_res,
651651 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
652652 iaddroff:$ptroff))]>,
653653 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
654654 def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
655655 symbolLo:$ptroff, ptr_rc:$ptrreg),
656 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
656 "sthu $rS, $ptroff($ptrreg)", LdStStore,
657657 [(set ptr_rc:$ea_res,
658658 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
659659 iaddroff:$ptroff))]>,
187187
188188 def DSS : DSS_Form<822, (outs),
189189 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
190 "dss $STRM", LdStGeneral /*FIXME*/, []>;
190 "dss $STRM", LdStLoad /*FIXME*/, []>;
191191 def DSSALL : DSS_Form<822, (outs),
192192 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2),
193 "dssall", LdStGeneral /*FIXME*/, []>;
193 "dssall", LdStLoad /*FIXME*/, []>;
194194 def DST : DSS_Form<342, (outs),
195195 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
196 "dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
196 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
197197 def DSTT : DSS_Form<342, (outs),
198198 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
199 "dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
199 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
200200 def DSTST : DSS_Form<374, (outs),
201201 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
202 "dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
202 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
203203 def DSTSTT : DSS_Form<374, (outs),
204204 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
205 "dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
205 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
206206
207207 def DST64 : DSS_Form<342, (outs),
208208 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
209 "dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
209 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
210210 def DSTT64 : DSS_Form<342, (outs),
211211 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
212 "dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
212 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
213213 def DSTST64 : DSS_Form<374, (outs),
214214 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
215 "dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
215 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
216216 def DSTSTT64 : DSS_Form<374, (outs),
217217 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
218 "dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
218 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
219219
220220 def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins),
221 "mfvscr $vD", LdStGeneral,
221 "mfvscr $vD", LdStStore,
222222 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
223223 def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB),
224 "mtvscr $vB", LdStGeneral,
224 "mtvscr $vB", LdStLoad,
225225 [(int_ppc_altivec_mtvscr VRRC:$vB)]>;
226226
227227 let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads.
228228 def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src),
229 "lvebx $vD, $src", LdStGeneral,
229 "lvebx $vD, $src", LdStLoad,
230230 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
231231 def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src),
232 "lvehx $vD, $src", LdStGeneral,
232 "lvehx $vD, $src", LdStLoad,
233233 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
234234 def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src),
235 "lvewx $vD, $src", LdStGeneral,
235 "lvewx $vD, $src", LdStLoad,
236236 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
237237 def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src),
238 "lvx $vD, $src", LdStGeneral,
238 "lvx $vD, $src", LdStLoad,
239239 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
240240 def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src),
241 "lvxl $vD, $src", LdStGeneral,
241 "lvxl $vD, $src", LdStLoad,
242242 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
243243 }
244244
245245 def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src),
246 "lvsl $vD, $src", LdStGeneral,
246 "lvsl $vD, $src", LdStLoad,
247247 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
248248 PPC970_Unit_LSU;
249249 def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src),
250 "lvsr $vD, $src", LdStGeneral,
250 "lvsr $vD, $src", LdStLoad,
251251 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
252252 PPC970_Unit_LSU;
253253
254254 let PPC970_Unit = 2 in { // Stores.
255255 def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
256 "stvebx $rS, $dst", LdStGeneral,
256 "stvebx $rS, $dst", LdStStore,
257257 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
258258 def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst),
259 "stvehx $rS, $dst", LdStGeneral,
259 "stvehx $rS, $dst", LdStStore,
260260 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
261261 def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst),
262 "stvewx $rS, $dst", LdStGeneral,
262 "stvewx $rS, $dst", LdStStore,
263263 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
264264 def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst),
265 "stvx $rS, $dst", LdStGeneral,
265 "stvx $rS, $dst", LdStStore,
266266 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
267267 def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst),
268 "stvxl $rS, $dst", LdStGeneral,
268 "stvxl $rS, $dst", LdStStore,
269269 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
270270 }
271271
639639 isDOT;
640640
641641 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
642 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
642 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
643643
644644 //===----------------------------------------------------------------------===//
645645 // PPC32 Load Instructions.
648648 // Unindexed (r+i) Loads.
649649 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
650650 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
651 "lbz $rD, $src", LdStGeneral,
651 "lbz $rD, $src", LdStLoad,
652652 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
653653 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
654654 "lha $rD, $src", LdStLHA,
655655 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
656656 PPC970_DGroup_Cracked;
657657 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
658 "lhz $rD, $src", LdStGeneral,
658 "lhz $rD, $src", LdStLoad,
659659 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
660660 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
661 "lwz $rD, $src", LdStGeneral,
661 "lwz $rD, $src", LdStLoad,
662662 [(set GPRC:$rD, (load iaddr:$src))]>;
663663
664664 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
672672 // Unindexed (r+i) Loads with Update (preinc).
673673 let mayLoad = 1 in {
674674 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
675 "lbzu $rD, $addr", LdStGeneral,
675 "lbzu $rD, $addr", LdStLoad,
676676 []>, RegConstraint<"$addr.reg = $ea_result">,
677677 NoEncode<"$ea_result">;
678678
679679 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
680 "lhau $rD, $addr", LdStGeneral,
680 "lhau $rD, $addr", LdStLoad,
681681 []>, RegConstraint<"$addr.reg = $ea_result">,
682682 NoEncode<"$ea_result">;
683683
684684 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
685 "lhzu $rD, $addr", LdStGeneral,
685 "lhzu $rD, $addr", LdStLoad,
686686 []>, RegConstraint<"$addr.reg = $ea_result">,
687687 NoEncode<"$ea_result">;
688688
689689 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
690 "lwzu $rD, $addr", LdStGeneral,
690 "lwzu $rD, $addr", LdStLoad,
691691 []>, RegConstraint<"$addr.reg = $ea_result">,
692692 NoEncode<"$ea_result">;
693693
707707 //
708708 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
709709 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
710 "lbzx $rD, $src", LdStGeneral,
710 "lbzx $rD, $src", LdStLoad,
711711 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
712712 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
713713 "lhax $rD, $src", LdStLHA,
714714 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
715715 PPC970_DGroup_Cracked;
716716 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
717 "lhzx $rD, $src", LdStGeneral,
717 "lhzx $rD, $src", LdStLoad,
718718 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
719719 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
720 "lwzx $rD, $src", LdStGeneral,
720 "lwzx $rD, $src", LdStLoad,
721721 [(set GPRC:$rD, (load xaddr:$src))]>;
722722
723723
724724 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
725 "lhbrx $rD, $src", LdStGeneral,
725 "lhbrx $rD, $src", LdStLoad,
726726 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
727727 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
728 "lwbrx $rD, $src", LdStGeneral,
728 "lwbrx $rD, $src", LdStLoad,
729729 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
730730
731731 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
743743 // Unindexed (r+i) Stores.
744744 let PPC970_Unit = 2 in {
745745 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
746 "stb $rS, $src", LdStGeneral,
746 "stb $rS, $src", LdStStore,
747747 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
748748 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
749 "sth $rS, $src", LdStGeneral,
749 "sth $rS, $src", LdStStore,
750750 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
751751 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
752 "stw $rS, $src", LdStGeneral,
752 "stw $rS, $src", LdStStore,
753753 [(store GPRC:$rS, iaddr:$src)]>;
754754 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
755755 "stfs $rS, $dst", LdStUX,
763763 let PPC970_Unit = 2 in {
764764 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
765765 symbolLo:$ptroff, ptr_rc:$ptrreg),
766 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
766 "stbu $rS, $ptroff($ptrreg)", LdStStore,
767767 [(set ptr_rc:$ea_res,
768768 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
769769 iaddroff:$ptroff))]>,
770770 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
771771 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
772772 symbolLo:$ptroff, ptr_rc:$ptrreg),
773 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
773 "sthu $rS, $ptroff($ptrreg)", LdStStore,
774774 [(set ptr_rc:$ea_res,
775775 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
776776 iaddroff:$ptroff))]>,
777777 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
778778 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
779779 symbolLo:$ptroff, ptr_rc:$ptrreg),
780 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
780 "stwu $rS, $ptroff($ptrreg)", LdStStore,
781781 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
782782 iaddroff:$ptroff))]>,
783783 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
784784 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
785785 symbolLo:$ptroff, ptr_rc:$ptrreg),
786 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
786 "stfsu $rS, $ptroff($ptrreg)", LdStStore,
787787 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
788788 iaddroff:$ptroff))]>,
789789 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
790790 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
791791 symbolLo:$ptroff, ptr_rc:$ptrreg),
792 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
792 "stfdu $rS, $ptroff($ptrreg)", LdStStore,
793793 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
794794 iaddroff:$ptroff))]>,
795795 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
800800 //
801801 let PPC970_Unit = 2 in {
802802 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
803 "stbx $rS, $dst", LdStGeneral,
803 "stbx $rS, $dst", LdStStore,
804804 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
805805 PPC970_DGroup_Cracked;
806806 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
807 "sthx $rS, $dst", LdStGeneral,
807 "sthx $rS, $dst", LdStStore,
808808 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
809809 PPC970_DGroup_Cracked;
810810 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
811 "stwx $rS, $dst", LdStGeneral,
811 "stwx $rS, $dst", LdStStore,
812812 [(store GPRC:$rS, xaddr:$dst)]>,
813813 PPC970_DGroup_Cracked;
814814
815815 let mayStore = 1 in {
816816 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
817 "stwux $rS, $rA, $rB", LdStGeneral,
817 "stwux $rS, $rA, $rB", LdStStore,
818818 []>;
819819 }
820820 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
821 "sthbrx $rS, $dst", LdStGeneral,
821 "sthbrx $rS, $dst", LdStStore,
822822 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
823823 PPC970_DGroup_Cracked;
824824 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
825 "stwbrx $rS, $dst", LdStGeneral,
825 "stwbrx $rS, $dst", LdStStore,
826826 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
827827 PPC970_DGroup_Cracked;
828828
4949 def LdStDCBA : InstrItinClass;
5050 def LdStDCBF : InstrItinClass;
5151 def LdStDCBI : InstrItinClass;
52 def LdStGeneral : InstrItinClass;
52 def LdStLoad : InstrItinClass;
53 def LdStStore : InstrItinClass;
5354 def LdStDSS : InstrItinClass;
5455 def LdStICBI : InstrItinClass;
5556 def LdStUX : InstrItinClass;
149150 // dcbf LdStDCBF
150151 // dcbi LdStDCBI
151152 // dcbst LdStDCBF
152 // dcbt LdStGeneral
153 // dcbtst LdStGeneral
153 // dcbt LdStLoad
154 // dcbtst LdStLoad
154155 // dcbz LdStDCBF
155156 // divd IntDivD
156157 // divdu IntDivD
159160 // dss LdStDSS
160161 // dst LdStDSS
161162 // dstst LdStDSS
162 // eciwx LdStGeneral
163 // ecowx LdStGeneral
164 // eieio LdStGeneral
163 // eciwx LdStLoad
164 // ecowx LdStLoad
165 // eieio LdStLoad
165166 // eqv IntGeneral
166167 // extsb IntGeneral
167168 // extsh IntGeneral
201202 // fsubs FPGeneral
202203 // icbi LdStICBI
203204 // isync SprISYNC
204 // lbz LdStGeneral
205 // lbzu LdStGeneral
205 // lbz LdStLoad
206 // lbzu LdStLoad
206207 // lbzux LdStUX
207 // lbzx LdStGeneral
208 // lbzx LdStLoad
208209 // ld LdStLD
209210 // ldarx LdStLDARX
210211 // ldu LdStLD
222223 // lhau LdStLHA
223224 // lhaux LdStLHA
224225 // lhax LdStLHA
225 // lhbrx LdStGeneral
226 // lhz LdStGeneral
227 // lhzu LdStGeneral
226 // lhbrx LdStLoad
227 // lhz LdStLoad
228 // lhzu LdStLoad
228229 // lhzux LdStUX
229 // lhzx LdStGeneral
230 // lhzx LdStLoad
230231 // lmw LdStLMW
231232 // lswi LdStLMW
232233 // lswx LdStLMW
241242 // lwarx LdStLWARX
242243 // lwaux LdStLHA
243244 // lwax LdStLHA
244 // lwbrx LdStGeneral
245 // lwz LdStGeneral
246 // lwzu LdStGeneral
245 // lwbrx LdStLoad
246 // lwz LdStLoad
247 // lwzu LdStLoad
247248 // lwzux LdStUX
248 // lwzx LdStGeneral
249 // lwzx LdStLoad
249250 // mcrf BrMCR
250251 // mcrfs FPGeneral
251252 // mcrxr BrMCRX
306307 // srawi IntShift
307308 // srd IntRotateD
308309 // srw IntGeneral
309 // stb LdStGeneral
310 // stbu LdStGeneral
311 // stbux LdStGeneral
312 // stbx LdStGeneral
310 // stb LdStStore
311 // stbu LdStStore
312 // stbux LdStStore
313 // stbx LdStStore
313314 // std LdStSTD
314315 // stdcx. LdStSTDCX
315316 // stdu LdStSTD
324325 // stfsu LdStUX
325326 // stfsux LdStUX
326327 // stfsx LdStUX
327 // sth LdStGeneral
328 // sthbrx LdStGeneral
329 // sthu LdStGeneral
330 // sthux LdStGeneral
331 // sthx LdStGeneral
328 // sth LdStStore
329 // sthbrx LdStStore
330 // sthu LdStStore
331 // sthux LdStStore
332 // sthx LdStStore
332333 // stmw LdStLMW
333334 // stswi LdStLMW
334335 // stswx LdStLMW
337338 // stvewx LdStSTVEBX
338339 // stvx LdStSTVEBX
339340 // stvxl LdStSTVEBX
340 // stw LdStGeneral
341 // stwbrx LdStGeneral
341 // stw LdStStore
342 // stwbrx LdStStore
342343 // stwcx. LdStSTWCX
343 // stwu LdStGeneral
344 // stwux LdStGeneral
345 // stwx LdStGeneral
344 // stwu LdStStore
345 // stwux LdStStore
346 // stwx LdStStore
346347 // subf IntGeneral
347348 // subfc IntGeneral
348349 // subfe IntGeneral
269269 InstrStage<1, [LWB]>],
270270 [8, 5],
271271 [NoBypass, GPR_Bypass]>,
272 InstrItinDataGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
272 InstrItinDataLoad , [InstrStage<1, [IFTH1, IFTH2]>,
273273 InstrStage<1, [PDCD1, PDCD2]>,
274274 InstrStage<1, [DISS1, DISS2]>,
275275 InstrStage<1, [LRACC]>,
276276 InstrStage<1, [AGEN]>,
277277 InstrStage<1, [CRD]>,
278278 InstrStage<2, [LWB]>],
279 [9, 5], // FIXME: should be [9, 5] for loads and
280 // [8, 5] for stores.
279 [9, 5],
280 [GPR_Bypass, GPR_Bypass]>,
281 InstrItinData,
282 InstrStage<1, [PDCD1, PDCD2]>,
283 InstrStage<1, [DISS1, DISS2]>,
284 InstrStage<1, [LRACC]>,
285 InstrStage<1, [AGEN]>,
286 InstrStage<1, [CRD]>,
287 InstrStage<2, [LWB]>],
288 [8, 5],
281289 [NoBypass, GPR_Bypass]>,
282290 InstrItinData,
283291 InstrStage<1, [PDCD1, PDCD2]>,
334342 [8, 5],
335343 [NoBypass, GPR_Bypass]>,
336344 InstrItinData,
345 InstrStage<1, [PDCD1, PDCD2]>,
346 InstrStage<1, [DISS1]>,
347 InstrStage<1, [IRACC], 0>,
348 InstrStage<4, [LWARX_Hold], 0>,
349 InstrStage<1, [LRACC]>,
350 InstrStage<1, [AGEN]>,
351 InstrStage<1, [CRD]>,
352 InstrStage<1, [LWB]>],
353 [8, 5],
354 [NoBypass, GPR_Bypass]>,
355 InstrItinData,
356 InstrStage<1, [PDCD1, PDCD2]>,
357 InstrStage<1, [DISS1, DISS2]>,
358 InstrStage<1, [LRACC]>,
359 InstrStage<1, [AGEN]>,
360 InstrStage<1, [CRD]>,
361 InstrStage<2, [LWB]>],
362 [8, 5],
363 [NoBypass, GPR_Bypass]>,
364 InstrItinData,
337365 InstrStage<1, [PDCD1, PDCD2]>,
338366 InstrStage<1, [DISS1]>,
339367 InstrStage<1, [IRACC], 0>,
3131 InstrItinData]>,
3232 InstrItinData]>,
3333 InstrItinData]>,
34 InstrItinDataGeneral , [InstrStage<2, [SLU]>]>,
34 InstrItinDataLoad , [InstrStage<2, [SLU]>]>,
35 InstrItinData]>,
3536 InstrItinData]>,
3637 InstrItinData]>,
3738 InstrItinData]>,
3030 InstrItinData]>,
3131 InstrItinData]>,
3232 InstrItinData]>,
33 InstrItinDataGeneral , [InstrStage<2, [SLU]>]>,
33 InstrItinDataLoad , [InstrStage<2, [SLU]>]>,
34 InstrItinData]>,
3435 InstrItinData]>,
3536 InstrItinData]>,
3637 InstrItinData]>,
3333 InstrItinData]>,
3434 InstrItinData]>,
3535 InstrItinData]>,
36 InstrItinDataGeneral , [InstrStage<3, [SLU]>]>,
36 InstrItinDataLoad , [InstrStage<3, [SLU]>]>,
37 InstrItinData]>,
3738 InstrItinData]>,
3839 InstrItinData]>,
3940 InstrItinData]>,
3434 InstrItinData]>,
3535 InstrItinData]>,
3636 InstrItinData]>,
37 InstrItinDataGeneral , [InstrStage<3, [SLU]>]>,
37 InstrItinDataLoad , [InstrStage<3, [SLU]>]>,
38 InstrItinData]>,
3839 InstrItinData]>,
3940 InstrItinData]>,
4041 InstrItinData]>,