llvm.org GIT mirror llvm / 20b0abc
Copy coalescing change to prevent a physical register from being pin to a long live interval that has low usage density. 1. Change order of coalescing to join physical registers with virtual registers first before virtual register intervals become too long. 2. Check size and usage density to determine if it's worthwhile to join. 3. If joining is aborted, assign virtual register live interval allocation preference field to the physical register. 4. Register allocator should try to allocate to the preferred register first (if available) to create identify moves that can be eliminated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36218 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
3 changed file(s) with 109 addition(s) and 93 deletion(s). Raw diff Collapse all Expand all
2222 #include "llvm/CodeGen/MachineFunctionPass.h"
2323 #include "llvm/CodeGen/LiveInterval.h"
2424 #include "llvm/ADT/BitVector.h"
25 #include "llvm/ADT/DenseMap.h"
2526 #include "llvm/ADT/IndexedMap.h"
2627
2728 namespace llvm {
2930 class LiveVariables;
3031 class MRegisterInfo;
3132 class TargetInstrInfo;
33 class TargetRegisterClass;
3234 class VirtRegMap;
3335
3436 class LiveIntervals : public MachineFunctionPass {
5557 Reg2RegMap r2rMap_;
5658
5759 BitVector allocatableRegs_;
60 DenseMap allocatableRCRegs_;
5861
5962 /// JoinedLIs - Keep track which register intervals have been coalesced
6063 /// with other intervals.
201204 /// CopyCoallesceInMBB - Coallsece copies in the specified MBB, putting
202205 /// copies that cannot yet be coallesced into the "TryAgain" list.
203206 void CopyCoallesceInMBB(MachineBasicBlock *MBB,
204 std::vector &TryAgain);
207 std::vector &TryAgain, bool PhysOnly = false);
205208
206209 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
207210 /// which are the src/dst of the copy instruction CopyMI. This returns true
209212 /// to coallesce these this copy, due to register constraints. It returns
210213 /// false if it is not currently possible to coallesce this interval, but
211214 /// it may be possible if other things get coallesced.
212 bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg);
215 bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg,
216 bool PhysOnly = false);
213217
214218 /// JoinIntervals - Attempt to join these two intervals. On failure, this
215219 /// returns false. Otherwise, if one of the intervals being joined is a
2929 #include "llvm/Target/TargetMachine.h"
3030 #include "llvm/Support/CommandLine.h"
3131 #include "llvm/Support/Debug.h"
32 #include "llvm/ADT/SmallSet.h"
3233 #include "llvm/ADT/Statistic.h"
3334 #include "llvm/ADT/STLExtras.h"
3435 #include
8687 mri_ = tm_->getRegisterInfo();
8788 tii_ = tm_->getInstrInfo();
8889 lv_ = &getAnalysis();
90 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
8991 allocatableRegs_ = mri_->getAllocatableSet(fn);
90 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
92 for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
93 E = mri_->regclass_end(); I != E; ++I)
94 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
9195
9296 // Number MachineInstrs and MachineBasicBlocks.
9397 // Initialize MBB indexes to a sentinal.
119123 }
120124
121125 // Join (coallesce) intervals if requested.
122 if (EnableJoining) joinIntervals();
126 if (EnableJoining) {
127 joinIntervals();
128 DOUT << "********** INTERVALS POST JOINING **********\n";
129 for (iterator I = begin(), E = end(); I != E; ++I) {
130 I->second.print(DOUT, mri_);
131 DOUT << "\n";
132 }
133 }
123134
124135 numIntervalsAfter += getNumIntervals();
125
126136
127137 // perform a final pass over the instructions and compute spill
128138 // weights, coalesce virtual registers and remove identity moves.
155165 mii = mbbi->erase(mii);
156166 ++numPeep;
157167 } else {
168 SmallSet UniqueUses;
158169 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
159170 const MachineOperand &mop = mii->getOperand(i);
160171 if (mop.isRegister() && mop.getReg() &&
163174 unsigned reg = rep(mop.getReg());
164175 mii->getOperand(i).setReg(reg);
165176
177 // Multiple uses of reg by the same instruction. It should not
178 // contribute to spill weight again.
179 if (UniqueUses.count(reg) != 0)
180 continue;
166181 LiveInterval &RegInt = getInterval(reg);
167182 float w = (mop.isUse()+mop.isDef()) * powf(10.0F, (float)loopDepth);
168183 // If the definition instruction is re-materializable, its spill
172187 if (RegInt.remat && !tii_->isLoadFromStackSlot(RegInt.remat, Dummy))
173188 w /= 2;
174189 RegInt.weight += w;
190 UniqueUses.insert(reg);
175191 }
176192 }
177193 ++mii;
187203 // it and hope it will be easier to allocate for this li.
188204 if (isZeroLengthInterval(&LI))
189205 LI.weight = HUGE_VALF;
190
206
207 // Slightly prefer live interval that has been assigned a preferred reg.
208 if (LI.preference)
209 LI.weight *= 1.01F;
210
191211 // Divide the weight of the interval by its size. This encourages
192212 // spilling of intervals that are large and have few uses, and
193213 // discourages spilling of small intervals with many uses.
194 unsigned Size = 0;
195 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II)
196 Size += II->end - II->start;
197
198 LI.weight /= Size;
214 LI.weight /= LI.getSize();
199215 }
200216 }
201217
865881 return true;
866882 }
867883
884
868885 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
869886 /// which are the src/dst of the copy instruction CopyMI. This returns true
870887 /// if the copy was successfully coallesced away, or if it is never possible
871 /// to coallesce these this copy, due to register constraints. It returns
888 /// to coallesce this copy, due to register constraints. It returns
872889 /// false if it is not currently possible to coallesce this interval, but
873890 /// it may be possible if other things get coallesced.
874891 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
875 unsigned SrcReg, unsigned DstReg) {
892 unsigned SrcReg, unsigned DstReg, bool PhysOnly) {
876893 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
877894
878895 // Get representative registers.
885902 return true; // Not coallescable.
886903 }
887904
905 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
906 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
907 if (PhysOnly && !SrcIsPhys && !DstIsPhys)
908 // Only joining physical registers with virtual registers in this round.
909 return true;
910
888911 // If they are both physical registers, we cannot join them.
889 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
890 MRegisterInfo::isPhysicalRegister(repDstReg)) {
912 if (SrcIsPhys && DstIsPhys) {
891913 DOUT << "\tCan not coallesce physregs.\n";
892914 return true; // Not coallescable.
893915 }
894916
895917 // We only join virtual registers with allocatable physical registers.
896 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
897 !allocatableRegs_[repSrcReg]) {
918 if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
898919 DOUT << "\tSrc reg is unallocatable physreg.\n";
899920 return true; // Not coallescable.
900921 }
901 if (MRegisterInfo::isPhysicalRegister(repDstReg) &&
902 !allocatableRegs_[repDstReg]) {
922 if (DstIsPhys && !allocatableRegs_[repDstReg]) {
903923 DOUT << "\tDst reg is unallocatable physreg.\n";
904924 return true; // Not coallescable.
905925 }
911931 }
912932
913933 LiveInterval &SrcInt = getInterval(repSrcReg);
914 LiveInterval &DestInt = getInterval(repDstReg);
915 assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg &&
934 LiveInterval &DstInt = getInterval(repDstReg);
935 assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
916936 "Register mapping is horribly broken!");
917
937
918938 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
919 DOUT << " and "; DestInt.print(DOUT, mri_);
939 DOUT << " and "; DstInt.print(DOUT, mri_);
920940 DOUT << ": ";
921941
922942 // Check if it is necessary to propagate "isDead" property before intervals
923943 // are joined.
924 MachineBasicBlock *CopyBB = CopyMI->getParent();
925944 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
926945 bool isDead = mopd->isDead();
927946 bool isShorten = false;
964983 // virtual register. Once the coalescing is done, it cannot be broken and
965984 // these are not spillable! If the destination interval uses are far away,
966985 // think twice about coalescing them!
967 if (!mopd->isDead() && MRegisterInfo::isPhysicalRegister(repSrcReg)) {
968 // Small function. No need to worry!
969 unsigned Threshold = allocatableRegs_.count() * 2;
970 if (r2iMap_.size() <= Threshold)
971 goto TryJoin;
972
973 LiveVariables::VarInfo& dvi = lv_->getVarInfo(repDstReg);
974 // Is the value used in the current BB or any immediate successroe BB?
975 if (dvi.UsedBlocks[CopyBB->getNumber()])
976 goto TryJoin;
977 for (MachineBasicBlock::succ_iterator SI = CopyBB->succ_begin(),
978 SE = CopyBB->succ_end(); SI != SE; ++SI) {
979 MachineBasicBlock *SuccMBB = *SI;
980 if (dvi.UsedBlocks[SuccMBB->getNumber()])
981 goto TryJoin;
982 }
983
984 // Ok, no use in this BB and no use in immediate successor BB's. Be really
985 // careful now!
986 // It's only used in one BB, forget about it!
987 if (dvi.UsedBlocks.count() < 2) {
986 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys)) {
987 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
988 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
989 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
990 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
991 unsigned Threshold = allocatableRCRegs_[RC].count();
992
993 // If the virtual register live interval is long has it has low use desity,
994 // do not join them, instead mark the physical register as its allocation
995 // preference.
996 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
997 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
998 if (Length > Threshold &&
999 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
1000 JoinVInt.preference = JoinPReg;
9881001 ++numAborts;
1002 DOUT << "\tMay tie down a physical register, abort!\n";
9891003 return false;
9901004 }
991
992 // Determine whether to allow coalescing based on how far the closest
993 // use is.
994 unsigned CopyIdx = getInstructionIndex(CopyMI);
995 unsigned MinDist = i2miMap_.size() * InstrSlots::NUM;
996 int UseBBNum = dvi.UsedBlocks.find_first();
997 while (UseBBNum != -1) {
998 MachineBasicBlock *UseBB = mf_->getBlockNumbered(UseBBNum);
999 unsigned UseIdx = getMBBStartIdx(UseBB);
1000 if (UseIdx > CopyIdx) {
1001 MinDist = std::min(MinDist, UseIdx - CopyIdx);
1002 if (MinDist <= Threshold)
1003 break;
1004 }
1005 UseBBNum = dvi.UsedBlocks.find_next(UseBBNum);
1006 }
1007 if (MinDist > Threshold) {
1008 // Don't do it!
1009 ++numAborts;
1010 return false;
1011 }
1012 }
1013
1014 TryJoin:
1005 }
1006
10151007 // Okay, attempt to join these two intervals. On failure, this returns false.
10161008 // Otherwise, if one of the intervals being joined is a physreg, this method
1017 // always canonicalizes DestInt to be it. The output "SrcInt" will not have
1009 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
10181010 // been modified, so we can use this information below to update aliases.
1019 if (JoinIntervals(DestInt, SrcInt)) {
1011 if (JoinIntervals(DstInt, SrcInt)) {
10201012 if (isDead) {
10211013 // Result of the copy is dead. Propagate this property.
10221014 if (SrcStart == 0) {
10371029
10381030 if (isShorten || isDead) {
10391031 // Shorten the live interval.
1040 LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt : SrcInt;
1032 LiveInterval &LiveInInt = (repSrcReg == DstInt.reg) ? DstInt : SrcInt;
10411033 LiveInInt.removeRange(RemoveStart, RemoveEnd);
10421034 }
10431035 } else {
10441036 // Coallescing failed.
10451037
10461038 // If we can eliminate the copy without merging the live ranges, do so now.
1047 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI))
1039 if (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI))
10481040 return true;
10491041
10501042 // Otherwise, we are unable to join the intervals.
10521044 return false;
10531045 }
10541046
1055 bool Swapped = repSrcReg == DestInt.reg;
1047 bool Swapped = repSrcReg == DstInt.reg;
10561048 if (Swapped)
10571049 std::swap(repSrcReg, repDstReg);
10581050 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
10691061 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
10701062 LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
10711063 dVI.UsedBlocks |= sVI.UsedBlocks;
1072 }
1073
1074 DOUT << "\n\t\tJoined. Result = "; DestInt.print(DOUT, mri_);
1064 dVI.NumUses += sVI.NumUses;
1065 }
1066
1067 DOUT << "\n\t\tJoined. Result = "; DstInt.print(DOUT, mri_);
10751068 DOUT << "\n";
10761069
10771070 // Remember these liveintervals have been joined.
10811074
10821075 // If the intervals were swapped by Join, swap them back so that the register
10831076 // mapping (in the r2i map) is correct.
1084 if (Swapped) SrcInt.swap(DestInt);
1077 if (Swapped) SrcInt.swap(DstInt);
10851078 removeInterval(repSrcReg);
10861079 r2rMap_[repSrcReg] = repDstReg;
10871080
12691262 // the LHS.
12701263 LHS.MergeRangesInAsValue(RHS, LHSValNo);
12711264 LHS.weight += RHS.weight;
1265 if (RHS.preference && !LHS.preference)
1266 LHS.preference = RHS.preference;
12721267
12731268 return true;
12741269 }
14771472
14781473
14791474 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
1480 std::vector &TryAgain) {
1475 std::vector &TryAgain, bool PhysOnly) {
14811476 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
14821477
14831478 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
14881483 unsigned SrcReg, DstReg;
14891484 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
14901485
1491 if (!JoinCopy(Inst, SrcReg, DstReg))
1486 if (!JoinCopy(Inst, SrcReg, DstReg, PhysOnly))
14921487 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
14931488 }
14941489 }
15111506 // Otherwise, join intervals in inner loops before other intervals.
15121507 // Unfortunately we can't just iterate over loop hierarchy here because
15131508 // there may be more MBB's than BB's. Collect MBB's for sorting.
1509
1510 // Join intervals in the function prolog first. We want to join physical
1511 // registers with virtual registers before the intervals got too long.
15141512 std::vector > MBBs;
1515 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1516 I != E; ++I)
1513 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I != E;++I)
15171514 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
15181515
15191516 // Sort by loop depth.
15211518
15221519 // Finally, join intervals in loop nest order.
15231520 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1524 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
1521 CopyCoallesceInMBB(MBBs[i].second, TryAgainList, true);
1522 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1523 CopyCoallesceInMBB(MBBs[i].second, TryAgainList, false);
15251524 }
15261525
15271526 // Joining intervals can allow other intervals to be joined. Iteratively join
562562
563563 // Find a register to spill.
564564 float minWeight = HUGE_VALF;
565 unsigned minReg = 0;
566 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
567 e = RC->allocation_order_end(*mf_); i != e; ++i) {
568 unsigned reg = *i;
569 if (minWeight > SpillWeights[reg]) {
570 minWeight = SpillWeights[reg];
571 minReg = reg;
572 }
573 }
565 unsigned minReg = cur->preference; // Try the preferred register first.
566
567 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
568 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
569 e = RC->allocation_order_end(*mf_); i != e; ++i) {
570 unsigned reg = *i;
571 if (minWeight > SpillWeights[reg]) {
572 minWeight = SpillWeights[reg];
573 minReg = reg;
574 }
575 }
574576
575577 // If we didn't find a register that is spillable, try aliases?
576578 if (!minReg) {
777779
778780 unsigned FreeReg = 0;
779781 unsigned FreeRegInactiveCount = 0;
780
782
783 // If copy coalescer has assigned a "preferred" register, check if it's
784 // available first.
785 if (cur->preference)
786 if (prt_->isRegAvail(cur->preference)) {
787 DOUT << "\t\tassigned the preferred register: "
788 << mri_->getName(cur->preference) << "\n";
789 return cur->preference;
790 } else
791 DOUT << "\t\tunable to assign the preferred register: "
792 << mri_->getName(cur->preference) << "\n";
793
781794 // Scan for the first available register.
782795 TargetRegisterClass::iterator I = rc->allocation_order_begin(*mf_);
783796 TargetRegisterClass::iterator E = rc->allocation_order_end(*mf_);