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Merging r200196: ------------------------------------------------------------------------ r200196 | michel.daenzer | 2014-01-26 23:20:51 -0800 (Sun, 26 Jan 2014) | 4 lines R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204637 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
4 changed file(s) with 142 addition(s) and 22 deletion(s). Raw diff Collapse all Expand all
424424
425425 multiclass MUBUF_Load_Helper op, string asm, RegisterClass regClass> {
426426
427 let glc = 0, lds = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */,
428 mayLoad = 1 in {
429
430 let offen = 1, idxen = 0, addr64 = 0, offset = 0 in {
431 def _OFFEN : MUBUF
432 (ins SReg_128:$srsrc, VReg_32:$vaddr),
433 asm#" $vdata, $srsrc + $vaddr", []>;
434 }
435
436 let offen = 0, idxen = 1, addr64 = 0 in {
437 def _IDXEN : MUBUF
438 (ins SReg_128:$srsrc, VReg_32:$vaddr, i16imm:$offset),
439 asm#" $vdata, $srsrc[$vaddr] + $offset", []>;
440 }
441
442 let offen = 0, idxen = 0, addr64 = 1 in {
443 def _ADDR64 : MUBUF
444 (ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
445 asm#" $vdata, $srsrc + $vaddr + $offset", []>;
446 }
427 let lds = 0, mayLoad = 1 in {
428
429 let addr64 = 0 in {
430
431 let offen = 0, idxen = 0 in {
432 def _OFFSET : MUBUF
433 (ins SReg_128:$srsrc, VReg_32:$vaddr,
434 i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
435 i1imm:$slc, i1imm:$tfe),
436 asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
437 }
438
439 let offen = 1, idxen = 0, offset = 0 in {
440 def _OFFEN : MUBUF
441 (ins SReg_128:$srsrc, VReg_32:$vaddr,
442 SSrc_32:$soffset, i1imm:$glc, i1imm:$slc,
443 i1imm:$tfe),
444 asm#" $vdata, $srsrc + $vaddr + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
445 }
446
447 let offen = 0, idxen = 1 in {
448 def _IDXEN : MUBUF
449 (ins SReg_128:$srsrc, VReg_32:$vaddr,
450 i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
451 i1imm:$slc, i1imm:$tfe),
452 asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
453 }
454
455 let offen = 1, idxen = 1 in {
456 def _BOTHEN : MUBUF
457 (ins SReg_128:$srsrc, VReg_64:$vaddr,
458 SSrc_32:$soffset, i1imm:$glc,
459 i1imm:$slc, i1imm:$tfe),
460 asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
461 }
462 }
463
464 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
465 def _ADDR64 : MUBUF
466 (ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
467 asm#" $vdata, $srsrc + $vaddr + $offset", []>;
468 }
447469 }
448470 }
449471
14121412 /* int_SI_vs_load_input */
14131413 def : Pat<
14141414 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1415 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset)
1415 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
14161416 >;
14171417
14181418 /* int_SI_export */
18181818 // 3. Offset in an 32Bit VGPR
18191819 def : Pat <
18201820 (SIload_constant i128:$sbase, i32:$voff),
1821 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff)
1821 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
18221822 >;
18231823
18241824 // The multiplication scales from [0,1] to the unsigned integer range
19791979 defm : MUBUFStore_Pattern ;
19801980 defm : MUBUFStore_Pattern ;
19811981
1982 // BUFFER_LOAD_DWORD*, addr64=0
1983 multiclass MUBUF_Load_Dword
1984 MUBUF bothen> {
1985
1986 def : Pat <
1987 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
1988 imm:$offset, 0, 0, imm:$glc, imm:$slc,
1989 imm:$tfe)),
1990 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
1991 (as_i1imm $slc), (as_i1imm $tfe))
1992 >;
1993
1994 def : Pat <
1995 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
1996 imm, 1, 0, imm:$glc, imm:$slc,
1997 imm:$tfe)),
1998 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
1999 (as_i1imm $tfe))
2000 >;
2001
2002 def : Pat <
2003 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
2004 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2005 imm:$tfe)),
2006 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2007 (as_i1imm $slc), (as_i1imm $tfe))
2008 >;
2009
2010 def : Pat <
2011 (vt (int_SI_buffer_load_dword i128:$rsrc, v2i32:$vaddr, i32:$soffset,
2012 imm, 1, 1, imm:$glc, imm:$slc,
2013 imm:$tfe)),
2014 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2015 (as_i1imm $tfe))
2016 >;
2017 }
2018
2019 defm : MUBUF_Load_Dword
2020 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2021 defm : MUBUF_Load_Dword
2022 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2023 defm : MUBUF_Load_Dword
2024 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2025
19822026 //===----------------------------------------------------------------------===//
19832027 // MTBUF Patterns
19842028 //===----------------------------------------------------------------------===//
3737 llvm_i32_ty], // tfe(imm)
3838 []>;
3939
40 // Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
41 def int_SI_buffer_load_dword : Intrinsic <
42 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
43 [llvm_anyint_ty, // rsrc(SGPR)
44 llvm_anyint_ty, // vaddr(VGPR)
45 llvm_i32_ty, // soffset(SGPR)
46 llvm_i32_ty, // inst_offset(imm)
47 llvm_i32_ty, // offen(imm)
48 llvm_i32_ty, // idxen(imm)
49 llvm_i32_ty, // glc(imm)
50 llvm_i32_ty, // slc(imm)
51 llvm_i32_ty], // tfe(imm)
52 [IntrReadArgMem]>;
53
4054 def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
4155
4256 class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
0 ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
1
2 ; Example of a simple geometry shader loading vertex attributes from the
3 ; ESGS ring buffer
4
5 ; CHECK-LABEL: @main
6 ; CHECK: BUFFER_LOAD_DWORD
7 ; CHECK: BUFFER_LOAD_DWORD
8 ; CHECK: BUFFER_LOAD_DWORD
9 ; CHECK: BUFFER_LOAD_DWORD
10
11 define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32, i32, i32, i32) #0 {
12 main_body:
13 %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
14 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
15 %12 = shl i32 %6, 2
16 %13 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0)
17 %14 = bitcast i32 %13 to float
18 %15 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 %12, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0)
19 %16 = bitcast i32 %15 to float
20 %17 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 %12, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 0)
21 %18 = bitcast i32 %17 to float
22 %19 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8> %11, <2 x i32> , i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 0)
23 %20 = bitcast i32 %19 to float
24 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %14, float %16, float %18, float %20)
25 ret void
26 }
27
28 ; Function Attrs: nounwind readonly
29 declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
30
31 ; Function Attrs: nounwind readonly
32 declare i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32) #1
33
34 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
35
36 attributes #0 = { "ShaderType"="1" }
37 attributes #1 = { nounwind readonly }
38
39 !0 = metadata !{metadata !"const", null, i32 1}