llvm.org GIT mirror llvm / 202a7a1
Add a new bit that ImmLeaf's can opt into, which allows them to duck out of the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 9 years ago
3 changed file(s) with 23 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
538538 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
539539 // is preferred over using PatLeaf because it allows the code generator to
540540 // reason more about the constraint.
541 class ImmLeaf : PatFrag<(ops), (vt imm)> {
541 //
542 // If FastIsel should ignore all instructions that have an operand of this type,
543 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
544 // the code size of the generated fast instruction selector.
545 class ImmLeaf
546 : PatFrag<(ops), (vt imm)> {
542547 let ImmediateCode = pred;
548 bit FastIselShouldIgnore = 0;
543549 }
544550
545551
480480 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
481481 def X86_COND_S : PatLeaf<(i8 15)>;
482482
483 def i16immSExt8 : ImmLeaf;
484 def i32immSExt8 : ImmLeaf;
485 def i64immSExt8 : ImmLeaf;
483 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
484 def i16immSExt8 : ImmLeaf;
485 def i32immSExt8 : ImmLeaf;
486 def i64immSExt8 : ImmLeaf;
487 }
488
486489 def i64immSExt32 : ImmLeaf;
487490
488491
189189 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
190190 unsigned PredNo = 0;
191191 if (!Op->getPredicateFns().empty()) {
192 TreePredicateFn PredFn = Op->getPredicateFns()[0];
192193 // If there is more than one predicate weighing in on this operand
193194 // then we don't handle it. This doesn't typically happen for
194195 // immediates anyway.
195196 if (Op->getPredicateFns().size() > 1 ||
196 !Op->getPredicateFns()[0].isImmediatePattern())
197 !PredFn.isImmediatePattern())
198 return false;
199 // Ignore any instruction with 'FastIselShouldIgnore', these are
200 // not needed and just bloat the fast instruction selector. For
201 // example, X86 doesn't need to generate code to match ADD16ri8 since
202 // ADD16ri will do just fine.
203 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
204 if (Rec->getValueAsBit("FastIselShouldIgnore"))
197205 return false;
198206
199 PredNo = ImmediatePredicates.getIDFor(Op->getPredicateFns()[0])+1;
207 PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
200208 }
201209
202210 // Handle unmatched immediate sizes here.