llvm.org GIT mirror llvm / 2015726
Merge r330269 to fix egregiously bad codegeneration in the new EFLAGS lowering that was defferred to a follow-up commit by me not understanding how part of the x86 backend worked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@332939 91177308-0d34-0410-b5e6-96231b3b80d8 Chandler Carruth 1 year, 4 months ago
7 changed file(s) with 32 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
635635 // also allow us to select a shorter encoding of `testb %reg, %reg` when that
636636 // would be equivalent.
637637 auto TestI =
638 BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8ri)).addReg(Reg).addImm(-1);
638 BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
639639 (void)TestI;
640640 DEBUG(dbgs() << " test cond: "; TestI->dump());
641641 ++NumTestsInserted;
4040 ; 32-GOOD-RA-NEXT: pushl %eax
4141 ; 32-GOOD-RA-NEXT: calll bar
4242 ; 32-GOOD-RA-NEXT: addl $16, %esp
43 ; 32-GOOD-RA-NEXT: testb $-1, %bl
43 ; 32-GOOD-RA-NEXT: testb %bl, %bl
4444 ; 32-GOOD-RA-NEXT: jne .LBB0_3
4545 ; 32-GOOD-RA-NEXT: # %bb.1: # %t
4646 ; 32-GOOD-RA-NEXT: movl $42, %eax
7171 ; 32-FAST-RA-NEXT: pushl %eax
7272 ; 32-FAST-RA-NEXT: calll bar
7373 ; 32-FAST-RA-NEXT: addl $16, %esp
74 ; 32-FAST-RA-NEXT: testb $-1, %bl
74 ; 32-FAST-RA-NEXT: testb %bl, %bl
7575 ; 32-FAST-RA-NEXT: jne .LBB0_3
7676 ; 32-FAST-RA-NEXT: # %bb.1: # %t
7777 ; 32-FAST-RA-NEXT: movl $42, %eax
9393 ; 64-ALL-NEXT: setne %bl
9494 ; 64-ALL-NEXT: movq %rax, %rdi
9595 ; 64-ALL-NEXT: callq bar
96 ; 64-ALL-NEXT: testb $-1, %bl
96 ; 64-ALL-NEXT: testb %bl, %bl
9797 ; 64-ALL-NEXT: jne .LBB0_2
9898 ; 64-ALL-NEXT: # %bb.1: # %t
9999 ; 64-ALL-NEXT: movl $42, %eax
218218 ; 32-GOOD-RA-NEXT: lock cmpxchgl %esi, (%ecx)
219219 ; 32-GOOD-RA-NEXT: sete %bl
220220 ; 32-GOOD-RA-NEXT: calll foo
221 ; 32-GOOD-RA-NEXT: testb $-1, %bl
221 ; 32-GOOD-RA-NEXT: testb %bl, %bl
222222 ; 32-GOOD-RA-NEXT: jne .LBB2_2
223223 ; 32-GOOD-RA-NEXT: # %bb.1: # %entry
224224 ; 32-GOOD-RA-NEXT: movl %eax, %esi
240240 ; 32-FAST-RA-NEXT: lock cmpxchgl %esi, (%ecx)
241241 ; 32-FAST-RA-NEXT: sete %bl
242242 ; 32-FAST-RA-NEXT: calll foo
243 ; 32-FAST-RA-NEXT: testb $-1, %bl
243 ; 32-FAST-RA-NEXT: testb %bl, %bl
244244 ; 32-FAST-RA-NEXT: jne .LBB2_2
245245 ; 32-FAST-RA-NEXT: # %bb.1: # %entry
246246 ; 32-FAST-RA-NEXT: movl %eax, %esi
261261 ; 64-ALL-NEXT: lock cmpxchgl %ebx, (%rdi)
262262 ; 64-ALL-NEXT: sete %bpl
263263 ; 64-ALL-NEXT: callq foo
264 ; 64-ALL-NEXT: testb $-1, %bpl
264 ; 64-ALL-NEXT: testb %bpl, %bpl
265265 ; 64-ALL-NEXT: cmovnel %ebx, %eax
266266 ; 64-ALL-NEXT: addq $8, %rsp
267267 ; 64-ALL-NEXT: popq %rbx
2929 ; X32-NEXT: cmpb %cl, %ah
3030 ; X32-NEXT: sete d
3131 ; X32-NEXT: movb %ch, a
32 ; X32-NEXT: testb $-1, %dl
32 ; X32-NEXT: testb %dl, %dl
3333 ; X32-NEXT: jne .LBB0_2
3434 ; X32-NEXT: # %bb.1: # %if.then
3535 ; X32-NEXT: movsbl %al, %eax
5454 ; X64-NEXT: cmpb %dil, %cl
5555 ; X64-NEXT: sete {{.*}}(%rip)
5656 ; X64-NEXT: movb %dl, {{.*}}(%rip)
57 ; X64-NEXT: testb $-1, %sil
57 ; X64-NEXT: testb %sil, %sil
5858 ; X64-NEXT: jne .LBB0_2
5959 ; X64-NEXT: # %bb.1: # %if.then
6060 ; X64-NEXT: pushq %rax
100100 ; X32-NEXT: pushl $42
101101 ; X32-NEXT: calll external
102102 ; X32-NEXT: addl $4, %esp
103 ; X32-NEXT: testb $-1, %bl
103 ; X32-NEXT: testb %bl, %bl
104104 ; X32-NEXT: je .LBB1_1
105105 ; X32-NEXT: # %bb.2: # %else
106106 ; X32-NEXT: xorl %eax, %eax
118118 ; X64-NEXT: setne %bl
119119 ; X64-NEXT: movl $42, %edi
120120 ; X64-NEXT: callq external
121 ; X64-NEXT: testb $-1, %bl
121 ; X64-NEXT: testb %bl, %bl
122122 ; X64-NEXT: je .LBB1_1
123123 ; X64-NEXT: # %bb.2: # %else
124124 ; X64-NEXT: xorl %eax, %eax
159159 ; X32-NEXT: setne %al
160160 ; X32-NEXT: incb a
161161 ; X32-NEXT: sete d
162 ; X32-NEXT: testb $-1, %al
162 ; X32-NEXT: testb %al, %al
163163 ; X32-NEXT: jne external_b # TAILCALL
164164 ; X32-NEXT: # %bb.1: # %then
165165 ; X32-NEXT: jmp external_a # TAILCALL
170170 ; X64-NEXT: setne %al
171171 ; X64-NEXT: incb {{.*}}(%rip)
172172 ; X64-NEXT: sete {{.*}}(%rip)
173 ; X64-NEXT: testb $-1, %al
173 ; X64-NEXT: testb %al, %al
174174 ; X64-NEXT: jne external_b # TAILCALL
175175 ; X64-NEXT: # %bb.1: # %then
176176 ; X64-NEXT: jmp external_a # TAILCALL
238238 ; X32-NEXT: setl %dl
239239 ; X32-NEXT: movzbl %dl, %ebp
240240 ; X32-NEXT: negl %ebp
241 ; X32-NEXT: testb $-1, %al
241 ; X32-NEXT: testb %al, %al
242242 ; X32-NEXT: jne .LBB3_3
243243 ; X32-NEXT: # %bb.2: # %bb1
244244 ; X32-NEXT: # in Loop: Header=BB3_1 Depth=1
247247 ; X32-NEXT: # in Loop: Header=BB3_1 Depth=1
248248 ; X32-NEXT: movb %cl, (%ebx)
249249 ; X32-NEXT: movl (%edi), %edx
250 ; X32-NEXT: testb $-1, %al
250 ; X32-NEXT: testb %al, %al
251251 ; X32-NEXT: jne .LBB3_5
252252 ; X32-NEXT: # %bb.4: # %bb1
253253 ; X32-NEXT: # in Loop: Header=BB3_1 Depth=1
9696 JMP_1 %bb.3
9797 ; CHECK-NOT: %eflags =
9898 ;
99 ; CHECK: TEST8ri %[[A_REG]], -1, implicit-def %eflags
99 ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def %eflags
100100 ; CHECK-NEXT: JNE_1 %bb.1, implicit killed %eflags
101101 ; CHECK-SAME: {{$[[:space:]]}}
102102 ; CHECK-NEXT: bb.4:
103103 ; CHECK-NEXT: successors: {{.*$}}
104104 ; CHECK-SAME: {{$[[:space:]]}}
105 ; CHECK-NEXT: TEST8ri %[[B_REG]], -1, implicit-def %eflags
105 ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def %eflags
106106 ; CHECK-NEXT: JNE_1 %bb.2, implicit killed %eflags
107107 ; CHECK-NEXT: JMP_1 %bb.3
108108
151151 JB_1 %bb.3, implicit %eflags
152152 ; CHECK-NOT: %eflags =
153153 ;
154 ; CHECK: TEST8ri %[[A_REG]], -1, implicit-def %eflags
154 ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def %eflags
155155 ; CHECK-NEXT: JNE_1 %bb.2, implicit killed %eflags
156156 ; CHECK-SAME: {{$[[:space:]]}}
157157 ; CHECK-NEXT: bb.4:
158158 ; CHECK-NEXT: successors: {{.*$}}
159159 ; CHECK-SAME: {{$[[:space:]]}}
160 ; CHECK-NEXT: TEST8ri %[[B_REG]], -1, implicit-def %eflags
160 ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def %eflags
161161 ; CHECK-NEXT: JNE_1 %bb.3, implicit killed %eflags
162162 ; CHECK-SAME: {{$[[:space:]]}}
163163 ; CHECK-NEXT: bb.1:
251251 %5:gr64 = CMOVE64rr %0, %1, implicit %eflags
252252 %6:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags
253253 ; CHECK-NOT: %eflags =
254 ; CHECK: TEST8ri %[[A_REG]], -1, implicit-def %eflags
254 ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def %eflags
255255 ; CHECK-NEXT: %3:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags
256 ; CHECK-NEXT: TEST8ri %[[B_REG]], -1, implicit-def %eflags
256 ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def %eflags
257257 ; CHECK-NEXT: %4:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags
258 ; CHECK-NEXT: TEST8ri %[[E_REG]], -1, implicit-def %eflags
258 ; CHECK-NEXT: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def %eflags
259259 ; CHECK-NEXT: %5:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags
260 ; CHECK-NEXT: TEST8ri %[[E_REG]], -1, implicit-def %eflags
260 ; CHECK-NEXT: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def %eflags
261261 ; CHECK-NEXT: %6:gr64 = CMOVE64rr %0, %1, implicit killed %eflags
262262 MOV64mr %rsp, 1, %noreg, -16, %noreg, killed %3
263263 MOV64mr %rsp, 1, %noreg, -16, %noreg, killed %4
363363 %5:gr64 = MOV64ri32 42
364364 %6:gr64 = ADCX64rr %2, %5, implicit-def %eflags, implicit %eflags
365365 ; CHECK-NOT: %eflags =
366 ; CHECK: TEST8ri %[[E_REG]], -1, implicit-def %eflags
366 ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def %eflags
367367 ; CHECK-NEXT: %4:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags
368368 ; CHECK-NEXT: %5:gr64 = MOV64ri32 42
369369 ; CHECK-NEXT: dead %{{[^:]*}}:gr8 = ADD8ri %[[CF_REG]], 255, implicit-def %eflags
402402 %5:gr64 = MOV64ri32 42
403403 %6:gr64 = ADOX64rr %2, %5, implicit-def %eflags, implicit %eflags
404404 ; CHECK-NOT: %eflags =
405 ; CHECK: TEST8ri %[[E_REG]], -1, implicit-def %eflags
405 ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def %eflags
406406 ; CHECK-NEXT: %4:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags
407407 ; CHECK-NEXT: %5:gr64 = MOV64ri32 42
408408 ; CHECK-NEXT: dead %{{[^:]*}}:gr8 = ADD8ri %[[OF_REG]], 127, implicit-def %eflags
220220 ; CHECK32-NEXT: pushl %eax
221221 ; CHECK32-NEXT: calll bar
222222 ; CHECK32-NEXT: addl $16, %esp
223 ; CHECK32-NEXT: testb $-1, %bl
223 ; CHECK32-NEXT: testb %bl, %bl
224224 ; CHECK32-NEXT: jne .LBB4_3
225225 ; CHECK32-NEXT: # %bb.1: # %t
226226 ; CHECK32-NEXT: movl $42, %eax
242242 ; CHECK64-NEXT: setne %bl
243243 ; CHECK64-NEXT: movq %rax, %rdi
244244 ; CHECK64-NEXT: callq bar
245 ; CHECK64-NEXT: testb $-1, %bl
245 ; CHECK64-NEXT: testb %bl, %bl
246246 ; CHECK64-NEXT: jne .LBB4_2
247247 ; CHECK64-NEXT: # %bb.1: # %t
248248 ; CHECK64-NEXT: movl $42, %eax
283283 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
284284 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
285285 ; CHECK32-NEXT: lock cmpxchg8b (%esi)
286 ; CHECK32-NEXT: setne {{[0-9]+}}(%esp) # 1-byte Folded Spill
286 ; CHECK32-NEXT: setne {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
287287 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
288288 ; CHECK32-NEXT: movl %edi, %edx
289289 ; CHECK32-NEXT: movl %ebp, %ecx
291291 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
292292 ; CHECK32-NEXT: lock cmpxchg8b (%esi)
293293 ; CHECK32-NEXT: sete %al
294 ; CHECK32-NEXT: testb $-1, {{[0-9]+}}(%esp) # 1-byte Folded Reload
294 ; CHECK32-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
295295 ; CHECK32-NEXT: jne .LBB5_4
296296 ; CHECK32-NEXT: # %bb.1: # %entry
297297 ; CHECK32-NEXT: testb %al, %al
318318 ; CHECK64-NEXT: movq %r8, %rax
319319 ; CHECK64-NEXT: lock cmpxchgq %r9, (%rcx)
320320 ; CHECK64-NEXT: sete %al
321 ; CHECK64-NEXT: testb $-1, %dl
321 ; CHECK64-NEXT: testb %dl, %dl
322322 ; CHECK64-NEXT: jne .LBB5_3
323323 ; CHECK64-NEXT: # %bb.1: # %entry
324324 ; CHECK64-NEXT: testb %al, %al
238238 ; ALL-NEXT: lock cmpxchgq %r8, (%rcx)
239239 ; ALL-NEXT: sete %bl
240240 ; ALL-NEXT: callq dummy
241 ; ALL-NEXT: testb $-1, %bl
241 ; ALL-NEXT: testb %bl, %bl
242242 ; ALL-NEXT: cmoveq %rsi, %rax
243243 ; ALL-NEXT: addq $40, %rsp
244244 ; ALL-NEXT: popq %rbx
4242 ; CHECK: pushl %esi
4343 ; CHECK: calll _g
4444 ; CHECK: addl $4, %esp
45 ; CHECK: testb $-1, %[[NE_REG]]
45 ; CHECK: testb %[[NE_REG]], %[[NE_REG]]
4646 ; CHECK: jne
4747
4848 attributes #0 = { nounwind optsize }