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[AArch64] Update test cases for Exynos M3 Update any test case relevant for Exynos M3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323775 91177308-0d34-0410-b5e6-96231b3b80d8 Evandro Menezes 2 years ago
4 changed file(s) with 106 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
0 ; REQUIRES: asserts
11 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s
2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOSM1 %s
3 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m3 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
34
45 ; Test ldr clustering.
56 ; CHECK: ********** MI Scheduling **********
78 ; CHECK: Cluster ld/st SU(1) - SU(2)
89 ; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
910 ; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
10 ; EXYNOS: ********** MI Scheduling **********
11 ; EXYNOS-LABEL: ldr_int:%bb.0
12 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
13 ; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
14 ; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
11 ; EXYNOSM1: ********** MI Scheduling **********
12 ; EXYNOSM1-LABEL: ldr_int:%bb.0
13 ; EXYNOSM1: Cluster ld/st SU(1) - SU(2)
14 ; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
15 ; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
1516 define i32 @ldr_int(i32* %a) nounwind {
1617 %p1 = getelementptr inbounds i32, i32* %a, i32 1
1718 %tmp1 = load i32, i32* %p1, align 2
2728 ; CHECK: Cluster ld/st SU(1) - SU(2)
2829 ; CHECK: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
2930 ; CHECK: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
30 ; EXYNOS: ********** MI Scheduling **********
31 ; EXYNOS-LABEL: ldp_sext_int:%bb.0
32 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
33 ; EXYNOS: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
34 ; EXYNOS: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
31 ; EXYNOSM1: ********** MI Scheduling **********
32 ; EXYNOSM1-LABEL: ldp_sext_int:%bb.0
33 ; EXYNOSM1: Cluster ld/st SU(1) - SU(2)
34 ; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
35 ; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
3536 define i64 @ldp_sext_int(i32* %p) nounwind {
3637 %tmp = load i32, i32* %p, align 4
3738 %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
4849 ; CHECK: Cluster ld/st SU(2) - SU(1)
4950 ; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
5051 ; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
51 ; EXYNOS: ********** MI Scheduling **********
52 ; EXYNOS-LABEL: ldur_int:%bb.0
53 ; EXYNOS: Cluster ld/st SU(2) - SU(1)
54 ; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
55 ; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
52 ; EXYNOSM1: ********** MI Scheduling **********
53 ; EXYNOSM1-LABEL: ldur_int:%bb.0
54 ; EXYNOSM1: Cluster ld/st SU(2) - SU(1)
55 ; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
56 ; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
5657 define i32 @ldur_int(i32* %a) nounwind {
5758 %p1 = getelementptr inbounds i32, i32* %a, i32 -1
5859 %tmp1 = load i32, i32* %p1, align 2
6869 ; CHECK: Cluster ld/st SU(3) - SU(4)
6970 ; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
7071 ; CHECK: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
71 ; EXYNOS: ********** MI Scheduling **********
72 ; EXYNOS-LABEL: ldp_half_sext_zext_int:%bb.0
73 ; EXYNOS: Cluster ld/st SU(3) - SU(4)
74 ; EXYNOS: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
75 ; EXYNOS: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
72 ; EXYNOSM1: ********** MI Scheduling **********
73 ; EXYNOSM1-LABEL: ldp_half_sext_zext_int:%bb.0
74 ; EXYNOSM1: Cluster ld/st SU(3) - SU(4)
75 ; EXYNOSM1: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
76 ; EXYNOSM1: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
7677 define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
7778 %tmp0 = load i64, i64* %q, align 4
7879 %tmp = load i32, i32* %p, align 4
9192 ; CHECK: Cluster ld/st SU(3) - SU(4)
9293 ; CHECK: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
9394 ; CHECK: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
94 ; EXYNOS: ********** MI Scheduling **********
95 ; EXYNOS-LABEL: ldp_half_zext_sext_int:%bb.0
96 ; EXYNOS: Cluster ld/st SU(3) - SU(4)
97 ; EXYNOS: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
98 ; EXYNOS: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
95 ; EXYNOSM1: ********** MI Scheduling **********
96 ; EXYNOSM1-LABEL: ldp_half_zext_sext_int:%bb.0
97 ; EXYNOSM1: Cluster ld/st SU(3) - SU(4)
98 ; EXYNOSM1: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
99 ; EXYNOSM1: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
99100 define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
100101 %tmp0 = load i64, i64* %q, align 4
101102 %tmp = load i32, i32* %p, align 4
114115 ; CHECK-NOT: Cluster ld/st
115116 ; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
116117 ; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
117 ; EXYNOS: ********** MI Scheduling **********
118 ; EXYNOS-LABEL: ldr_int_volatile:%bb.0
119 ; EXYNOS-NOT: Cluster ld/st
120 ; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
121 ; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
118 ; EXYNOSM1: ********** MI Scheduling **********
119 ; EXYNOSM1-LABEL: ldr_int_volatile:%bb.0
120 ; EXYNOSM1-NOT: Cluster ld/st
121 ; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
122 ; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
122123 define i32 @ldr_int_volatile(i32* %a) nounwind {
123124 %p1 = getelementptr inbounds i32, i32* %a, i32 1
124125 %tmp1 = load volatile i32, i32* %p1, align 2
134135 ; CHECK: Cluster ld/st SU(1) - SU(3)
135136 ; CHECK: SU(1): %{{[0-9]+}}:fpr128 = LDRQui
136137 ; CHECK: SU(3): %{{[0-9]+}}:fpr128 = LDRQui
137 ; EXYNOS: ********** MI Scheduling **********
138 ; EXYNOS-LABEL: ldq_cluster:%bb.0
139 ; EXYNOS-NOT: Cluster ld/st
138 ; EXYNOSM1: ********** MI Scheduling **********
139 ; EXYNOSM1-LABEL: ldq_cluster:%bb.0
140 ; EXYNOSM1-NOT: Cluster ld/st
140141 define <2 x i64> @ldq_cluster(i64* %p) {
141142 %a1 = bitcast i64* %p to <2 x i64>*
142143 %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s --check-prefixes=CHECK,GENERIC
11 ; The instruction latencies of Exynos-M1 trigger the transform we see under the Exynos check.
22 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m1 | FileCheck %s --check-prefixes=CHECK,EXYNOSM1
3 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m3 | FileCheck %s --check-prefixes=CHECK,EXYNOSM3
34
45 declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>)
56
352353 ; GENERIC: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
353354 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[1]
354355 ; EXYNOSM1: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
356 ; EXYNOSM3: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
355357 entry:
356358 %lane = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32>
357359 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
365367 ; GENERIC: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
366368 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[1]
367369 ; EXYNOSM1: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
370 ; EXYNOSM3: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
368371 entry:
369372 %lane = shufflevector <2 x float> %v, <2 x float> undef, <4 x i32>
370373 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane, <4 x float> %b, <4 x float> %a)
378381 ; GENERIC: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
379382 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[3]
380383 ; EXYNOSM1: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
384 ; EXYNOSM3: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
381385 entry:
382386 %lane = shufflevector <4 x float> %v, <4 x float> undef, <2 x i32>
383387 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
389393 ; GENERIC: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
390394 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[3]
391395 ; EXYNOSM1: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
396 ; EXYNOSM3: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
392397 entry:
393398 %lane = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32>
394399 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane, <4 x float> %b, <4 x float> %a)
400405 ; GENERIC: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
401406 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[1]
402407 ; EXYNOSM1: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
408 ; EXYNOSM3: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
403409 entry:
404410 %sub = fsub <2 x float> , %v
405411 %lane = shufflevector <2 x float> %sub, <2 x float> undef, <2 x i32>
412418 ; GENERIC: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
413419 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[1]
414420 ; EXYNOSM1: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
421 ; EXYNOSM3: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
415422 entry:
416423 %sub = fsub <2 x float> , %v
417424 %lane = shufflevector <2 x float> %sub, <2 x float> undef, <4 x i32>
424431 ; GENERIC: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
425432 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[3]
426433 ; EXYNOSM1: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
434 ; EXYNOSM3: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
427435 entry:
428436 %sub = fsub <4 x float> , %v
429437 %lane = shufflevector <4 x float> %sub, <4 x float> undef, <2 x i32>
436444 ; GENERIC: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
437445 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[3]
438446 ; EXYNOSM1: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
447 ; EXYNOSM3: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
439448 entry:
440449 %sub = fsub <4 x float> , %v
441450 %lane = shufflevector <4 x float> %sub, <4 x float> undef, <4 x i32>
448457 ; GENERIC: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
449458 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
450459 ; EXYNOSM1: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
460 ; EXYNOSM3: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
451461 entry:
452462 %lane = shufflevector <1 x double> %v, <1 x double> undef, <2 x i32> zeroinitializer
453463 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %lane, <2 x double> %b, <2 x double> %a)
461471 ; GENERIC: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
462472 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[1]
463473 ; EXYNOSM1: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
474 ; EXYNOSM3: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
464475 entry:
465476 %lane = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32>
466477 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %lane, <2 x double> %b, <2 x double> %a)
472483 ; GENERIC: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
473484 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
474485 ; EXYNOSM1: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
486 ; EXYNOSM3: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
475487 entry:
476488 %sub = fsub <1 x double> , %v
477489 %lane = shufflevector <1 x double> %sub, <1 x double> undef, <2 x i32> zeroinitializer
484496 ; GENERIC: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
485497 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[1]
486498 ; EXYNOSM1: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
499 ; EXYNOSM3: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
487500 entry:
488501 %sub = fsub <2 x double> , %v
489502 %lane = shufflevector <2 x double> %sub, <2 x double> undef, <2 x i32>
13101323 ; GENERIC: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
13111324 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[1]
13121325 ; EXYNOSM1: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
1326 ; EXYNOSM3: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
13131327 entry:
13141328 %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32>
13151329 %mul = fmul <2 x float> %shuffle, %a
13331347 ; GENERIC: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
13341348 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[1]
13351349 ; EXYNOSM1: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
1350 ; EXYNOSM3: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
13361351 entry:
13371352 %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <4 x i32>
13381353 %mul = fmul <4 x float> %shuffle, %a
13441359 ; GENERIC: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
13451360 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
13461361 ; EXYNOSM1: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1362 ; EXYNOSM3: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
13471363 entry:
13481364 %shuffle = shufflevector <1 x double> %v, <1 x double> undef, <2 x i32> zeroinitializer
13491365 %mul = fmul <2 x double> %shuffle, %a
13551371 ; GENERIC: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
13561372 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[3]
13571373 ; EXYNOSM1: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
1374 ; EXYNOSM3: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
13581375 entry:
13591376 %shuffle = shufflevector <4 x float> %v, <4 x float> undef, <2 x i32>
13601377 %mul = fmul <2 x float> %shuffle, %a
13781395 ; GENERIC: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
13791396 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[3]
13801397 ; EXYNOSM1: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
1398 ; EXYNOSM3: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
13811399 entry:
13821400 %shuffle = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32>
13831401 %mul = fmul <4 x float> %shuffle, %a
13891407 ; GENERIC: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
13901408 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[1]
13911409 ; EXYNOSM1: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
1410 ; EXYNOSM3: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
13921411 entry:
13931412 %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32>
13941413 %mul = fmul <2 x double> %shuffle, %a
14001419 ; GENERIC: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
14011420 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[1]
14021421 ; EXYNOSM1: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
1422 ; EXYNOSM3: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
14031423 entry:
14041424 %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32>
14051425 %vmulx2.i = tail call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %a, <2 x float> %shuffle)
14111431 ; GENERIC: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
14121432 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[1]
14131433 ; EXYNOSM1: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
1434 ; EXYNOSM3: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
14141435 entry:
14151436 %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <4 x i32>
14161437 %vmulx2.i = tail call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %a, <4 x float> %shuffle)
14221443 ; GENERIC: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
14231444 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
14241445 ; EXYNOSM1: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
1446 ; EXYNOSM3: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
14251447 entry:
14261448 %shuffle = shufflevector <1 x double> %v, <1 x double> undef, <2 x i32> zeroinitializer
14271449 %vmulx2.i = tail call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %a, <2 x double> %shuffle)
14331455 ; GENERIC: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
14341456 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[3]
14351457 ; EXYNOSM1: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
1458 ; EXYNOSM3: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
14361459 entry:
14371460 %shuffle = shufflevector <4 x float> %v, <4 x float> undef, <2 x i32>
14381461 %vmulx2.i = tail call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %a, <2 x float> %shuffle)
14441467 ; GENERIC: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
14451468 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[3]
14461469 ; EXYNOSM1: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
1470 ; EXYNOSM3: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
14471471 entry:
14481472 %shuffle = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32>
14491473 %vmulx2.i = tail call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %a, <4 x float> %shuffle)
14551479 ; GENERIC: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
14561480 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[1]
14571481 ; EXYNOSM1: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
1482 ; EXYNOSM3: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
14581483 entry:
14591484 %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32>
14601485 %vmulx2.i = tail call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %a, <2 x double> %shuffle)
17701795 ; GENERIC: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
17711796 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[0]
17721797 ; EXYNOSM1: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
1798 ; EXYNOSM3: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
17731799 entry:
17741800 %lane = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> zeroinitializer
17751801 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
17811807 ; GENERIC: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
17821808 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[0]
17831809 ; EXYNOSM1: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
1810 ; EXYNOSM3: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
17841811 entry:
17851812 %lane = shufflevector <2 x float> %v, <2 x float> undef, <4 x i32> zeroinitializer
17861813 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane, <4 x float> %b, <4 x float> %a)
17921819 ; GENERIC: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
17931820 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[0]
17941821 ; EXYNOSM1: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
1822 ; EXYNOSM3: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
17951823 entry:
17961824 %lane = shufflevector <4 x float> %v, <4 x float> undef, <2 x i32> zeroinitializer
17971825 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
18031831 ; GENERIC: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
18041832 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[0]
18051833 ; EXYNOSM1: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
1834 ; EXYNOSM3: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
18061835 entry:
18071836 %lane = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer
18081837 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane, <4 x float> %b, <4 x float> %a)
18141843 ; GENERIC: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
18151844 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[0]
18161845 ; EXYNOSM1: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
1846 ; EXYNOSM3: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
18171847 entry:
18181848 %sub = fsub <2 x float> , %v
18191849 %lane = shufflevector <2 x float> %sub, <2 x float> undef, <2 x i32> zeroinitializer
18261856 ; GENERIC: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
18271857 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[0]
18281858 ; EXYNOSM1: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
1859 ; EXYNOSM3: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
18291860 entry:
18301861 %sub = fsub <2 x float> , %v
18311862 %lane = shufflevector <2 x float> %sub, <2 x float> undef, <4 x i32> zeroinitializer
18381869 ; GENERIC: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
18391870 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[0]
18401871 ; EXYNOSM1: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
1872 ; EXYNOSM3: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
18411873 entry:
18421874 %sub = fsub <4 x float> , %v
18431875 %lane = shufflevector <4 x float> %sub, <4 x float> undef, <2 x i32> zeroinitializer
18501882 ; GENERIC: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
18511883 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[0]
18521884 ; EXYNOSM1: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
1885 ; EXYNOSM3: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
18531886 entry:
18541887 %sub = fsub <4 x float> , %v
18551888 %lane = shufflevector <4 x float> %sub, <4 x float> undef, <4 x i32> zeroinitializer
18621895 ; GENERIC: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
18631896 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
18641897 ; EXYNOSM1: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
1898 ; EXYNOSM3: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
18651899 entry:
18661900 %lane = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> zeroinitializer
18671901 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %lane, <2 x double> %b, <2 x double> %a)
18731907 ; GENERIC: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
18741908 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
18751909 ; EXYNOSM1: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
1910 ; EXYNOSM3: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
18761911 entry:
18771912 %sub = fsub <2 x double> , %v
18781913 %lane = shufflevector <2 x double> %sub, <2 x double> undef, <2 x i32> zeroinitializer
26052640 ; GENERIC: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
26062641 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[0]
26072642 ; EXYNOSM1: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
2643 ; EXYNOSM3: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
26082644 entry:
26092645 %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> zeroinitializer
26102646 %mul = fmul <2 x float> %shuffle, %a
26162652 ; GENERIC: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
26172653 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[0]
26182654 ; EXYNOSM1: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
2655 ; EXYNOSM3: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
26192656 entry:
26202657 %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <4 x i32> zeroinitializer
26212658 %mul = fmul <4 x float> %shuffle, %a
26272664 ; GENERIC: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
26282665 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[0]
26292666 ; EXYNOSM1: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
2667 ; EXYNOSM3: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
26302668 entry:
26312669 %shuffle = shufflevector <4 x float> %v, <4 x float> undef, <2 x i32> zeroinitializer
26322670 %mul = fmul <2 x float> %shuffle, %a
26502688 ; GENERIC: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
26512689 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[0]
26522690 ; EXYNOSM1: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
2691 ; EXYNOSM3: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
26532692 entry:
26542693 %shuffle = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer
26552694 %mul = fmul <4 x float> %shuffle, %a
26612700 ; GENERIC: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
26622701 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
26632702 ; EXYNOSM1: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
2703 ; EXYNOSM3: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
26642704 entry:
26652705 %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> zeroinitializer
26662706 %mul = fmul <2 x double> %shuffle, %a
26722712 ; GENERIC: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
26732713 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[0]
26742714 ; EXYNOSM1: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
2715 ; EXYNOSM3: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
26752716 entry:
26762717 %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> zeroinitializer
26772718 %vmulx2.i = tail call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %a, <2 x float> %shuffle)
26832724 ; GENERIC: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
26842725 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[0]
26852726 ; EXYNOSM1: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
2727 ; EXYNOSM3: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
26862728 entry:
26872729 %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <4 x i32> zeroinitializer
26882730 %vmulx2.i = tail call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %a, <4 x float> %shuffle)
26942736 ; GENERIC: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
26952737 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
26962738 ; EXYNOSM1: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
2739 ; EXYNOSM3: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
26972740 entry:
26982741 %shuffle = shufflevector <1 x double> %v, <1 x double> undef, <2 x i32> zeroinitializer
26992742 %vmulx2.i = tail call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %a, <2 x double> %shuffle)
27052748 ; GENERIC: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
27062749 ; EXYNOSM1: dup [[V:v[0-9]+]].2s, {{v[0-9]+}}.s[0]
27072750 ; EXYNOSM1: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[V]].2s
2751 ; EXYNOSM3: mulx {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
27082752 entry:
27092753 %shuffle = shufflevector <4 x float> %v, <4 x float> undef, <2 x i32> zeroinitializer
27102754 %vmulx2.i = tail call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %a, <2 x float> %shuffle)
27162760 ; GENERIC: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
27172761 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[0]
27182762 ; EXYNOSM1: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
2763 ; EXYNOSM3: mulx {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
27192764 entry:
27202765 %shuffle = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer
27212766 %vmulx2.i = tail call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %a, <4 x float> %shuffle)
27272772 ; GENERIC: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
27282773 ; EXYNOSM1: dup [[V:v[0-9]+]].2d, {{v[0-9]+}}.d[0]
27292774 ; EXYNOSM1: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, [[V]].2d
2775 ; EXYNOSM3: mulx {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
27302776 entry:
27312777 %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> zeroinitializer
27322778 %vmulx2.i = tail call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %a, <2 x double> %shuffle)
27402786 ; EXYNOSM1: dup [[V:v[0-9]+]].4s, {{v[0-9]+}}.s[3]
27412787 ; EXYNOSM1: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
27422788 ; EXYNOSM1: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
2789 ; EXYNOSM3: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
2790 ; EXYNOSM3: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
27432791 entry:
27442792 %lane1 = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32>
27452793 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane1, <4 x float> %b, <4 x float> %a)
27572805 ; EXYNOSM1: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[V]].4s
27582806 ; EXYNOSM1: dup [[W:v[0-9]+]].4s, {{v[0-9]+}}.s[1]
27592807 ; EXYNOSM1: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, [[W]].4s
2808 ; EXYNOSM3: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
2809 ; EXYNOSM3: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
27602810 entry:
27612811 %lane1 = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32>
27622812 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane1, <4 x float> %b, <4 x float> %a)
27842834 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
27852835 ret <2 x float> %0
27862836 }
2837
2838 define <2 x float> @test_vfma_lane_simdinstr_opt_pass_caching_m3(<2 x float> %a, <2 x float> %b, <2 x float> %v) "target-cpu"="exynos-m3" {
2839 ; CHECK-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_m3:
2840 ; GENERIC: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
2841 entry:
2842 %lane = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32>
2843 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
2844 ret <2 x float> %0
2845 }
44 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cyclone < %s | FileCheck %s
55 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 < %s | FileCheck %s
66 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m2 < %s | FileCheck %s
7 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 < %s | FileCheck %s
78 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo < %s | FileCheck %s
89 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
910
None ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+slow-paired-128 -verify-machineinstrs -asm-verbose=false | FileCheck %s
1 ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+slow-paired-128 -verify-machineinstrs -asm-verbose=false | FileCheck %s --check-prefixes=CHECK,SLOW
1 ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s --check-prefixes=CHECK,SLOW
2 ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m3 -verify-machineinstrs -asm-verbose=false | FileCheck %s --check-prefixes=CHECK,FAST
23
34 ; CHECK-LABEL: test_nopair_st
4 ; CHECK: str
5 ; CHECK: stur
6 ; CHECK-NOT: stp
5 ; SLOW: str
6 ; SLOW: stur
7 ; SLOW-NOT: stp
8 ; FAST: stp
79 define void @test_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) {
810 %tmp1 = bitcast double* %ptr to <2 x double>*
911 store <2 x double> %v2, <2 x double>* %tmp1, align 16
1416 }
1517
1618 ; CHECK-LABEL: test_nopair_ld
17 ; CHECK: ldr
18 ; CHECK: ldr
19 ; CHECK-NOT: ldp
19 ; SLOW: ldr
20 ; SLOW: ldr
21 ; SLOW-NOT: ldp
22 ; FAST: ldp
2023 define <2 x i64> @test_nopair_ld(i64* %p) {
2124 %a1 = bitcast i64* %p to <2 x i64>*
2225 %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8