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AMDGPU/GlobalISel: Add support for amdgpu_ps calling convention Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45837 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330767 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 66 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
138138 unsigned NumArgs = F.arg_size();
139139 Function::const_arg_iterator CurOrigArg = F.arg_begin();
140140 const AMDGPUTargetLowering &TLI = *getTLI();
141 unsigned PSInputNum = 0;
142 BitVector Skipped(NumArgs);
141143 for (unsigned i = 0; i != NumArgs; ++i, ++CurOrigArg) {
142144 EVT ValEVT = TLI.getValueType(DL, CurOrigArg->getType());
143145
144146 // We can only hanlde simple value types at the moment.
145 if (!ValEVT.isSimple())
146 return false;
147 MVT ValVT = ValEVT.getSimpleVT();
148147 ISD::ArgFlagsTy Flags;
149148 ArgInfo OrigArg{VRegs[i], CurOrigArg->getType()};
150149 setArgFlags(OrigArg, i + 1, DL, F);
151150 Flags.setOrigAlign(DL.getABITypeAlignment(CurOrigArg->getType()));
151
152 if (F.getCallingConv() == CallingConv::AMDGPU_PS &&
153 !OrigArg.Flags.isInReg() && !OrigArg.Flags.isByVal() &&
154 PSInputNum <= 15) {
155 if (CurOrigArg->use_empty() && !Info->isPSInputAllocated(PSInputNum)) {
156 Skipped.set(i);
157 ++PSInputNum;
158 continue;
159 }
160
161 Info->markPSInputAllocated(PSInputNum);
162 if (!CurOrigArg->use_empty())
163 Info->markPSInputEnabled(PSInputNum);
164
165 ++PSInputNum;
166 }
167
152168 CCAssignFn *AssignFn = CCAssignFnForCall(F.getCallingConv(),
153169 /*IsVarArg=*/false);
154 bool Res =
155 AssignFn(i, ValVT, ValVT, CCValAssign::Full, OrigArg.Flags, CCInfo);
156
157 // Fail if we don't know how to handle this type.
158 if (Res)
159 return false;
170
171 if (ValEVT.isVector()) {
172 EVT ElemVT = ValEVT.getVectorElementType();
173 if (!ValEVT.isSimple())
174 return false;
175 MVT ValVT = ElemVT.getSimpleVT();
176 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full,
177 OrigArg.Flags, CCInfo);
178 if (!Res)
179 return false;
180 } else {
181 MVT ValVT = ValEVT.getSimpleVT();
182 if (!ValEVT.isSimple())
183 return false;
184 bool Res =
185 AssignFn(i, ValVT, ValVT, CCValAssign::Full, OrigArg.Flags, CCInfo);
186
187 // Fail if we don't know how to handle this type.
188 if (Res)
189 return false;
190 }
160191 }
161192
162193 Function::const_arg_iterator Arg = F.arg_begin();
163194
164 if (F.getCallingConv() == CallingConv::AMDGPU_VS) {
165 for (unsigned i = 0; i != NumArgs; ++i, ++Arg) {
166 CCValAssign &VA = ArgLocs[i];
167 MRI.addLiveIn(VA.getLocReg(), VRegs[i]);
195 if (F.getCallingConv() == CallingConv::AMDGPU_VS ||
196 F.getCallingConv() == CallingConv::AMDGPU_PS) {
197 for (unsigned i = 0, OrigArgIdx = 0;
198 OrigArgIdx != NumArgs && i != ArgLocs.size(); ++Arg, ++OrigArgIdx) {
199 if (Skipped.test(OrigArgIdx))
200 continue;
201 CCValAssign &VA = ArgLocs[i++];
202 MRI.addLiveIn(VA.getLocReg(), VRegs[OrigArgIdx]);
168203 MIRBuilder.getMBB().addLiveIn(VA.getLocReg());
169 MIRBuilder.buildCopy(VRegs[i], VA.getLocReg());
204 MIRBuilder.buildCopy(VRegs[OrigArgIdx], VA.getLocReg());
170205 }
171206 return true;
172207 }
173208
174 for (unsigned i = 0; i != NumArgs; ++i, ++Arg) {
209 for (unsigned i = 0; i != ArgLocs.size(); ++i, ++Arg) {
175210 // FIXME: We should be getting DebugInfo from the arguments some how.
176211 CCValAssign &VA = ArgLocs[i];
177212 lowerParameter(MIRBuilder, Arg->getType(),
0 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
1
2 ; Check that we correctly skip over disabled inputs
3 ; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY $sgpr0
4 ; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY $vgpr0
5 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]](s32), [[S0]](s32), [[S0]](s32), [[V0]](s32)
6 define amdgpu_ps void @ps0(float inreg %arg0, float %psinput0, float %psinput1) #1 {
7 main_body:
8 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
9 ret void
10 }
11
12 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
13
14 attributes #0 = { nounwind }
15 attributes #1 = { "InitialPSInputAddr"="0x00002" }