llvm.org GIT mirror llvm / 1fab4a6
Recommitting parts of r48130. These do not appear to cause the observed failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8 Christopher Lamb 12 years ago
8 changed file(s) with 68 addition(s) and 47 deletion(s). Raw diff Collapse all Expand all
8989 MachineFunction &MF = *MBB->getParent();
9090 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
9191 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
92 unsigned DstReg = 0;
92 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
93 ((MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) ||
94 MI->getOperand(1).isImmediate()) &&
95 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
96 MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
97
98 unsigned DstReg = MI->getOperand(0).getReg();
9399 unsigned SrcReg = 0;
94 unsigned InsReg = 0;
95 unsigned SubIdx = 0;
96
97 // If only have 3 operands, then the source superreg is undef
98 // and we can supress the copy from the undef value
99 if (MI->getNumOperands() == 3) {
100 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
101 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
102 MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
103 DstReg = MI->getOperand(0).getReg();
100 // Check if we're inserting into an implicit value.
101 if (MI->getOperand(1).isImmediate())
104102 SrcReg = DstReg;
105 InsReg = MI->getOperand(1).getReg();
106 SubIdx = MI->getOperand(2).getImm();
107 } else if (MI->getNumOperands() == 4) {
108 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
109 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
110 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
111 MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
112 DstReg = MI->getOperand(0).getReg();
103 else
113104 SrcReg = MI->getOperand(1).getReg();
114 InsReg = MI->getOperand(2).getReg();
115 SubIdx = MI->getOperand(3).getImm();
116 } else
117 assert(0 && "Malformed extract_subreg");
105 unsigned InsReg = MI->getOperand(2).getReg();
106 unsigned SubIdx = MI->getOperand(3).getImm();
118107
119108 assert(SubIdx != 0 && "Invalid index for extract_subreg");
120109 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
694694 MI->addOperand(MachineOperand::CreateImm(SubIdx));
695695
696696 } else if (Opc == TargetInstrInfo::INSERT_SUBREG) {
697 assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) &&
698 "Malformed insert_subreg node");
699 bool isUndefInput = (Node->getNumOperands() == 2);
700 unsigned SubReg = 0;
701 unsigned SubIdx = 0;
702
703 if (isUndefInput) {
704 SubReg = getVR(Node->getOperand(0), VRBaseMap);
705 SubIdx = cast(Node->getOperand(1))->getValue();
706 } else {
707 SubReg = getVR(Node->getOperand(1), VRBaseMap);
708 SubIdx = cast(Node->getOperand(2))->getValue();
709 }
697 SDOperand N0 = Node->getOperand(0);
698 SDOperand N1 = Node->getOperand(1);
699 SDOperand N2 = Node->getOperand(2);
700 unsigned SubReg = getVR(N1, VRBaseMap);
701 unsigned SubIdx = cast(N2)->getValue();
710702
711703 // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
712704 // to allow coalescing in the allocator
744736 }
745737
746738 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
747 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
748 if (!isUndefInput)
749 AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap);
739
740 // If N0 is a constant then it indicates the insert is being done
741 // into a target specific constant value, not a register.
742 if (const ConstantSDNode *SD = dyn_cast(N0))
743 MI->addOperand(MachineOperand::CreateImm(SD->getValue()));
744 else
745 AddOperand(MI, N0, 0, 0, VRBaseMap);
746 // Add the subregster being inserted
747 AddOperand(MI, N1, 0, 0, VRBaseMap);
750748 MI->addOperand(MachineOperand::CreateImm(SubIdx));
751749 } else
752750 assert(0 && "Node is not a subreg insert or extract");
262262 /// flags. But currently we have but one flag.
263263 def ptr_rc;
264264
265 /// unknown definition - Mark this operand as being of unknown type, causing
266 /// it to be resolved by inference in the context it is used.
267 def unknown;
268
265269 /// Operand Types - These provide the built-in operand types that may be used
266270 /// by a target. Targets can optionally provide their own operand types as
267271 /// needed, though this should not be needed for RISC targets.
350354 let hasCtrlDep = 1;
351355 }
352356 def EXTRACT_SUBREG : Instruction {
353 let OutOperandList = (ops variable_ops);
354 let InOperandList = (ops variable_ops);
357 let OutOperandList = (ops unknown:$dst);
358 let InOperandList = (ops unknown:$supersrc, i32imm:$subidx);
355359 let AsmString = "";
356360 let Namespace = "TargetInstrInfo";
357361 let neverHasSideEffects = 1;
358362 }
359363 def INSERT_SUBREG : Instruction {
360 let OutOperandList = (ops variable_ops);
361 let InOperandList = (ops variable_ops);
364 let OutOperandList = (ops unknown:$dst);
365 let InOperandList = (ops unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
362366 let AsmString = "";
363367 let Namespace = "TargetInstrInfo";
364368 let neverHasSideEffects = 1;
15321532 AddToISelQueue(N0);
15331533 if (NVT == MVT::i64 || NVT == MVT::i32 || NVT == MVT::i16) {
15341534 SDOperand SRIdx;
1535 SDOperand ImplVal = CurDAG->getTargetConstant(X86::IMPL_VAL_UNDEF,
1536 MVT::i32);
15351537 switch(N0.getValueType()) {
15361538 case MVT::i32:
1537 SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
1539 SRIdx = CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
1540 // x86-64 zero extends 32-bit inserts int 64-bit registers
1541 if (Subtarget->is64Bit())
1542 ImplVal = CurDAG->getTargetConstant(X86::IMPL_VAL_ZERO, MVT::i32);
15381543 break;
15391544 case MVT::i16:
1540 SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
1545 SRIdx = CurDAG->getTargetConstant(X86::SUBREG_16BIT, MVT::i32);
15411546 break;
15421547 case MVT::i8:
15431548 if (Subtarget->is64Bit())
1544 SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1549 SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
15451550 break;
15461551 default: assert(0 && "Unknown any_extend!");
15471552 }
15481553 if (SRIdx.Val) {
15491554 SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG,
1550 NVT, N0, SRIdx);
1555 NVT, ImplVal, N0, SRIdx);
15511556
15521557 #ifndef NDEBUG
15531558 DOUT << std::string(Indent-2, ' ') << "=> ";
4545 COND_INVALID
4646 };
4747
48 // X86 specific implict values used for subregister inserts.
49 // This can be used to model the fact that x86-64 by default
50 // inserts 32-bit values into 64-bit registers implicitly containing zeros.
51 enum ImplicitVal {
52 IMPL_VAL_UNDEF = 0,
53 IMPL_VAL_ZERO = 1
54 };
55
4856 // Turn condition code into conditional branch opcode.
4957 unsigned GetCondBranchFromCond(CondCode CC);
5058
159159
160160 // Branch targets have OtherVT type.
161161 def brtarget : Operand;
162
163 // These should match the enum X86::ImplicitVal
164 def x86_impl_val_undef : PatLeaf<(i32 0)>;
165 def x86_impl_val_zero : PatLeaf<(i32 1)>;
162166
163167 //===----------------------------------------------------------------------===//
164168 // X86 Complex Pattern Definitions.
2828 namespace N86 {
2929 enum {
3030 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
31 };
32 }
33
34 namespace X86 {
35 /// SubregIndex - The index of various sized subregister classes. Note that
36 /// these indices must be kept in sync with the class indices in the
37 /// X86RegisterInfo.td file.
38 enum SubregIndex {
39 SUBREG_8BIT = 1, SUBREG_16BIT = 2, SUBREG_32BIT = 3
3140 };
3241 }
3342
175175 // sub registers for each register.
176176 //
177177
178 def x86_subreg_8bit : PatLeaf<(i32 1)>;
179 def x86_subreg_16bit : PatLeaf<(i32 2)>;
180 def x86_subreg_32bit : PatLeaf<(i32 3)>;
181
178182 def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
179183 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
180184 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,