llvm.org GIT mirror llvm / 1f4a80f
Add extra operand to CALLSEQ_START to keep frame part set up previously Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302527 91177308-0d34-0410-b5e6-96231b3b80d8 Serge Pavlov 3 years ago
63 changed file(s) with 190 addition(s) and 169 deletion(s). Raw diff Collapse all Expand all
643643 /// of a call sequence, and carry arbitrary information that target might
644644 /// want to know. The first operand is a chain, the rest are specified by
645645 /// the target and not touched by the DAG optimizers.
646 /// Targets that may use stack to pass call arguments define additional
647 /// operands:
648 /// - size of the call frame part that must be set up within the
649 /// CALLSEQ_START..CALLSEQ_END pair,
650 /// - part of the call frame prepared prior to CALLSEQ_START.
651 /// Both these parameters must be constants, their sum is the total call
652 /// frame size.
646653 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
647654 CALLSEQ_START, // Beginning of a call sequence
648655 CALLSEQ_END, // End of a call sequence
736736 /// \brief Create a logical NOT operation as (XOR Val, BooleanOne).
737737 SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);
738738
739 /// Return a new CALLSEQ_START node, which always must have a glue result
740 /// (to ensure it's not CSE'd). CALLSEQ_START does not have a useful SDLoc.
741 SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL) {
739 /// Return a new CALLSEQ_START node, that starts new call frame, in which
740 /// InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and
741 /// OutSize specifies part of the frame set up prior to the sequence.
742 SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize,
743 const SDLoc &DL) {
742744 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
743 SDValue Ops[] = { Chain, Op };
745 SDValue Ops[] = { Chain,
746 getIntPtrConstant(InSize, DL, true),
747 getIntPtrConstant(OutSize, DL, true) };
744748 return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
745749 }
746750
171171 /// inalloca arguments. This function reports only the size of the frame part
172172 /// that is set up between the frame setup and destroy pseudo instructions.
173173 int64_t getFrameSize(const MachineInstr &I) const {
174 assert(isFrameInstr(I));
174 assert(isFrameInstr(I) && "Not a frame instruction");
175175 assert(I.getOperand(0).getImm() >= 0);
176176 return I.getOperand(0).getImm();
177 }
178
179 /// Returns the total frame size, which is made up of the space set up inside
180 /// the pair of frame start-stop instructions and the space that is set up
181 /// prior to the pair.
182 int64_t getFrameTotalSize(const MachineInstr &I) const {
183 if (isFrameSetup(I)) {
184 assert(I.getOperand(1).getImm() >= 0 && "Frame size must not be negative");
185 return getFrameSize(I) + I.getOperand(1).getImm();
186 }
187 return getFrameSize(I);
177188 }
178189
179190 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
280280 ]>;
281281
282282 class SDCallSeqStart constraints> :
283 SDTypeProfile<0, 1, constraints>;
283 SDTypeProfile<0, 2, constraints>;
284284 class SDCallSeqEnd constraints> :
285285 SDTypeProfile<0, 2, constraints>;
286286
20622062 if (I.getOpcode() == FrameSetupOpcode) {
20632063 if (BBState.ExitIsSetup)
20642064 report("FrameSetup is after another FrameSetup", &I);
2065 BBState.ExitValue -= TII->getFrameSize(I);
2065 BBState.ExitValue -= TII->getFrameTotalSize(I);
20662066 BBState.ExitIsSetup = true;
20672067 }
20682068
20692069 if (I.getOpcode() == FrameDestroyOpcode) {
2070 int Size = TII->getFrameSize(I);
2070 int Size = TII->getFrameTotalSize(I);
20712071 if (!BBState.ExitIsSetup)
20722072 report("FrameDestroy is not after a FrameSetup", &I);
20732073 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
621621 // have to worry about calling conventions and target-specific lowering code.
622622 // Instead we perform the call lowering right here.
623623 //
624 // CALLSEQ_START(0...)
624 // CALLSEQ_START(0, 0...)
625625 // STACKMAP(id, nbytes, ...)
626626 // CALLSEQ_END(0, 0)
627627 //
14921492
14931493 // Chain the dynamic stack allocation so that it doesn't modify the stack
14941494 // pointer when other instructions are using the stack.
1495 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1495 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
14961496
14971497 SDValue Size = Tmp2.getOperand(1);
14981498 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
74397439 // have to worry about calling conventions and target specific lowering code.
74407440 // Instead we perform the call lowering right here.
74417441 //
7442 // chain, flag = CALLSEQ_START(chain, 0)
7442 // chain, flag = CALLSEQ_START(chain, 0, 0)
74437443 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
74447444 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
74457445 //
7446 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7446 Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL);
74477447 InFlag = Chain.getValue(1);
74487448
74497449 // Add the and constants.
379379 MIRBuilder.buildSequence(OrigRet.Reg, SplitRegs, RegOffsets);
380380 }
381381
382 CallSeqStart.addImm(Handler.StackSize);
382 CallSeqStart.addImm(Handler.StackSize).addImm(0);
383383 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
384384 .addImm(Handler.StackSize)
385385 .addImm(0);
30133013 // Issue CALLSEQ_START
30143014 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
30153015 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
3016 .addImm(NumBytes);
3016 .addImm(NumBytes).addImm(0);
30173017
30183018 // Process the args.
30193019 for (CCValAssign &VA : ArgLocs) {
32483248 // Adjust the stack pointer for the new arguments...
32493249 // These operations are automatically eliminated by the prolog/epilog pass
32503250 if (!IsSibCall)
3251 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
3252 true),
3253 DL);
3251 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
32543252
32553253 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
32563254 getPointerTy(DAG.getDataLayout()));
155155 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
156156 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
157157 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
158 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
158 SDCallSeqStart<[ SDTCisVT<0, i32>,
159 SDTCisVT<1, i32> ]>,
159160 [SDNPHasChain, SDNPOutGlue]>;
160161 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
161162 SDCallSeqEnd<[ SDTCisVT<0, i32>,
327328 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
328329 // We set Sched to empty list because we expect these instructions to simply get
329330 // removed in most cases.
330 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
331 [(AArch64callseq_start timm:$amt)]>, Sched<[]>;
331 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
332 [(AArch64callseq_start timm:$amt1, timm:$amt2)]>,
333 Sched<[]>;
332334 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
333335 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>,
334336 Sched<[]>;
403403 /// Returns predicate register associated with the given frame instruction.
404404 unsigned getFramePred(const MachineInstr &MI) const {
405405 assert(isFrameInstr(MI));
406 if (isFrameSetup(MI))
407 // Operands of ADJCALLSTACKDOWN:
408 // - argument declared in ADJCALLSTACKDOWN pattern:
409 // 0 - frame size
410 // 1 - predicate code (like ARMCC::AL)
411 // - added by predOps:
412 // 2 - predicate reg
413 return MI.getOperand(2).getReg();
414 assert(MI.getOpcode() == ARM::ADJCALLSTACKUP ||
415 MI.getOpcode() == ARM::tADJCALLSTACKUP);
416 // Operands of ADJCALLSTACKUP:
417 // - argument declared in ADJCALLSTACKUP pattern:
406 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
407 // - argument declared in the pattern:
418408 // 0 - frame size
419 // 1 - arg of CALLSEQ_END
420 // 2 - predicate code
409 // 1 - arg of CALLSEQ_START/CALLSEQ_END
410 // 2 - predicate code (like ARMCC::AL)
421411 // - added by predOps:
422412 // 3 - predicate reg
423413 return MI.getOperand(3).getReg();
432432
433433 // We now know the size of the stack - update the ADJCALLSTACKDOWN
434434 // accordingly.
435 CallSeqStart.addImm(ArgHandler.StackSize).add(predOps(ARMCC::AL));
435 CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
436436
437437 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
438438 .addImm(ArgHandler.StackSize)
19481948 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
19491949 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
19501950 TII.get(AdjStackDown))
1951 .addImm(NumBytes));
1951 .addImm(NumBytes).addImm(0));
19521952
19531953 // Process the args.
19541954 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
18161816 // Adjust the stack pointer for the new arguments...
18171817 // These operations are automatically eliminated by the prolog/epilog pass
18181818 if (!isSibCall)
1819 Chain = DAG.getCALLSEQ_START(Chain,
1820 DAG.getIntPtrConstant(NumBytes, dl, true), dl);
1819 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
18211820
18221821 SDValue StackPtr =
18231822 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1515 //
1616
1717 // Type profiles.
18 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
18 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
19 SDTCisVT<1, i32> ]>;
1920 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
2021 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
2122 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
19671968 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
19681969
19691970 def ADJCALLSTACKDOWN :
1970 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1971 [(ARMcallseq_start timm:$amt)]>;
1971 PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary,
1972 [(ARMcallseq_start timm:$amt, timm:$amt2)]>;
19721973 }
19731974
19741975 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
283283 Requires<[IsThumb, IsThumb1Only]>;
284284
285285 def tADJCALLSTACKDOWN :
286 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
287 [(ARMcallseq_start imm:$amt)]>,
286 PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2), NoItinerary,
287 [(ARMcallseq_start imm:$amt, imm:$amt2)]>,
288288 Requires<[IsThumb, IsThumb1Only]>;
289289 }
290290
374374
375375 DebugLoc DL = MI->getDebugLoc();
376376 unsigned int Opcode = MI->getOpcode();
377 int Amount = MI->getOperand(0).getImm();
377 int Amount = TII.getFrameSize(*MI);
378378
379379 // Adjcallstackup does not need to allocate stack space for the call, instead
380380 // we insert push instructions that will allocate the necessary stack.
11651165 // Get a count of how many bytes are to be pushed on the stack.
11661166 unsigned NumBytes = CCInfo.getNextStackOffset();
11671167
1168 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1169 DL);
1168 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
11701169
11711170 SmallVector, 8> RegsToPass;
11721171
1616 // AVR Type Profiles
1717 //===----------------------------------------------------------------------===//
1818
19 def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
19 def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
2020 def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
2121 def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
2222 def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
332332 Uses = [SP] in
333333 {
334334 def ADJCALLSTACKDOWN : Pseudo<(outs),
335 (ins i16imm:$amt),
335 (ins i16imm:$amt, i16imm:$amt2),
336336 "#ADJCALLSTACKDOWN",
337 [(AVRcallseq_start timm:$amt)]>;
337 [(AVRcallseq_start timm:$amt, timm:$amt2)]>;
338338
339339 // R31R30 is used to update SP, since it is a scratch reg and this instruction
340340 // is placed after the function call then R31R30 should be always free.
256256 }
257257
258258 auto PtrVT = getPointerTy(MF.getDataLayout());
259 Chain = DAG.getCALLSEQ_START(
260 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL);
259 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
261260
262261 SmallVector, MaxArgs> RegsToPass;
263262
1515 // Instruction Operands and Patterns
1616
1717 // These are target-independent nodes, but have target-specific formats.
18 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
18 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
19 SDTCisVT<1, iPTR>]>;
1920 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
2021 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
2122 def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
444445
445446 // ADJCALLSTACKDOWN/UP pseudo insns
446447 let Defs = [R11], Uses = [R11] in {
447 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
448 "#ADJCALLSTACKDOWN $amt",
449 [(BPFcallseq_start timm:$amt)]>;
448 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
449 "#ADJCALLSTACKDOWN $amt1 $amt2",
450 [(BPFcallseq_start timm:$amt1, timm:$amt2)]>;
450451 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
451452 "#ADJCALLSTACKUP $amt1 $amt2",
452453 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
847847
848848 SDValue Glue;
849849 if (!IsTailCall) {
850 SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
851 Chain = DAG.getCALLSEQ_START(Chain, C, dl);
850 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
852851 Glue = Chain.getValue(1);
853852 }
854853
713713 def: Pat<(i1 1), (PS_true)>;
714714
715715 // Pseudo instructions.
716 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
716 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
717 SDTCisVT<1, i32> ]>;
717718 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
718719 SDTCisVT<1, i32> ]>;
719720
731732 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
732733
733734
734 def: Pat<(callseq_start timm:$amt),
735 (ADJCALLSTACKDOWN imm:$amt)>;
735 def: Pat<(callseq_start timm:$amt, timm:$amt2),
736 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>;
736737 def: Pat<(callseq_end timm:$amt1, timm:$amt2),
737738 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>;
738739
7979 [(set I1:$dst, 0)], "", C2_andn.Itinerary, TypeCR>;
8080
8181 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
82 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
82 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
8383 ".error \"should not emit\" ", []>;
8484
8585 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
648648 ByValArgs.push_back(FIPtr);
649649 }
650650
651 Chain = DAG.getCALLSEQ_START(
652 Chain,
653 DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
654 DL);
651 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
655652
656653 SmallVector, 4> RegsToPass;
657654 SmallVector MemOpChains;
2121 // -------------------------------------------------- //
2222
2323 // These are target-independent nodes, but have target-specific formats.
24 def SDT_LanaiCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
24 def SDT_LanaiCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
25 SDTCisVT<1, i32>]>;
2526 def SDT_LanaiCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
2627 SDTCisVT<1, i32>]>;
2728 def SDT_LanaiCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
749750 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
750751 // sub / add which can clobber SP.
751752 let Defs = [SP], Uses = [SP] in {
752 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
753 "#ADJCALLSTACKDOWN $amt",
754 [(CallSeqStart timm:$amt)]>;
753 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
754 "#ADJCALLSTACKDOWN $amt1 $amt2",
755 [(CallSeqStart timm:$amt1, timm:$amt2)]>;
755756 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
756757 "#ADJCALLSTACKUP $amt1 $amt2",
757758 [(CallSeqEnd timm:$amt1, timm:$amt2)]>;
235235 // adjcallstackdown instruction into 'add SP, '
236236 // TODO: consider using push / pop instead of sub + store / add
237237 MachineInstr &Old = *I;
238 uint64_t Amount = Old.getOperand(0).getImm();
238 uint64_t Amount = TII.getFrameSize(Old);
239239 if (Amount != 0) {
240240 // We need to keep the stack aligned properly. To do this, we round the
241241 // amount of space needed for the outgoing arguments up to the next
251251 } else {
252252 assert(Old.getOpcode() == TII.getCallFrameDestroyOpcode());
253253 // factor out the amount the callee already popped.
254 uint64_t CalleeAmt = Old.getOperand(1).getImm();
255 Amount -= CalleeAmt;
254 Amount -= TII.getFramePoppedByCallee(Old);
256255 if (Amount)
257256 New = BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::ADD16ri),
258257 MSP430::SP)
271270 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
272271 // If we are performing frame pointer elimination and if the callee pops
273272 // something off the stack pointer, add it back.
274 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
273 if (uint64_t CalleeAmt = TII.getFramePoppedByCallee(*I)) {
275274 MachineInstr &Old = *I;
276275 MachineInstr *New =
277276 BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP)
614614 unsigned NumBytes = CCInfo.getNextStackOffset();
615615 auto PtrVT = getPointerTy(DAG.getDataLayout());
616616
617 Chain = DAG.getCALLSEQ_START(Chain,
618 DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
617 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
619618
620619 SmallVector, 4> RegsToPass;
621620 SmallVector MemOpChains;
8484 MachineBasicBlock *FBB, ArrayRef Cond,
8585 const DebugLoc &DL,
8686 int *BytesAdded = nullptr) const override;
87
88 int64_t getFramePoppedByCallee(const MachineInstr &I) const {
89 assert(isFrameInstr(I) && "Not a frame instruction");
90 assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative");
91 return I.getOperand(1).getImm();
92 }
8793 };
8894
8995 }
2222 // Type Profiles.
2323 //===----------------------------------------------------------------------===//
2424 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
25 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
25 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>,
26 SDTCisVT<1, i16>]>;
2627 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
2728 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
2829 SDTCisPtrTy<0>]>;
112113 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
113114 // sub / add which can clobber SR.
114115 let Defs = [SP, SR], Uses = [SP] in {
115 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
116117 "#ADJCALLSTACKDOWN",
117 [(MSP430callseq_start timm:$amt)]>;
118 [(MSP430callseq_start timm:$amt1, timm:$amt2)]>;
118119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
119120 "#ADJCALLSTACKUP",
120121 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
11321132 if (NumBytes < 16)
11331133 NumBytes = 16;
11341134
1135 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1135 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
11361136 // Process the args.
11371137 MVT firstMVT;
11381138 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
27862786 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
27872787
27882788 if (!IsTailCall)
2789 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2789 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
27902790
27912791 SDValue StackPtr =
27922792 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2020 SDTCisSameAs<1, 2>,
2121 SDTCisSameAs<3, 4>,
2222 SDTCisInt<4>]>;
23 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
23 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2424 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2525 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
2626 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
17181718 }
17191719
17201720 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1721 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1722 [(callseq_start timm:$amt)]>;
1721 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1722 [(callseq_start timm:$amt1, timm:$amt2)]>;
17231723 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
17241724 [(callseq_end timm:$amt1, timm:$amt2)]>;
17251725 }
14291429 return Chain;
14301430
14311431 SDValue tempChain = Chain;
1432 Chain = DAG.getCALLSEQ_START(
1433 Chain, DAG.getIntPtrConstant(uniqueCallSite, dl, true), dl);
1432 Chain = DAG.getCALLSEQ_START(Chain, uniqueCallSite, 0, dl);
14341433 SDValue InFlag = Chain.getValue(1);
14351434
14361435 unsigned paramCount = 0;
31003100 (CBranchOther Int1Regs:$a, bb:$target)>;
31013101
31023102 // Call
3103 def SDT_NVPTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
3103 def SDT_NVPTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
3104 SDTCisVT<1, i32>]>;
31043105 def SDT_NVPTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
31053106
31063107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_NVPTXCallSeqStart,
31253126 : NVPTXInst;
31263127
31273128 def Callseq_Start :
3128 NVPTXInst<(outs), (ins i32imm:$amt),
3129 "\\{ // callseq $amt\n"
3129 NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
3130 "\\{ // callseq $amt1, $amt2\n"
31303131 "\t.reg .b32 temp_param_reg;",
3131 [(callseq_start timm:$amt)]>;
3132 [(callseq_start timm:$amt1, timm:$amt2)]>;
31323133 def Callseq_End :
31333134 NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
31343135 "\\} // callseq $amt1",
13291329 // Issue CALLSEQ_START.
13301330 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
13311331 TII.get(TII.getCallFrameSetupOpcode()))
1332 .addImm(NumBytes);
1332 .addImm(NumBytes).addImm(0);
13331333
13341334 // Prepare to assign register arguments. Every argument uses up a
13351335 // GPR protocol register even if it's passed in a floating-point
49484948
49494949 // Adjust the stack pointer for the new arguments...
49504950 // These operations are automatically eliminated by the prolog/epilog pass
4951 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4952 dl);
4951 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
49534952 SDValue CallSeqStart = Chain;
49544953
49554954 // Load the return address and frame pointer so it can be moved somewhere else
49994998 Flags, DAG, dl);
50004999
50015000 // This must go outside the CALLSEQ_START..END.
5002 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
5003 CallSeqStart.getNode()->getOperand(1),
5004 SDLoc(MemcpyCall));
5001 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
5002 SDLoc(MemcpyCall));
50055003 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
50065004 NewCallSeqStart.getNode());
50075005 Chain = CallSeqStart = NewCallSeqStart;
50825080 CallSeqStart.getNode()->getOperand(0),
50835081 Flags, DAG, dl);
50845082 // The MEMCPY must go outside the CALLSEQ_START..END.
5085 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
5086 CallSeqStart.getNode()->getOperand(1),
5087 SDLoc(MemcpyCall));
5083 int64_t FrameSize = CallSeqStart.getConstantOperandVal(1);
5084 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
5085 SDLoc(MemcpyCall));
50885086 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
50895087 NewCallSeqStart.getNode());
50905088 return NewCallSeqStart;
52675265 // Adjust the stack pointer for the new arguments...
52685266 // These operations are automatically eliminated by the prolog/epilog pass
52695267 if (!IsSibCall)
5270 Chain = DAG.getCALLSEQ_START(Chain,
5271 DAG.getIntPtrConstant(NumBytes, dl, true), dl);
5268 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
52725269 SDValue CallSeqStart = Chain;
52735270
52745271 // Load the return address and frame pointer so it can be move somewhere else
58275824
58285825 // Adjust the stack pointer for the new arguments...
58295826 // These operations are automatically eliminated by the prolog/epilog pass
5830 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5831 dl);
5827 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
58325828 SDValue CallSeqStart = Chain;
58335829
58345830 // Load the return address and frame pointer so it can be move somewhere else
3232 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
3333 ]>;
3434
35 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
35 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
36 SDTCisVT<1, i32> ]>;
3637 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
3738 SDTCisVT<1, i32> ]>;
3839 def SDT_PPCvperm : SDTypeProfile<1, 3, [
10981099
10991100 let hasCtrlDep = 1 in {
11001101 let Defs = [R1], Uses = [R1] in {
1101 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1102 [(callseq_start timm:$amt)]>;
1103 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1102 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
1103 "#ADJCALLSTACKDOWN $amt1 $amt2",
1104 [(callseq_start timm:$amt1, timm:$amt2)]>;
1105 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
1106 "#ADJCALLSTACKUP $amt1 $amt2",
11041107 [(callseq_end timm:$amt1, timm:$amt2)]>;
11051108 }
11061109
9898 // Don't really need to save data to the stack - the clobbered
9999 // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
100100 // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
101 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0);
101 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
102 .addImm(0);
102103
103104 // Expand into two ops built prior to the existing instruction.
104105 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
772772 }
773773 }
774774
775 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
776 dl);
775 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);
777776
778777 SmallVector, 8> RegsToPass;
779778 SmallVector MemOpChains;
11641163 // Adjust the stack pointer to make room for the arguments.
11651164 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
11661165 // with more than 6 arguments.
1167 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1168 DL);
1166 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
11691167
11701168 // Collect the set of registers to pass to the function and their values.
11711169 // This will be emitted as a sequence of CopyToReg nodes glued to the call
20572055 SDValue Chain = DAG.getEntryNode();
20582056 SDValue InFlag;
20592057
2060 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL);
2058 Chain = DAG.getCALLSEQ_START(Chain, 1, 0, DL);
20612059 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
20622060 InFlag = Chain.getValue(1);
20632061 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
194194 [SDNPHasChain, SDNPSideEffect]>;
195195
196196 // These are target-independent nodes, but have target-specific formats.
197 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
197 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
198 SDTCisVT<1, i32> ]>;
198199 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
199200 SDTCisVT<1, i32> ]>;
200201
403404 }
404405
405406 let Defs = [O6], Uses = [O6] in {
406 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
407 "!ADJCALLSTACKDOWN $amt",
408 [(callseq_start timm:$amt)]>;
407 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
408 "!ADJCALLSTACKDOWN $amt1, $amt2",
409 [(callseq_start timm:$amt1, timm:$amt2)]>;
409410 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
410411 "!ADJCALLSTACKUP $amt1",
411412 [(callseq_end timm:$amt1, timm:$amt2)]>;
11091109
11101110 // Mark the start of the call.
11111111 if (!IsTailCall)
1112 Chain = DAG.getCALLSEQ_START(Chain,
1113 DAG.getConstant(NumBytes, DL, PtrVT, true),
1114 DL);
1112 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
11151113
11161114 // Copy argument values to their designated locations.
11171115 SmallVector, 9> RegsToPass;
1111 //===----------------------------------------------------------------------===//
1212
1313 let hasNoSchedulingInfo = 1 in {
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
15 [(callseq_start timm:$amt1, timm:$amt2)]>;
1616 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
1717 [(callseq_end timm:$amt1, timm:$amt2)]>;
1818 }
99 //===----------------------------------------------------------------------===//
1010 // Type profiles
1111 //===----------------------------------------------------------------------===//
12 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
12 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>,
13 SDTCisVT<1, i64>]>;
1314 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
1415 SDTCisVT<1, i64>]>;
1516 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
1818 // Call sequence markers. These have an immediate which represents the amount of
1919 // stack space to allocate or free, which is used for varargs lowering.
2020 let Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 in {
21 def ADJCALLSTACKDOWN : I<(outs), (ins i32imm:$amt),
22 [(WebAssemblycallseq_start timm:$amt)]>;
21 def ADJCALLSTACKDOWN : I<(outs), (ins i32imm:$amt, i32imm:$amt2),
22 [(WebAssemblycallseq_start timm:$amt, timm:$amt2)]>;
2323 def ADJCALLSTACKUP : I<(outs), (ins i32imm:$amt, i32imm:$amt2),
2424 [(WebAssemblycallseq_end timm:$amt, timm:$amt2)]>;
2525 } // isCodeGenOnly = 1
2424 // WebAssembly-specific DAG Node Types.
2525 //===----------------------------------------------------------------------===//
2626
27 def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
27 def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
28 SDTCisVT<1, iPTR>]>;
2829 def SDT_WebAssemblyCallSeqEnd :
2930 SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
3031 def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
32923292 // Issue CALLSEQ_START
32933293 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
32943294 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
3295 .addImm(NumBytes).addImm(0);
3295 .addImm(NumBytes).addImm(0).addImm(0);
32963296
32973297 // Walk the register/memloc assignments, inserting copies/loads.
32983298 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
34143414 }
34153415
34163416 if (!IsSibcall)
3417 Chain = DAG.getCALLSEQ_START(
3418 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3417 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
3418 NumBytes - NumBytesToPush, dl);
34193419
34203420 SDValue RetAddrFrIdx;
34213421 // Load return address for tail calls.
1472414724 // location.
1472514725 SDValue Chain = DAG.getEntryNode();
1472614726 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14727 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, DL, true), DL);
14727 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
1472814728 SDValue Args[] = { Chain, Offset };
1472914729 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
1473014730 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
1857118571
1857218572 // Chain the dynamic stack allocation so that it doesn't modify the stack
1857318573 // pointer when other instructions are using the stack.
18574 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
18574 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1857518575
1857618576 bool Is64Bit = Subtarget.is64Bit();
1857718577 MVT SPTy = getPointerTy(DAG.getDataLayout());
2578625786 // Emit CALLSEQ_START right before the instruction.
2578725787 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2578825788 MachineInstrBuilder CallseqStart =
25789 BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0);
25789 BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0).addImm(0);
2579025790 BB->insert(MachineBasicBlock::iterator(MI), CallseqStart);
2579125791
2579225792 // Emit CALLSEQ_END right after the instruction.
4242 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
4343 // sub / add which can clobber EFLAGS.
4444 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
45 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
45 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
46 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
4647 "#ADJCALLSTACKDOWN",
4748 []>,
4849 Requires<[NotLP64]>;
5152 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
5253 Requires<[NotLP64]>;
5354 }
54 def : Pat<(X86callseq_start timm:$amt1),
55 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
55 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
56 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
5657
5758
5859 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
6162 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
6263 // sub / add which can clobber EFLAGS.
6364 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
64 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
66 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
6567 "#ADJCALLSTACKDOWN",
6668 []>,
6769 Requires<[IsLP64]>;
7072 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
7173 Requires<[IsLP64]>;
7274 }
73 def : Pat<(X86callseq_start timm:$amt1),
74 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
75 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
76 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
7577
7678
7779 // x86-64 va_start lowering magic.
185185 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
186186 int64_t getFrameAdjustment(const MachineInstr &I) const {
187187 assert(isFrameInstr(I));
188 if (isFrameSetup(I))
189 return I.getOperand(2).getImm();
188190 return I.getOperand(1).getImm();
189191 }
190192
192194 /// instruction.
193195 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
194196 assert(isFrameInstr(I));
195 I.getOperand(1).setImm(V);
197 if (isFrameSetup(I))
198 I.getOperand(2).setImm(V);
199 else
200 I.getOperand(1).setImm(V);
196201 }
197202
198203 /// getSPAdjust - This returns the stack pointer adjustment made by
8383
8484 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
8585
86 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
86 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
87 SDTCisVT<1, i32>]>;
8788 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
8889 SDTCisVT<1, i32>]>;
8990
11301130 unsigned NumBytes = RetCCInfo.getNextStackOffset();
11311131 auto PtrVT = getPointerTy(DAG.getDataLayout());
11321132
1133 Chain = DAG.getCALLSEQ_START(Chain,
1134 DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
1133 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
11351134
11361135 SmallVector, 4> RegsToPass;
11371136 SmallVector MemOpChains;
7272 [SDNPHasChain, SDNPMayLoad]>;
7373
7474 // These are target-independent nodes, but have target-specific formats.
75 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
75 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
76 SDTCisVT<1, i32> ]>;
7677 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
77 SDTCisVT<1, i32> ]>;
78 SDTCisVT<1, i32> ]>;
7879
7980 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
8081 [SDNPHasChain, SDNPOutGlue]>;
322323 //===----------------------------------------------------------------------===//
323324
324325 let Defs = [SP], Uses = [SP] in {
325 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
326 "# ADJCALLSTACKDOWN $amt",
327 [(callseq_start timm:$amt)]>;
326 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt, i32imm:$amt2),
327 "# ADJCALLSTACKDOWN $amt, $amt2",
328 [(callseq_start timm:$amt, timm:$amt2)]>;
328329 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
329330 "# ADJCALLSTACKUP $amt1",
330331 [(callseq_end timm:$amt1, timm:$amt2)]>;
0 ; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
11
22 ; CHECK-LABEL: name: test_trivial_call
3 ; CHECK: ADJCALLSTACKDOWN 0, implicit-def %sp, implicit %sp
3 ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
44 ; CHECK: BL @trivial_callee, csr_aarch64_aapcs, implicit-def %lr
55 ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
66 declare void @trivial_callee()
185185 ; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42
186186 ; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
187187 ; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
188 ; CHECK: ADJCALLSTACKDOWN 24, implicit-def %sp, implicit %sp
188 ; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def %sp, implicit %sp
189189 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
190190 ; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
191191 ; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
66 store i64 11, i64* %metadata
77 store i64 12, i64* %metadata
88 store i64 13, i64* %metadata
9 ; ISEL: ADJCALLSTACKDOWN 0, implicit-def
9 ; ISEL: ADJCALLSTACKDOWN 0, 0, implicit-def
1010 ; ISEL-NEXT: STACKMAP
1111 ; ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def
1212 call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
13 ; FAST-ISEL: ADJCALLSTACKDOWN 0, implicit-def
13 ; FAST-ISEL: ADJCALLSTACKDOWN 0, 0, implicit-def
1414 ; FAST-ISEL-NEXT: STACKMAP
1515 ; FAST-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def
1616 ret void
420420 define arm_aapcscc void @test_indirect_call(void() *%fptr) {
421421 ; CHECK-LABEL: name: test_indirect_call
422422 ; CHECK: [[FPTR:%[0-9]+]](p0) = COPY %r0
423 ; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
423 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
424424 ; CHECK: BLX [[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
425425 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
426426 entry:
432432
433433 define arm_aapcscc void @test_direct_call() {
434434 ; CHECK-LABEL: name: test_direct_call
435 ; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
435 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
436436 ; CHECK: BLX @call_target, csr_aapcs, implicit-def %lr, implicit %sp
437437 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
438438 entry:
446446 ; CHECK-LABEL: name: test_call_simple_reg_params
447447 ; CHECK-DAG: [[AVREG:%[0-9]+]](p0) = COPY %r0
448448 ; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r1
449 ; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
449 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
450450 ; CHECK-DAG: %r0 = COPY [[BVREG]]
451451 ; CHECK-DAG: %r1 = COPY [[AVREG]]
452452 ; CHECK: BLX @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0
465465 ; CHECK-LABEL: name: test_call_simple_stack_params
466466 ; CHECK-DAG: [[AVREG:%[0-9]+]](p0) = COPY %r0
467467 ; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r1
468 ; CHECK: ADJCALLSTACKDOWN 8, 14, _, implicit-def %sp, implicit %sp
468 ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp
469469 ; CHECK-DAG: %r0 = COPY [[BVREG]]
470470 ; CHECK-DAG: %r1 = COPY [[AVREG]]
471471 ; CHECK-DAG: %r2 = COPY [[BVREG]]
495495 ; CHECK-DAG: [[AVREG:%[0-9]+]](s8) = COPY %r0
496496 ; CHECK-DAG: [[BVREG:%[0-9]+]](s16) = COPY %r1
497497 ; CHECK-DAG: [[CVREG:%[0-9]+]](s1) = COPY %r2
498 ; CHECK: ADJCALLSTACKDOWN 20, 14, _, implicit-def %sp, implicit %sp
498 ; CHECK: ADJCALLSTACKDOWN 20, 0, 14, _, implicit-def %sp, implicit %sp
499499 ; CHECK: [[SEXTA:%[0-9]+]](s32) = G_SEXT [[AVREG]](s8)
500500 ; CHECK: %r0 = COPY [[SEXTA]]
501501 ; CHECK: [[ZEXTA:%[0-9]+]](s32) = G_ZEXT [[AVREG]](s8)
546546 ; CHECK-LABEL: name: test_call_vfpcc_fp_params
547547 ; CHECK-DAG: [[AVREG:%[0-9]+]](s64) = COPY %d0
548548 ; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %s2
549 ; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
549 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
550550 ; CHECK-DAG: %s0 = COPY [[BVREG]]
551551 ; CHECK-DAG: %d1 = COPY [[AVREG]]
552552 ; CHECK: BLX @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0
568568 ; LITTLE-DAG: [[AVREG:%[0-9]+]](s64) = G_SEQUENCE [[A1]](s32), 0, [[A2]](s32), 32
569569 ; BIG-DAG: [[AVREG:%[0-9]+]](s64) = G_SEQUENCE [[A2]](s32), 0, [[A1]](s32), 32
570570 ; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r2
571 ; CHECK: ADJCALLSTACKDOWN 16, 14, _, implicit-def %sp, implicit %sp
571 ; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp
572572 ; CHECK-DAG: %r0 = COPY [[BVREG]]
573573 ; CHECK-DAG: [[A1:%[0-9]+]](s32) = G_EXTRACT [[AVREG]](s64), 0
574574 ; CHECK-DAG: [[A2:%[0-9]+]](s32) = G_EXTRACT [[AVREG]](s64), 32
607607 define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
608608 ; CHECK-LABEL: name: test_call_different_call_conv
609609 ; CHECK: [[X:%[0-9]+]](s32) = COPY %s0
610 ; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
610 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
611611 ; CHECK: %r0 = COPY [[X]]
612612 ; CHECK: BLX @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0
613613 ; CHECK: [[R:%[0-9]+]](s32) = COPY %r0
160160 bb.1.for.body:
161161 successors: %bb.3.for.end, %bb.2.if.end82
162162
163 ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
163 ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
164164 J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
165165 ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
166166 undef %29.isub_lo = COPY killed %r0
167167 %29.isub_hi = S2_asr_i_r %29.isub_lo, 31
168 ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
168 ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
169169 J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
170170 ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
171171 %32.isub_lo = COPY killed %r0
172172 %7 = S2_extractup %32, 22, 9
173 ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
173 ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
174174 J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
175175 ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
176176 undef %43.isub_lo = COPY killed %r0
178178 %16 = S2_extractup %43, 6, 25
179179 %18 = A2_tfrpi -1
180180 %18 = S2_asl_r_p_acc %18, %47, %16.isub_lo
181 ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
181 ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
182182 J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3
183183 ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
184184 %22 = S2_asl_r_p %18, %8.isub_lo
643643 bb.1.if.then:
644644 successors: %bb.2.while.body
645645
646 ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp
646 ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
647647 CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
648648 ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
649649
662662 bb.4.if.then4:
663663 successors: %bb.5.while.body6
664664
665 ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp
665 ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
666666 CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
667667 ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
668668
5959 liveins: %eax
6060
6161 MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax
62 ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
62 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
6363 %rsi = LEA64r %stack.0.tmp, 1, _, 0, _
6464 %edi = MOV32r0 implicit-def dead %eflags
6565 CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax
66 store i64 11, i64* %metadata
77 store i64 12, i64* %metadata
88 store i64 13, i64* %metadata
9 ; ISEL: ADJCALLSTACKDOWN 0, implicit-def
9 ; ISEL: ADJCALLSTACKDOWN 0, 0, implicit-def
1010 ; ISEL-NEXT: STACKMAP
1111 ; ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def
1212 call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
13 ; FAST-ISEL: ADJCALLSTACKDOWN 0, implicit-def
13 ; FAST-ISEL: ADJCALLSTACKDOWN 0, 0, implicit-def
1414 ; FAST-ISEL-NEXT: STACKMAP
1515 ; FAST-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def
1616 ret void
66 store i64 11, i64* %metadata
77 store i64 12, i64* %metadata
88 store i64 13, i64* %metadata
9 ; ISEL: ADJCALLSTACKDOWN64 0, 0, implicit-def
9 ; ISEL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def
1010 ; ISEL-NEXT: STACKMAP
1111 ; ISEL-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def
1212 call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
13 ; FAST-ISEL: ADJCALLSTACKDOWN64 0, 0, implicit-def
13 ; FAST-ISEL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def
1414 ; FAST-ISEL-NEXT: STACKMAP
1515 ; FAST-ISEL-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def
1616 ret void