llvm.org GIT mirror llvm / 1f072c3
Add ARM big endian Target (armeb, thumbeb) Reviewed at http://llvm-reviews.chandlerc.com/D3095 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205007 91177308-0d34-0410-b5e6-96231b3b80d8 Christian Pirker 6 years ago
23 changed file(s) with 516 addition(s) and 107 deletion(s). Raw diff Collapse all Expand all
4545 enum ArchType {
4646 UnknownArch,
4747
48 arm, // ARM: arm, armv.*, xscale
48 arm, // ARM (little endian): arm, armv.*, xscale
49 armeb, // ARM (big endian): armeb
4950 aarch64, // AArch64 (little endian): aarch64
5051 aarch64_be, // AArch64 (big endian): aarch64_be
5152 hexagon, // Hexagon: hexagon
6263 sparcv9, // Sparcv9: Sparcv9
6364 systemz, // SystemZ: s390x
6465 tce, // TCE (http://tce.cs.tut.fi/): tce
65 thumb, // Thumb: thumb, thumbv.*
66 thumb, // Thumb (little endian): thumb, thumbv.*
67 thumbeb, // Thumb (big endian): thumbeb
6668 x86, // X86: i[3-9]86
6769 x86_64, // X86-64: amd64, x86_64
6870 xcore, // XCore: xcore
507507 *StubAddr = 0xd61f0200; // br ip0
508508
509509 return Addr;
510 } else if (Arch == Triple::arm) {
510 } else if (Arch == Triple::arm || Arch == Triple::armeb) {
511511 // TODO: There is only ARM far stub now. We should add the Thumb stub,
512512 // and stubs for branches Thumb - ARM and ARM - Thumb.
513513 uint32_t *StubAddr = (uint32_t *)Addr;
847847 resolveAArch64Relocation(Section, Offset, Value, Type, Addend);
848848 break;
849849 case Triple::arm: // Fall through.
850 case Triple::armeb:
850851 case Triple::thumb:
852 case Triple::thumbeb:
851853 resolveARMRelocation(Section, Offset, (uint32_t)(Value & 0xffffffffL), Type,
852854 (uint32_t)(Addend & 0xffffffffL));
853855 break;
2121 case aarch64: return "aarch64";
2222 case aarch64_be: return "aarch64_be";
2323 case arm: return "arm";
24 case armeb: return "armeb";
2425 case hexagon: return "hexagon";
2526 case mips: return "mips";
2627 case mipsel: return "mipsel";
3637 case systemz: return "s390x";
3738 case tce: return "tce";
3839 case thumb: return "thumb";
40 case thumbeb: return "thumbeb";
3941 case x86: return "i386";
4042 case x86_64: return "x86_64";
4143 case xcore: return "xcore";
5961 case aarch64_be: return "aarch64";
6062
6163 case arm:
62 case thumb: return "arm";
64 case armeb:
65 case thumb:
66 case thumbeb: return "arm";
6367
6468 case ppc64:
6569 case ppc64le:
167171 .Case("aarch64", aarch64)
168172 .Case("aarch64_be", aarch64_be)
169173 .Case("arm", arm)
174 .Case("armeb", armeb)
170175 .Case("mips", mips)
171176 .Case("mipsel", mipsel)
172177 .Case("mips64", mips64)
183188 .Case("systemz", systemz)
184189 .Case("tce", tce)
185190 .Case("thumb", thumb)
191 .Case("thumbeb", thumbeb)
186192 .Case("x86", x86)
187193 .Case("x86-64", x86_64)
188194 .Case("xcore", xcore)
211217 .Cases("armv5", "armv5e", "thumbv5", "thumbv5e", "armv5")
212218 .Cases("armv6", "thumbv6", "armv6")
213219 .Cases("armv7", "thumbv7", "armv7")
220 .Case("armeb", "armeb")
214221 .Case("r600", "r600")
215222 .Case("nvptx", "nvptx")
216223 .Case("nvptx64", "nvptx64")
236243 // FIXME: It would be good to replace these with explicit names for all the
237244 // various suffixes supported.
238245 .StartsWith("armv", Triple::arm)
246 .Case("armeb", Triple::armeb)
247 .StartsWith("armebv", Triple::armeb)
239248 .Case("thumb", Triple::thumb)
240249 .StartsWith("thumbv", Triple::thumb)
250 .Case("thumbeb", Triple::thumbeb)
251 .StartsWith("thumbebv", Triple::thumbeb)
241252 .Case("msp430", Triple::msp430)
242253 .Cases("mips", "mipseb", "mipsallegrex", Triple::mips)
243254 .Cases("mipsel", "mipsallegrexel", Triple::mipsel)
742753
743754 case llvm::Triple::amdil:
744755 case llvm::Triple::arm:
756 case llvm::Triple::armeb:
745757 case llvm::Triple::hexagon:
746758 case llvm::Triple::le32:
747759 case llvm::Triple::mips:
752764 case llvm::Triple::sparc:
753765 case llvm::Triple::tce:
754766 case llvm::Triple::thumb:
767 case llvm::Triple::thumbeb:
755768 case llvm::Triple::x86:
756769 case llvm::Triple::xcore:
757770 case llvm::Triple::spir:
800813 case Triple::amdil:
801814 case Triple::spir:
802815 case Triple::arm:
816 case Triple::armeb:
803817 case Triple::hexagon:
804818 case Triple::le32:
805819 case Triple::mips:
810824 case Triple::sparc:
811825 case Triple::tce:
812826 case Triple::thumb:
827 case Triple::thumbeb:
813828 case Triple::x86:
814829 case Triple::xcore:
815830 // Already 32-bit.
832847 case Triple::UnknownArch:
833848 case Triple::amdil:
834849 case Triple::arm:
850 case Triple::armeb:
835851 case Triple::hexagon:
836852 case Triple::le32:
837853 case Triple::msp430:
838854 case Triple::r600:
839855 case Triple::tce:
840856 case Triple::thumb:
857 case Triple::thumbeb:
841858 case Triple::xcore:
842859 T.setArch(UnknownArch);
843860 break;
17181718
17191719 // Force static initialization.
17201720 extern "C" void LLVMInitializeARMAsmPrinter() {
1721 RegisterAsmPrinter X(TheARMTarget);
1722 RegisterAsmPrinter Y(TheThumbTarget);
1723 }
1721 RegisterAsmPrinter X(TheARMleTarget);
1722 RegisterAsmPrinter Y(TheARMbeTarget);
1723 RegisterAsmPrinter A(TheThumbleTarget);
1724 RegisterAsmPrinter B(TheThumbbeTarget);
1725 }
7474 clEnumValEnd));
7575
7676 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
77 const std::string &FS, const TargetOptions &Options)
77 const std::string &FS, bool IsLittle,
78 const TargetOptions &Options)
7879 : ARMGenSubtargetInfo(TT, CPU, FS)
7980 , ARMProcFamily(Others)
8081 , ARMProcClass(None)
8182 , stackAlignment(4)
8283 , CPUString(CPU)
84 , IsLittle(IsLittle)
8385 , TargetTriple(TT)
8486 , Options(Options)
8587 , TargetABI(ARM_ABI_UNKNOWN) {
202202 /// CPUString - String name of used CPU.
203203 std::string CPUString;
204204
205 /// IsLittle - The target is Little Endian
206 bool IsLittle;
207
205208 /// TargetTriple - What processor and OS we're targeting.
206209 Triple TargetTriple;
207210
225228 /// of the specified triple.
226229 ///
227230 ARMSubtarget(const std::string &TT, const std::string &CPU,
228 const std::string &FS, const TargetOptions &Options);
231 const std::string &FS, bool IsLittle,
232 const TargetOptions &Options);
229233
230234 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
231235 /// that still makes it profitable to inline the call.
374378
375379 const std::string & getCPUString() const { return CPUString; }
376380
381 bool isLittle() const { return IsLittle; }
382
377383 unsigned getMispredictionPenalty() const;
378384
379385 /// This function returns true if the target has sincos() routine in its
2929
3030 extern "C" void LLVMInitializeARMTarget() {
3131 // Register the target.
32 RegisterTargetMachine X(TheARMTarget);
33 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
32 RegisterTargetMachine<ARMleTargetMachine> X(TheARMleTarget);
33 RegisterTargetMachine Y(TheARMbeTarget);
34 RegisterTargetMachine A(TheThumbleTarget);
35 RegisterTargetMachine B(TheThumbbeTarget);
3436 }
3537
3638
4042 StringRef CPU, StringRef FS,
4143 const TargetOptions &Options,
4244 Reloc::Model RM, CodeModel::Model CM,
43 CodeGenOpt::Level OL)
45 CodeGenOpt::Level OL,
46 bool isLittle)
4447 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, Options),
48 Subtarget(TT, CPU, FS, isLittle, Options),
4649 JITInfo(),
4750 InstrItins(Subtarget.getInstrItineraryData()) {
4851
6467 void ARMTargetMachine::anchor() { }
6568
6669 static std::string computeDataLayout(ARMSubtarget &ST) {
67 // Little endian.
68 std::string Ret = "e";
70 std::string Ret = "";
71
72 if (ST.isLittle())
73 // Little endian.
74 Ret += "e";
75 else
76 // Big endian.
77 Ret += "E";
6978
7079 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
7180
117126 StringRef CPU, StringRef FS,
118127 const TargetOptions &Options,
119128 Reloc::Model RM, CodeModel::Model CM,
120 CodeGenOpt::Level OL)
121 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
129 CodeGenOpt::Level OL,
130 bool isLittle)
131 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
122132 InstrInfo(Subtarget),
123133 DL(computeDataLayout(Subtarget)),
124134 TLInfo(*this),
130140 "support ARM mode execution!");
131141 }
132142
143 void ARMleTargetMachine::anchor() { }
144
145 ARMleTargetMachine::
146 ARMleTargetMachine(const Target &T, StringRef TT,
147 StringRef CPU, StringRef FS, const TargetOptions &Options,
148 Reloc::Model RM, CodeModel::Model CM,
149 CodeGenOpt::Level OL)
150 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
151
152 void ARMbeTargetMachine::anchor() { }
153
154 ARMbeTargetMachine::
155 ARMbeTargetMachine(const Target &T, StringRef TT,
156 StringRef CPU, StringRef FS, const TargetOptions &Options,
157 Reloc::Model RM, CodeModel::Model CM,
158 CodeGenOpt::Level OL)
159 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
160
133161 void ThumbTargetMachine::anchor() { }
134162
135163 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
136164 StringRef CPU, StringRef FS,
137165 const TargetOptions &Options,
138166 Reloc::Model RM, CodeModel::Model CM,
139 CodeGenOpt::Level OL)
140 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
167 CodeGenOpt::Level OL,
168 bool isLittle)
169 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
141170 InstrInfo(Subtarget.hasThumb2()
142171 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
143172 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
149178 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
150179 initAsmInfo();
151180 }
181
182 void ThumbleTargetMachine::anchor() { }
183
184 ThumbleTargetMachine::
185 ThumbleTargetMachine(const Target &T, StringRef TT,
186 StringRef CPU, StringRef FS, const TargetOptions &Options,
187 Reloc::Model RM, CodeModel::Model CM,
188 CodeGenOpt::Level OL)
189 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
190
191 void ThumbbeTargetMachine::anchor() { }
192
193 ThumbbeTargetMachine::
194 ThumbbeTargetMachine(const Target &T, StringRef TT,
195 StringRef CPU, StringRef FS, const TargetOptions &Options,
196 Reloc::Model RM, CodeModel::Model CM,
197 CodeGenOpt::Level OL)
198 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
152199
153200 namespace {
154201 /// ARM Code Generator Pass Configuration Options.
4141 StringRef CPU, StringRef FS,
4242 const TargetOptions &Options,
4343 Reloc::Model RM, CodeModel::Model CM,
44 CodeGenOpt::Level OL);
44 CodeGenOpt::Level OL,
45 bool isLittle);
4546
4647 ARMJITInfo *getJITInfo() override { return &JITInfo; }
4748 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
7677 StringRef CPU, StringRef FS,
7778 const TargetOptions &Options,
7879 Reloc::Model RM, CodeModel::Model CM,
79 CodeGenOpt::Level OL);
80 CodeGenOpt::Level OL,
81 bool isLittle);
8082
8183 const ARMRegisterInfo *getRegisterInfo() const override {
8284 return &InstrInfo.getRegisterInfo();
9496 }
9597 const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
9698 const DataLayout *getDataLayout() const override { return &DL; }
99 };
100
101 /// ARMleTargetMachine - ARM little endian target machine.
102 ///
103 class ARMleTargetMachine : public ARMTargetMachine {
104 virtual void anchor();
105 public:
106 ARMleTargetMachine(const Target &T, StringRef TT,
107 StringRef CPU, StringRef FS, const TargetOptions &Options,
108 Reloc::Model RM, CodeModel::Model CM,
109 CodeGenOpt::Level OL);
110 };
111
112 /// ARMbeTargetMachine - ARM big endian target machine.
113 ///
114 class ARMbeTargetMachine : public ARMTargetMachine {
115 virtual void anchor();
116 public:
117 ARMbeTargetMachine(const Target &T, StringRef TT,
118 StringRef CPU, StringRef FS, const TargetOptions &Options,
119 Reloc::Model RM, CodeModel::Model CM,
120 CodeGenOpt::Level OL);
97121 };
98122
99123 /// ThumbTargetMachine - Thumb target machine.
114138 StringRef CPU, StringRef FS,
115139 const TargetOptions &Options,
116140 Reloc::Model RM, CodeModel::Model CM,
117 CodeGenOpt::Level OL);
141 CodeGenOpt::Level OL,
142 bool isLittle);
118143
119144 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
120145 const ARMBaseRegisterInfo *getRegisterInfo() const override {
140165 const DataLayout *getDataLayout() const override { return &DL; }
141166 };
142167
168 /// ThumbleTargetMachine - Thumb little endian target machine.
169 ///
170 class ThumbleTargetMachine : public ThumbTargetMachine {
171 virtual void anchor();
172 public:
173 ThumbleTargetMachine(const Target &T, StringRef TT,
174 StringRef CPU, StringRef FS, const TargetOptions &Options,
175 Reloc::Model RM, CodeModel::Model CM,
176 CodeGenOpt::Level OL);
177 };
178
179 /// ThumbbeTargetMachine - Thumb big endian target machine.
180 ///
181 class ThumbbeTargetMachine : public ThumbTargetMachine {
182 virtual void anchor();
183 public:
184 ThumbbeTargetMachine(const Target &T, StringRef TT,
185 StringRef CPU, StringRef FS, const TargetOptions &Options,
186 Reloc::Model RM, CodeModel::Model CM,
187 CodeGenOpt::Level OL);
188 };
189
143190 } // end namespace llvm
144191
145192 #endif
92509250
92519251 /// Force static initialization.
92529252 extern "C" void LLVMInitializeARMAsmParser() {
9253 RegisterMCAsmParser X(TheARMTarget);
9254 RegisterMCAsmParser Y(TheThumbTarget);
9253 RegisterMCAsmParser X(TheARMleTarget);
9254 RegisterMCAsmParser Y(TheARMbeTarget);
9255 RegisterMCAsmParser A(TheThumbleTarget);
9256 RegisterMCAsmParser B(TheThumbbeTarget);
92559257 }
92569258
92579259 #define GET_REGISTER_MATCHER
855855
856856
857857 extern "C" void LLVMInitializeARMDisassembler() {
858 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
858 TargetRegistry::RegisterMCDisassembler(TheARMleTarget,
859859 createARMDisassembler);
860 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
860 TargetRegistry::RegisterMCDisassembler(TheARMbeTarget,
861 createARMDisassembler);
862 TargetRegistry::RegisterMCDisassembler(TheThumbleTarget,
863 createThumbDisassembler);
864 TargetRegistry::RegisterMCDisassembler(TheThumbbeTarget,
861865 createThumbDisassembler);
862866 }
863867
4040
4141 class ARMAsmBackend : public MCAsmBackend {
4242 const MCSubtargetInfo* STI;
43 bool isThumbMode; // Currently emitting Thumb code.
43 bool isThumbMode; // Currently emitting Thumb code.
44 bool IsLittleEndian; // Big or little endian.
4445 public:
45 ARMAsmBackend(const Target &T, const StringRef TT)
46 ARMAsmBackend(const Target &T, const StringRef TT, bool IsLittle)
4647 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
47 isThumbMode(TT.startswith("thumb")) {}
48 isThumbMode(TT.startswith("thumb")), IsLittleEndian(IsLittle) {}
4849
4950 ~ARMAsmBackend() {
5051 delete STI;
5960 }
6061
6162 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
62 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
63 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
6364 // This table *must* be in the order that the fixup_* kinds are defined in
6465 // ARMFixupKinds.h.
6566 //
100101 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
101102 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
102103 };
104 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
105 // This table *must* be in the order that the fixup_* kinds are defined in
106 // ARMFixupKinds.h.
107 //
108 // Name Offset (bits) Size (bits) Flags
109 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
111 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
112 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
113 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
114 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
115 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
116 { "fixup_thumb_adr_pcrel_10",8, 8, MCFixupKindInfo::FKF_IsPCRel |
117 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
118 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
119 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
120 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
121 { "fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
122 { "fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
123 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
124 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
125 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
126 { "fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
127 { "fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
128 { "fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel },
129 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
130 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
131 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
132 { "fixup_arm_thumb_cp", 8, 8, MCFixupKindInfo::FKF_IsPCRel |
133 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
134 { "fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel },
135 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
136 { "fixup_arm_movt_hi16", 12, 20, 0 },
137 { "fixup_arm_movw_lo16", 12, 20, 0 },
138 { "fixup_t2_movt_hi16", 12, 20, 0 },
139 { "fixup_t2_movw_lo16", 12, 20, 0 },
140 { "fixup_arm_movt_hi16_pcrel", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
141 { "fixup_arm_movw_lo16_pcrel", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
142 { "fixup_t2_movt_hi16_pcrel", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
143 { "fixup_t2_movw_lo16_pcrel", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
144 };
103145
104146 if (Kind < FirstTargetFixupKind)
105147 return MCAsmBackend::getFixupKindInfo(Kind);
106148
107149 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
108150 "Invalid kind!");
109 return Infos[Kind - FirstTargetFixupKind];
151 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
110152 }
111153
112154 /// processFixupValue - Target hook to process the literal value of a fixup
145187 unsigned getPointerSize() const { return 4; }
146188 bool isThumb() const { return isThumbMode; }
147189 void setIsThumb(bool it) { isThumbMode = it; }
190 bool isLittle() const { return IsLittleEndian; }
148191 };
149192 } // end anonymous namespace
150193
636679 }
637680 }
638681
682 /// getFixupKindContainerSizeBytes - The number of bytes of the
683 /// container involved in big endian.
684 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
685 switch (Kind) {
686 default:
687 llvm_unreachable("Unknown fixup kind!");
688
689 case FK_Data_1:
690 return 1;
691 case FK_Data_2:
692 return 2;
693 case FK_Data_4:
694 return 4;
695
696 case ARM::fixup_arm_thumb_bcc:
697 case ARM::fixup_arm_thumb_cp:
698 case ARM::fixup_thumb_adr_pcrel_10:
699 case ARM::fixup_arm_thumb_br:
700 case ARM::fixup_arm_thumb_cb:
701 // Instruction size is 2 bytes.
702 return 2;
703
704 case ARM::fixup_arm_pcrel_10_unscaled:
705 case ARM::fixup_arm_ldst_pcrel_12:
706 case ARM::fixup_arm_pcrel_10:
707 case ARM::fixup_arm_adr_pcrel_12:
708 case ARM::fixup_arm_uncondbl:
709 case ARM::fixup_arm_condbl:
710 case ARM::fixup_arm_blx:
711 case ARM::fixup_arm_condbranch:
712 case ARM::fixup_arm_uncondbranch:
713 case ARM::fixup_t2_ldst_pcrel_12:
714 case ARM::fixup_t2_condbranch:
715 case ARM::fixup_t2_uncondbranch:
716 case ARM::fixup_t2_pcrel_10:
717 case ARM::fixup_t2_adr_pcrel_12:
718 case ARM::fixup_arm_thumb_bl:
719 case ARM::fixup_arm_thumb_blx:
720 case ARM::fixup_arm_movt_hi16:
721 case ARM::fixup_arm_movw_lo16:
722 case ARM::fixup_arm_movt_hi16_pcrel:
723 case ARM::fixup_arm_movw_lo16_pcrel:
724 case ARM::fixup_t2_movt_hi16:
725 case ARM::fixup_t2_movw_lo16:
726 case ARM::fixup_t2_movt_hi16_pcrel:
727 case ARM::fixup_t2_movw_lo16_pcrel:
728 // Instruction size is 4 bytes.
729 return 4;
730 }
731 }
732
639733 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
640734 unsigned DataSize, uint64_t Value) const {
641735 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
645739 unsigned Offset = Fixup.getOffset();
646740 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
647741
742 // Used to point to big endian bytes.
743 unsigned FullSizeBytes;
744 if (!IsLittleEndian)
745 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
746
648747 // For each byte of the fragment that the fixup touches, mask in the bits from
649748 // the fixup value. The Value has been "split up" into the appropriate
650749 // bitfields above.
651 for (unsigned i = 0; i != NumBytes; ++i)
652 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
750 for (unsigned i = 0; i != NumBytes; ++i) {
751 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
752 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
753 }
653754 }
654755
655756 namespace {
660761 public:
661762 uint8_t OSABI;
662763 ELFARMAsmBackend(const Target &T, const StringRef TT,
663 uint8_t _OSABI)
664 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
764 uint8_t _OSABI, bool _IsLittle)
765 : ARMAsmBackend(T, TT, _IsLittle), OSABI(_OSABI) { }
665766
666767 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
667 return createARMELFObjectWriter(OS, OSABI);
768 return createARMELFObjectWriter(OS, OSABI, isLittle());
668769 }
669770 };
670771
674775 const MachO::CPUSubTypeARM Subtype;
675776 DarwinARMAsmBackend(const Target &T, const StringRef TT,
676777 MachO::CPUSubTypeARM st)
677 : ARMAsmBackend(T, TT), Subtype(st) {
778 : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) {
678779 HasDataInCodeSupport = true;
679780 }
680781
689790
690791 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
691792 const MCRegisterInfo &MRI,
692 StringRef TT, StringRef CPU) {
793 StringRef TT, StringRef CPU,
794 bool isLittle) {
693795 Triple TheTriple(TT);
694796
695797 if (TheTriple.isOSBinFormatMachO()) {
715817 #endif
716818
717819 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
718 return new ELFARMAsmBackend(T, TT, OSABI);
719 }
820 return new ELFARMAsmBackend(T, TT, OSABI, isLittle);
821 }
822
823 MCAsmBackend *llvm::createARMleAsmBackend(const Target &T,
824 const MCRegisterInfo &MRI,
825 StringRef TT, StringRef CPU) {
826 return createARMAsmBackend(T, MRI, TT, CPU, true);
827 }
828
829 MCAsmBackend *llvm::createARMbeAsmBackend(const Target &T,
830 const MCRegisterInfo &MRI,
831 StringRef TT, StringRef CPU) {
832 return createARMAsmBackend(T, MRI, TT, CPU, false);
833 }
834
835 MCAsmBackend *llvm::createThumbleAsmBackend(const Target &T,
836 const MCRegisterInfo &MRI,
837 StringRef TT, StringRef CPU) {
838 return createARMAsmBackend(T, MRI, TT, CPU, true);
839 }
840
841 MCAsmBackend *llvm::createThumbbeAsmBackend(const Target &T,
842 const MCRegisterInfo &MRI,
843 StringRef TT, StringRef CPU) {
844 return createARMAsmBackend(T, MRI, TT, CPU, false);
845 }
846
298298 }
299299
300300 MCObjectWriter *llvm::createARMELFObjectWriter(raw_ostream &OS,
301 uint8_t OSABI) {
301 uint8_t OSABI,
302 bool IsLittleEndian) {
302303 MCELFObjectTargetWriter *MOTW = new ARMELFObjectWriter(OSABI);
303 return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true);
304 }
304 return createELFObjectWriter(MOTW, OS, IsLittleEndian);
305 }
1212
1313 #include "ARMMCAsmInfo.h"
1414 #include "llvm/Support/CommandLine.h"
15 #include "llvm/ADT/Triple.h"
1516
1617 using namespace llvm;
1718
1819 void ARMMCAsmInfoDarwin::anchor() { }
1920
20 ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin() {
21 ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(StringRef TT) {
22 Triple TheTriple(TT);
23 if ((TheTriple.getArch() == Triple::armeb) ||
24 (TheTriple.getArch() == Triple::thumbeb))
25 IsLittleEndian = false;
26
2127 Data64bitsDirective = 0;
2228 CommentString = "@";
2329 Code16Directive = ".code\t16";
3440
3541 void ARMELFMCAsmInfo::anchor() { }
3642
37 ARMELFMCAsmInfo::ARMELFMCAsmInfo() {
43 ARMELFMCAsmInfo::ARMELFMCAsmInfo(StringRef TT) {
44 Triple TheTriple(TT);
45 if ((TheTriple.getArch() == Triple::armeb) ||
46 (TheTriple.getArch() == Triple::thumbeb))
47 IsLittleEndian = false;
48
3849 // ".comm align is in bytes but .align is pow-2."
3950 AlignmentIsInBytes = false;
4051
2121 class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
2222 void anchor() override;
2323 public:
24 explicit ARMMCAsmInfoDarwin();
24 explicit ARMMCAsmInfoDarwin(StringRef TT);
2525 };
2626
2727 class ARMELFMCAsmInfo : public MCAsmInfoELF {
2828 void anchor() override;
2929 public:
30 explicit ARMELFMCAsmInfo();
30 explicit ARMELFMCAsmInfo(StringRef TT);
3131
3232 void setUseIntegratedAssembler(bool Value) override;
3333 };
3939 void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
4040 const MCInstrInfo &MCII;
4141 const MCContext &CTX;
42 bool IsLittleEndian;
4243
4344 public:
44 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
45 : MCII(mcii), CTX(ctx) {
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
46 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
4647 }
4748
4849 ~ARMMCCodeEmitter() {}
384385 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
385386 // Output the constant in little endian byte order.
386387 for (unsigned i = 0; i != Size; ++i) {
387 EmitByte(Val & 255, OS);
388 Val >>= 8;
388 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
389 EmitByte((Val >> Shift) & 0xff, OS);
389390 }
390391 }
391392
396397
397398 } // end anonymous namespace
398399
399 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
400 const MCRegisterInfo &MRI,
401 const MCSubtargetInfo &STI,
402 MCContext &Ctx) {
403 return new ARMMCCodeEmitter(MCII, Ctx);
400 MCCodeEmitter *llvm::createARMleMCCodeEmitter(const MCInstrInfo &MCII,
401 const MCRegisterInfo &MRI,
402 const MCSubtargetInfo &STI,
403 MCContext &Ctx) {
404 return new ARMMCCodeEmitter(MCII, Ctx, true);
405 }
406
407 MCCodeEmitter *llvm::createARMbeMCCodeEmitter(const MCInstrInfo &MCII,
408 const MCRegisterInfo &MRI,
409 const MCSubtargetInfo &STI,
410 MCContext &Ctx) {
411 return new ARMMCCodeEmitter(MCII, Ctx, false);
404412 }
405413
406414 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
8888 unsigned Idx = 0;
8989
9090 // FIXME: Enhance Triple helper class to extract ARM version.
91 bool isThumb = triple.getArch() == Triple::thumb;
91 bool isThumb = triple.getArch() == Triple::thumb ||
92 triple.getArch() == Triple::thumbeb;
9293 if (Len >= 5 && TT.substr(0, 4) == "armv")
9394 Idx = 4;
95 else if (Len >= 7 && TT.substr(0, 6) == "armebv")
96 Idx = 6;
9497 else if (Len >= 7 && TT.substr(0, 6) == "thumbv")
9598 Idx = 6;
99 else if (Len >= 9 && TT.substr(0, 8) == "thumbebv")
100 Idx = 8;
96101
97102 bool NoCPU = CPU == "generic" || CPU.empty();
98103 std::string ARMArchFeature;
213218
214219 MCAsmInfo *MAI;
215220 if (TheTriple.isOSBinFormatMachO())
216 MAI = new ARMMCAsmInfoDarwin();
221 MAI = new ARMMCAsmInfoDarwin(TT);
217222 else
218 MAI = new ARMELFMCAsmInfo();
223 MAI = new ARMELFMCAsmInfo(TT);
219224
220225 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
221226 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(0, Reg, 0));
322327 // Force static initialization.
323328 extern "C" void LLVMInitializeARMTargetMC() {
324329 // Register the MC asm info.
325 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
326 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
330 RegisterMCAsmInfoFn X(TheARMleTarget, createARMMCAsmInfo);
331 RegisterMCAsmInfoFn Y(TheARMbeTarget, createARMMCAsmInfo);
332 RegisterMCAsmInfoFn A(TheThumbleTarget, createARMMCAsmInfo);
333 RegisterMCAsmInfoFn B(TheThumbbeTarget, createARMMCAsmInfo);
327334
328335 // Register the MC codegen info.
329 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
330 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
336 TargetRegistry::RegisterMCCodeGenInfo(TheARMleTarget, createARMMCCodeGenInfo);
337 TargetRegistry::RegisterMCCodeGenInfo(TheARMbeTarget, createARMMCCodeGenInfo);
338 TargetRegistry::RegisterMCCodeGenInfo(TheThumbleTarget, createARMMCCodeGenInfo);
339 TargetRegistry::RegisterMCCodeGenInfo(TheThumbbeTarget, createARMMCCodeGenInfo);
331340
332341 // Register the MC instruction info.
333 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
334 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
342 TargetRegistry::RegisterMCInstrInfo(TheARMleTarget, createARMMCInstrInfo);
343 TargetRegistry::RegisterMCInstrInfo(TheARMbeTarget, createARMMCInstrInfo);
344 TargetRegistry::RegisterMCInstrInfo(TheThumbleTarget, createARMMCInstrInfo);
345 TargetRegistry::RegisterMCInstrInfo(TheThumbbeTarget, createARMMCInstrInfo);
335346
336347 // Register the MC register info.
337 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
338 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
348 TargetRegistry::RegisterMCRegInfo(TheARMleTarget, createARMMCRegisterInfo);
349 TargetRegistry::RegisterMCRegInfo(TheARMbeTarget, createARMMCRegisterInfo);
350 TargetRegistry::RegisterMCRegInfo(TheThumbleTarget, createARMMCRegisterInfo);
351 TargetRegistry::RegisterMCRegInfo(TheThumbbeTarget, createARMMCRegisterInfo);
339352
340353 // Register the MC subtarget info.
341 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
354 TargetRegistry::RegisterMCSubtargetInfo(TheARMleTarget,
342355 ARM_MC::createARMMCSubtargetInfo);
343 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
356 TargetRegistry::RegisterMCSubtargetInfo(TheARMbeTarget,
344357 ARM_MC::createARMMCSubtargetInfo);
358 TargetRegistry::RegisterMCSubtargetInfo(TheThumbleTarget,
359 ARM_MC::createARMMCSubtargetInfo);
360 TargetRegistry::RegisterMCSubtargetInfo(TheThumbbeTarget,
361 ARM_MC::createARMMCSubtargetInfo);
345362
346363 // Register the MC instruction analyzer.
347 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
364 TargetRegistry::RegisterMCInstrAnalysis(TheARMleTarget,
348365 createARMMCInstrAnalysis);
349 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
366 TargetRegistry::RegisterMCInstrAnalysis(TheARMbeTarget,
350367 createARMMCInstrAnalysis);
368 TargetRegistry::RegisterMCInstrAnalysis(TheThumbleTarget,
369 createARMMCInstrAnalysis);
370 TargetRegistry::RegisterMCInstrAnalysis(TheThumbbeTarget,
371 createARMMCInstrAnalysis);
351372
352373 // Register the MC Code Emitter
353 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
354 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
374 TargetRegistry::RegisterMCCodeEmitter(TheARMleTarget,
375 createARMleMCCodeEmitter);
376 TargetRegistry::RegisterMCCodeEmitter(TheARMbeTarget,
377 createARMbeMCCodeEmitter);
378 TargetRegistry::RegisterMCCodeEmitter(TheThumbleTarget,
379 createARMleMCCodeEmitter);
380 TargetRegistry::RegisterMCCodeEmitter(TheThumbbeTarget,
381 createARMbeMCCodeEmitter);
355382
356383 // Register the asm backend.
357 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
358 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
384 TargetRegistry::RegisterMCAsmBackend(TheARMleTarget, createARMleAsmBackend);
385 TargetRegistry::RegisterMCAsmBackend(TheARMbeTarget, createARMbeAsmBackend);
386 TargetRegistry::RegisterMCAsmBackend(TheThumbleTarget,
387 createThumbleAsmBackend);
388 TargetRegistry::RegisterMCAsmBackend(TheThumbbeTarget,
389 createThumbbeAsmBackend);
359390
360391 // Register the object streamer.
361 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
362 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
392 TargetRegistry::RegisterMCObjectStreamer(TheARMleTarget, createMCStreamer);
393 TargetRegistry::RegisterMCObjectStreamer(TheARMbeTarget, createMCStreamer);
394 TargetRegistry::RegisterMCObjectStreamer(TheThumbleTarget, createMCStreamer);
395 TargetRegistry::RegisterMCObjectStreamer(TheThumbbeTarget, createMCStreamer);
363396
364397 // Register the asm streamer.
365 TargetRegistry::RegisterAsmStreamer(TheARMTarget, createMCAsmStreamer);
366 TargetRegistry::RegisterAsmStreamer(TheThumbTarget, createMCAsmStreamer);
398 TargetRegistry::RegisterAsmStreamer(TheARMleTarget, createMCAsmStreamer);
399 TargetRegistry::RegisterAsmStreamer(TheARMbeTarget, createMCAsmStreamer);
400 TargetRegistry::RegisterAsmStreamer(TheThumbleTarget, createMCAsmStreamer);
401 TargetRegistry::RegisterAsmStreamer(TheThumbbeTarget, createMCAsmStreamer);
367402
368403 // Register the MCInstPrinter.
369 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
370 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
404 TargetRegistry::RegisterMCInstPrinter(TheARMleTarget, createARMMCInstPrinter);
405 TargetRegistry::RegisterMCInstPrinter(TheARMbeTarget, createARMMCInstPrinter);
406 TargetRegistry::RegisterMCInstPrinter(TheThumbleTarget,
407 createARMMCInstPrinter);
408 TargetRegistry::RegisterMCInstPrinter(TheThumbbeTarget,
409 createARMMCInstPrinter);
371410
372411 // Register the MC relocation info.
373 TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
412 TargetRegistry::RegisterMCRelocationInfo(TheARMleTarget,
374413 createARMMCRelocationInfo);
375 TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
414 TargetRegistry::RegisterMCRelocationInfo(TheARMbeTarget,
376415 createARMMCRelocationInfo);
377 }
416 TargetRegistry::RegisterMCRelocationInfo(TheThumbleTarget,
417 createARMMCRelocationInfo);
418 TargetRegistry::RegisterMCRelocationInfo(TheThumbbeTarget,
419 createARMMCRelocationInfo);
420 }
3232 class Target;
3333 class raw_ostream;
3434
35 extern Target TheARMTarget, TheThumbTarget;
35 extern Target TheARMleTarget, TheThumbleTarget;
36 extern Target TheARMbeTarget, TheThumbbeTarget;
3637
3738 namespace ARM_MC {
3839 std::string ParseARMTriple(StringRef TT, StringRef CPU);
5051 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
5152 MCAsmBackend *TAB, bool ShowInst);
5253
53 MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII,
54 const MCRegisterInfo &MRI,
55 const MCSubtargetInfo &STI,
56 MCContext &Ctx);
54 MCCodeEmitter *createARMleMCCodeEmitter(const MCInstrInfo &MCII,
55 const MCRegisterInfo &MRI,
56 const MCSubtargetInfo &STI,
57 MCContext &Ctx);
58
59 MCCodeEmitter *createARMbeMCCodeEmitter(const MCInstrInfo &MCII,
60 const MCRegisterInfo &MRI,
61 const MCSubtargetInfo &STI,
62 MCContext &Ctx);
5763
5864 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
65 StringRef TT, StringRef CPU,
66 bool IsLittleEndian);
67
68 MCAsmBackend *createARMleAsmBackend(const Target &T, const MCRegisterInfo &MRI,
5969 StringRef TT, StringRef CPU);
70
71 MCAsmBackend *createARMbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
72 StringRef TT, StringRef CPU);
73
74 MCAsmBackend *createThumbleAsmBackend(const Target &T, const MCRegisterInfo &MRI,
75 StringRef TT, StringRef CPU);
76
77 MCAsmBackend *createThumbbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
78 StringRef TT, StringRef CPU);
6079
6180 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
6281 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
63 uint8_t OSABI);
82 uint8_t OSABI,
83 bool IsLittleEndian);
6484
6585 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
6686 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
1111 #include "llvm/Support/TargetRegistry.h"
1212 using namespace llvm;
1313
14 Target llvm::TheARMTarget, llvm::TheThumbTarget;
14 Target llvm::TheARMleTarget, llvm::TheARMbeTarget;
15 Target llvm::TheThumbleTarget, llvm::TheThumbbeTarget;
1516
1617 extern "C" void LLVMInitializeARMTargetInfo() {
1718 RegisterTarget
18 X(TheARMTarget, "arm", "ARM");
19 X(TheARMleTarget, "arm", "ARM");
20 RegisterTarget
21 Y(TheARMbeTarget, "armeb", "ARM (big endian)");
1922
2023 RegisterTarget
21 Y(TheThumbTarget, "thumb", "Thumb");
24 A(TheThumbleTarget, "thumb", "Thumb");
25 RegisterTarget
26 B(TheThumbbeTarget, "thumbeb", "Thumb (big endian)");
2227 }
0 @ RUN: llvm-mc -triple armv7-unknown-unknown %s --show-encoding > %t
11 @ RUN: FileCheck < %t %s
2 @ RUN: llvm-mc -triple armebv7-unknown-unknown %s --show-encoding > %t
3 @ RUN: FileCheck --check-prefix=CHECK-BE < %t %s
24
35 bl _printf
46 @ CHECK: bl _printf @ encoding: [A,A,A,0xeb]
57 @ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbl
8 @ CHECK-BE: bl _printf @ encoding: [0xeb,A,A,A]
9 @ CHECK-BE: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbl
610
711 mov r9, :lower16:(_foo)
812 movw r9, :lower16:(_foo)
1014
1115 @ CHECK: movw r9, :lower16:_foo @ encoding: [A,0x90'A',0b0000AAAA,0xe3]
1216 @ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16
17 @ CHECK-BE: movw r9, :lower16:_foo @ encoding: [0xe3,0b0000AAAA,0x90'A',A]
18 @ CHECK-BE: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16
1319 @ CHECK: movw r9, :lower16:_foo @ encoding: [A,0x90'A',0b0000AAAA,0xe3]
1420 @ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16
21 @ CHECK-BE: movw r9, :lower16:_foo @ encoding: [0xe3,0b0000AAAA,0x90'A',A]
22 @ CHECK-BE: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16
1523 @ CHECK: movt r9, :upper16:_foo @ encoding: [A,0x90'A',0b0100AAAA,0xe3]
1624 @ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movt_hi16
25 @ CHECK-BE: movt r9, :upper16:_foo @ encoding: [0xe3,0b0100AAAA,0x90'A',A]
26 @ CHECK-BE: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movt_hi16
1727
1828 mov r2, fred
1929
2030 @ CHECK: movw r2, fred @ encoding: [A,0x20'A',0b0000AAAA,0xe3]
2131 @ CHECK: @ fixup A - offset: 0, value: fred, kind: fixup_arm_movw_lo16
32 @ CHECK-BE: movw r2, fred @ encoding: [0xe3,0b0000AAAA,0x20'A',A]
33 @ CHECK-BE: @ fixup A - offset: 0, value: fred, kind: fixup_arm_movw_lo16
0 @ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s
1 @ RUN: llvm-mc -triple=armebv7-unknown-unknown -mcpu=cortex-a8 -show-encoding < %s | FileCheck --check-prefix=CHECK-BE %s
12 .syntax unified
23 .globl _func
34
134135 @ CHECK: Lback:
135136 @ CHECK: adr r2, Lback @ encoding: [A,0x20'A',0x0f'A',0xe2'A']
136137 @ CHECK: @ fixup A - offset: 0, value: Lback, kind: fixup_arm_adr_pcrel_12
138 @ CHECK-BE: adr r2, Lback @ encoding: [0xe2'A',0x0f'A',0x20'A',A]
139 @ CHECK-BE: @ fixup A - offset: 0, value: Lback, kind: fixup_arm_adr_pcrel_12
137140 @ CHECK: adr r3, Lforward @ encoding: [A,0x30'A',0x0f'A',0xe2'A']
138141 @ CHECK: @ fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12
142 @ CHECK-BE: adr r3, Lforward @ encoding: [0xe2'A',0x0f'A',0x30'A',A]
143 @ CHECK-BE: @ fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12
139144 @ CHECK: Lforward:
140145 @ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2]
141146 @ CHECK: adr r2, #-3 @ encoding: [0x03,0x20,0x4f,0xe2]
309314 beq _baz
310315
311316 @ CHECK: b _bar @ encoding: [A,A,A,0xea]
312 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
317 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
318 @ CHECK-BE: b _bar @ encoding: [0xea,A,A,A]
319 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
313320 @ CHECK: beq _baz @ encoding: [A,A,A,0x0a]
314 @ fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
321 @ CHECK: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
322 @ CHECK-BE: beq _baz @ encoding: [0x0a,A,A,A]
323 @ CHECK-BE: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
315324
316325
317326 @------------------------------------------------------------------------------
419428
420429 @ CHECK: bl _bar @ encoding: [A,A,A,0xeb]
421430 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbl
431 @ CHECK-BE: bl _bar @ encoding: [0xeb,A,A,A]
432 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbl
422433 @ CHECK: bleq _bar @ encoding: [A,A,A,0x0b]
423434 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_condbl
435 @ CHECK-BE: bleq _bar @ encoding: [0x0b,A,A,A]
436 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_condbl
424437 @ CHECK: blx _bar @ encoding: [A,A,A,0xfa]
425 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_blx
438 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_blx
439 @ CHECK-BE: blx _bar @ encoding: [0xfa,A,A,A]
440 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_blx
426441 @ CHECK: blls #28634268 @ encoding: [0x27,0x3b,0x6d,0x9b]
427442 @ CHECK: blx #32424576 @ encoding: [0xa0,0xb0,0x7b,0xfa]
428443 @ CHECK: blx #16212288 @ encoding: [0x50,0xd8,0x3d,0xfa]
33 @---
44 @ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
55 @ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s
6 @ RUN: llvm-mc -triple=thumbebv7-unknown-unknown -show-encoding < %s | FileCheck --check-prefix=CHECK-BE %s
67 .syntax unified
78 .globl _func
89
8990 adr r3, #1020
9091
9192 @ CHECK: adr r2, _baz @ encoding: [A,0xa2]
92 @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
93 @ CHECK: @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
94 @ CHECK-BE: adr r2, _baz @ encoding: [0xa2,A]
95 @ CHECK-BE: @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
9396 @ CHECK: adr r5, #0 @ encoding: [0x00,0xa5]
9497 @ CHECK: adr r2, #4 @ encoding: [0x01,0xa2]
9598 @ CHECK: adr r3, #1020 @ encoding: [0xff,0xa3]
131134 beq #160
132135
133136 @ CHECK: b _baz @ encoding: [A,0xe0'A']
134 @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
137 @ CHECK: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
138 @ CHECK-BE: b _baz @ encoding: [0xe0'A',A]
139 @ CHECK-BE: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
135140 @ CHECK: beq _bar @ encoding: [A,0xd0]
136 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
141 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
142 @ CHECK-BE: beq _bar @ encoding: [0xd0,A]
143 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
137144 @ CHECK: b #1838 @ encoding: [0x97,0xe3]
138145 @ CHECK: b #-420 @ encoding: [0x2e,0xe7]
139146 @ CHECK: beq #-256 @ encoding: [0x80,0xd0]
173180 blx _baz
174181
175182 @ CHECK: bl _bar @ encoding: [A,0xf0'A',A,0xd0'A']
176 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
183 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
184 @ CHECK-BE: bl _bar @ encoding: [0xf0'A',A,0xd0'A',A]
185 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
177186 @ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xc0'A']
178 @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx
187 @ CHECK: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx
188 @ CHECK-BE: blx _baz @ encoding: [0xf0'A',A,0xc0'A',A]
189 @ CHECK-BE: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx
179190
180191
181192 @------------------------------------------------------------------------------
271282 ldr r3, #368
272283
273284 @ CHECK: ldr r1, _foo @ encoding: [A,0x49]
274 @ fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp
285 @ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp
286 @ CHECK-BE: ldr r1, _foo @ encoding: [0x49,A]
287 @ CHECK-BE: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp
275288 @ CHECK: ldr r3, [pc, #604] @ encoding: [0x97,0x4b]
276289 @ CHECK: ldr r3, [pc, #368] @ encoding: [0x5c,0x4b]
277290
0 @ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s
1 @ RUN: llvm-mc -triple=thumbebv7-unknown-unknown -mcpu=cortex-a8 -show-encoding < %s | FileCheck --check-prefix=CHECK-BE %s
12 .syntax unified
23 .globl _func
34
226227 bmi.w #-183396
227228
228229 @ CHECK: b.w _bar @ encoding: [A,0xf0'A',A,0x90'A']
229 @ fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch
230 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch
231 @ CHECK-BE: b.w _bar @ encoding: [0xf0'A',A,0x90'A',A]
232 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch
230233 @ CHECK: beq.w _bar @ encoding: [A,0xf0'A',A,0x80'A']
231 @ fixup A - offset: 0, value: _bar, kind: fixup_t2_condbranch
234 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_condbranch
235 @ CHECK-BE: beq.w _bar @ encoding: [0xf0'A',A,0x80'A',A]
236 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_condbranch
232237 @ CHECK: it eq @ encoding: [0x08,0xbf]
233238 @ CHECK: beq.w _bar @ encoding: [A,0xf0'A',A,0x90'A']
234 @ fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch
239 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch
240 @ CHECK-BE: beq.w _bar @ encoding: [0xf0'A',A,0x90'A',A]
241 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch
235242 @ CHECK: bmi.w #-183396 @ encoding: [0x13,0xf5,0xce,0xa9]
236243
237244
331338 @ CHECK: cbnz r7, #6 @ encoding: [0x1f,0xb9]
332339 @ CHECK: cbnz r7, #12 @ encoding: [0x37,0xb9]
333340 @ CHECK: cbz r6, _bar @ encoding: [0x06'A',0xb1'A']
334 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_cb
341 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_cb
342 @ CHECK-BE: cbz r6, _bar @ encoding: [0xb1'A',0x06'A']
343 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_cb
335344 @ CHECK: cbnz r6, _bar @ encoding: [0x06'A',0xb9'A']
336 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_cb
345 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_cb
346 @ CHECK-BE: cbnz r6, _bar @ encoding: [0xb9'A',0x06'A']
347 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_cb
337348
338349
339350 @------------------------------------------------------------------------------
803814
804815 @ CHECK: ldr.w r5, _foo @ encoding: [0x5f'A',0xf8'A',A,0x50'A']
805816 @ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
817 @ CHECK-BE: ldr.w r5, _foo @ encoding: [0xf8'A',0x5f'A',0x50'A',A]
818 @ CHECK-BE: @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
806819 @ CHECK: ldr.w lr, _strcmp-4 @ encoding: [0x5f'A',0xf8'A',A,0xe0'A']
807820 @ CHECK: @ fixup A - offset: 0, value: _strcmp-4, kind: fixup_t2_ldst_pcrel_12
821 @ CHECK-BE: ldr.w lr, _strcmp-4 @ encoding: [0xf8'A',0x5f'A',0xe0'A',A]
822 @ CHECK-BE: @ fixup A - offset: 0, value: _strcmp-4, kind: fixup_t2_ldst_pcrel_12
808823 @ CHECK: ldr.w sp, _foo @ encoding: [0x5f'A',0xf8'A',A,0xd0'A']
809824 @ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
825 @ CHECK-BE: ldr.w sp, _foo @ encoding: [0xf8'A',0x5f'A',0xd0'A',A]
826 @ CHECK-BE: @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
810827
811828 ldr r7, [pc, #8]
812829 ldr.n r7, [pc, #8]
10261043
10271044 @ CHECK: ldrh.w r5, _bar @ encoding: [0x3f'A',0xf8'A',A,0x50'A']
10281045 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
1046 @ CHECK-BE: ldrh.w r5, _bar @ encoding: [0xf8'A',0x3f'A',0x50'A',A]
1047 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
10291048
10301049
10311050 @------------------------------------------------------------------------------
10951114
10961115 @ CHECK: ldrsb.w r5, _bar @ encoding: [0x1f'A',0xf9'A',A,0x50'A']
10971116 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
1117 @ CHECK-BE: ldrsb.w r5, _bar @ encoding: [0xf9'A',0x1f'A',0x50'A',A]
1118 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
10981119
10991120
11001121 @------------------------------------------------------------------------------
11641185
11651186 @ CHECK: ldrsh.w r5, _bar @ encoding: [0x3f'A',0xf9'A',A,0x50'A']
11661187 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
1188 @ CHECK-BE: ldrsh.w r5, _bar @ encoding: [0xf9'A',0x3f'A',0x50'A',A]
1189 @ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
11671190
11681191 @ TEMPORARILY DISABLED:
11691192 @ ldrsh.w r4, [pc, #1435]