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Fix ppcf128 component access on little-endian systems The PowerPC 128-bit long double data type (ppcf128 in LLVM) is in fact a pair of two doubles, where one is considered the "high" or more-significant part, and the other is considered the "low" or less-significant part. When a ppcf128 value is stored in memory or a register pair, the high part always comes first, i.e. at the lower memory address or in the lower-numbered register, and the low part always comes second. This is true both on big-endian and little-endian PowerPC systems. (Similar to how with a complex number, the real part always comes first and the imaginary part second, no matter the byte order of the system.) This was implemented incorrectly for little-endian systems in LLVM. This commit fixes three related issues: - When printing an immediate ppcf128 constant to assembler output in emitGlobalConstantFP, emit the high part first on both big- and little-endian systems. - When lowering a ppcf128 type to a pair of f64 types in SelectionDAG (which is used e.g. when generating code to load an argument into a register pair), use correct low/high part ordering on little-endian systems. - In a related issue, because lowering ppcf128 into a pair of f64 must operate differently from lowering an int128 into a pair of i64, bitcasts between ppcf128 and int128 must not be optimized away by the DAG combiner on little-endian systems, but must effect a word-swap. Reviewed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212274 91177308-0d34-0410-b5e6-96231b3b80d8 Ulrich Weigand 6 years ago
7 changed file(s) with 183 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
715715 /// reduce runtime.
716716 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
717717
718 /// When splitting a value of the specified type into parts, does the Lo
719 /// or Hi part come first? This usually follows the endianness, except
720 /// for ppcf128, where the Hi part always comes first.
721 bool hasBigEndianPartOrdering(EVT VT) const {
722 return isBigEndian() || VT == MVT::ppcf128;
723 }
724
718725 /// If true, the target has custom DAG combine transformations that it can
719726 /// perform for the specified node.
720727 bool hasTargetDAGCombine(ISD::NodeType NT) const {
18801880
18811881 // PPC's long double has odd notions of endianness compared to how LLVM
18821882 // handles it: p[0] goes first for *big* endian on PPC.
1883 if (AP.TM.getDataLayout()->isBigEndian() != CFP->getType()->isPPC_FP128Ty()) {
1883 if (AP.TM.getDataLayout()->isBigEndian() &&
1884 !CFP->getType()->isPPC_FP128Ty()) {
18841885 int Chunk = API.getNumWords() - 1;
18851886
18861887 if (TrailingBytes)
62096209 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
62106210 // Do not change the width of a volatile load.
62116211 !cast(N0)->isVolatile() &&
6212 // Do not remove the cast if the types differ in endian layout.
6213 TLI.hasBigEndianPartOrdering(N0.getValueType()) ==
6214 TLI.hasBigEndianPartOrdering(VT) &&
62126215 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
62136216 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
62146217 LoadSDNode *LN0 = cast(N0);
5959 case TargetLowering::TypeExpandFloat:
6060 // Convert the expanded pieces of the input.
6161 GetExpandedOp(InOp, Lo, Hi);
62 if (TLI.hasBigEndianPartOrdering(InVT) !=
63 TLI.hasBigEndianPartOrdering(OutVT))
64 std::swap(Lo, Hi);
6265 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
6366 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
6467 return;
6568 case TargetLowering::TypeSplitVector:
6669 GetSplitVector(InOp, Lo, Hi);
67 if (TLI.isBigEndian())
70 if (TLI.hasBigEndianPartOrdering(OutVT))
6871 std::swap(Lo, Hi);
6972 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
7073 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
8184 EVT LoVT, HiVT;
8285 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT);
8386 std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoVT, HiVT);
84 if (TLI.isBigEndian())
87 if (TLI.hasBigEndianPartOrdering(OutVT))
8588 std::swap(Lo, Hi);
8689 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
8790 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
175178 false, false, MinAlign(Alignment, IncrementSize));
176179
177180 // Handle endianness of the load.
178 if (TLI.isBigEndian())
181 if (TLI.hasBigEndianPartOrdering(OutVT))
179182 std::swap(Lo, Hi);
180183 }
181184
244247 SDLoc dl(N);
245248
246249 LoadSDNode *LD = cast(N);
247 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
250 EVT ValueVT = LD->getValueType(0);
251 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
248252 SDValue Chain = LD->getChain();
249253 SDValue Ptr = LD->getBasePtr();
250254 unsigned Alignment = LD->getAlignment();
274278 Hi.getValue(1));
275279
276280 // Handle endianness of the load.
277 if (TLI.isBigEndian())
281 if (TLI.hasBigEndianPartOrdering(ValueVT))
278282 std::swap(Lo, Hi);
279283
280284 // Modified the chain - switch anything that used the old chain to use
294298 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2), 0);
295299
296300 // Handle endianness of the load.
297 if (TLI.isBigEndian())
301 if (TLI.hasBigEndianPartOrdering(OVT))
298302 std::swap(Lo, Hi);
299303
300304 // Modified the chain - switch anything that used the old chain to use
458462 SDLoc dl(N);
459463
460464 StoreSDNode *St = cast(N);
461 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(),
462 St->getValue().getValueType());
465 EVT ValueVT = St->getValue().getValueType();
466 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
463467 SDValue Chain = St->getChain();
464468 SDValue Ptr = St->getBasePtr();
465469 unsigned Alignment = St->getAlignment();
473477 SDValue Lo, Hi;
474478 GetExpandedOp(St->getValue(), Lo, Hi);
475479
476 if (TLI.isBigEndian())
480 if (TLI.hasBigEndianPartOrdering(ValueVT))
477481 std::swap(Lo, Hi);
478482
479483 Lo = DAG.getStore(Chain, dl, Lo, Ptr, St->getPointerInfo(),
168168 SDValue Lo, Hi;
169169 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
170170 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
171 if (TLI.isBigEndian())
171 if (TLI.hasBigEndianPartOrdering(ValueVT))
172172 std::swap(Lo, Hi);
173173 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
174174 } else {
0 ; RUN: llc -mcpu=pwr7 -mattr=+altivec < %s | FileCheck %s
1
2 target datalayout = "e-m:e-i64:64-n32:64"
3 target triple = "powerpc64le-unknown-linux-gnu"
4
5 @g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
6
7 define void @callee(ppc_fp128 %x) {
8 entry:
9 %x.addr = alloca ppc_fp128, align 16
10 store ppc_fp128 %x, ppc_fp128* %x.addr, align 16
11 %0 = load ppc_fp128* %x.addr, align 16
12 store ppc_fp128 %0, ppc_fp128* @g, align 16
13 ret void
14 }
15 ; CHECK: @callee
16 ; CHECK: ld [[REG:[0-9]+]], .LC
17 ; CHECK: stfd 2, 8([[REG]])
18 ; CHECK: stfd 1, 0([[REG]])
19 ; CHECK: blr
20
21 define void @caller() {
22 entry:
23 %0 = load ppc_fp128* @g, align 16
24 call void @test(ppc_fp128 %0)
25 ret void
26 }
27 ; CHECK: @caller
28 ; CHECK: ld [[REG:[0-9]+]], .LC
29 ; CHECK: lfd 2, 8([[REG]])
30 ; CHECK: lfd 1, 0([[REG]])
31 ; CHECK: bl test
32
33 declare void @test(ppc_fp128)
34
35 define void @caller_const() {
36 entry:
37 call void @test(ppc_fp128 0xM3FF00000000000000000000000000000)
38 ret void
39 }
40 ; CHECK: .LCPI[[LC:[0-9]+]]_0:
41 ; CHECK: .long 1065353216
42 ; CHECK: .LCPI[[LC]]_1:
43 ; CHECK: .long 0
44 ; CHECK: @caller_const
45 ; CHECK: addi [[REG0:[0-9]+]], {{[0-9]+}}, .LCPI[[LC]]_0
46 ; CHECK: addi [[REG1:[0-9]+]], {{[0-9]+}}, .LCPI[[LC]]_1
47 ; CHECK: lfs 1, 0([[REG0]])
48 ; CHECK: lfs 2, 0([[REG1]])
49 ; CHECK: bl test
50
51 define ppc_fp128 @result() {
52 entry:
53 %0 = load ppc_fp128* @g, align 16
54 ret ppc_fp128 %0
55 }
56 ; CHECK: @result
57 ; CHECK: ld [[REG:[0-9]+]], .LC
58 ; CHECK: lfd 1, 0([[REG]])
59 ; CHECK: lfd 2, 8([[REG]])
60 ; CHECK: blr
61
62 define void @use_result() {
63 entry:
64 %call = tail call ppc_fp128 @test_result() #3
65 store ppc_fp128 %call, ppc_fp128* @g, align 16
66 ret void
67 }
68 ; CHECK: @use_result
69 ; CHECK: bl test_result
70 ; CHECK: ld [[REG:[0-9]+]], .LC
71 ; CHECK: stfd 2, 8([[REG]])
72 ; CHECK: stfd 1, 0([[REG]])
73 ; CHECK: blr
74
75 declare ppc_fp128 @test_result()
76
77 define void @caller_result() {
78 entry:
79 %call = tail call ppc_fp128 @test_result()
80 tail call void @test(ppc_fp128 %call)
81 ret void
82 }
83 ; CHECK: @caller_result
84 ; CHECK: bl test_result
85 ; CHECK-NEXT: nop
86 ; CHECK-NEXT: bl test
87 ; CHECK-NEXT: nop
88
89 define i128 @convert_from(ppc_fp128 %x) {
90 entry:
91 %0 = bitcast ppc_fp128 %x to i128
92 ret i128 %0
93 }
94 ; CHECK: @convert_from
95 ; CHECK: stfd 1, [[OFF1:.*]](1)
96 ; CHECK: stfd 2, [[OFF2:.*]](1)
97 ; CHECK: ld 3, [[OFF1]](1)
98 ; CHECK: ld 4, [[OFF2]](1)
99 ; CHECK: blr
100
101 define ppc_fp128 @convert_to(i128 %x) {
102 entry:
103 %0 = bitcast i128 %x to ppc_fp128
104 ret ppc_fp128 %0
105 }
106 ; CHECK: @convert_to
107 ; CHECK: std 3, [[OFF1:.*]](1)
108 ; CHECK: std 4, [[OFF2:.*]](1)
109 ; CHECK: lfd 1, [[OFF1]](1)
110 ; CHECK: lfd 2, [[OFF2]](1)
111 ; CHECK: blr
112
113 define ppc_fp128 @convert_to2(i128 %x) {
114 entry:
115 %shl = shl i128 %x, 1
116 %0 = bitcast i128 %shl to ppc_fp128
117 ret ppc_fp128 %0
118 }
119
120 ; CHECK: @convert_to
121 ; CHECK: std 3, [[OFF1:.*]](1)
122 ; CHECK: std 4, [[OFF2:.*]](1)
123 ; CHECK: lfd 1, [[OFF1]](1)
124 ; CHECK: lfd 2, [[OFF2]](1)
125 ; CHECK: blr
126
127 define double @convert_vector(<4 x i32> %x) {
128 entry:
129 %cast = bitcast <4 x i32> %x to ppc_fp128
130 %conv = fptrunc ppc_fp128 %cast to double
131 ret double %conv
132 }
133 ; CHECK: @convert_vector
134 ; CHECK: addi [[REG:[0-9]+]], 1, [[OFF:.*]]
135 ; CHECK: stvx 2, 0, [[REG]]
136 ; CHECK: lfd 1, [[OFF]](1)
137 ; CHECK: blr
138
139 declare void @llvm.va_start(i8*)
140
141 define double @vararg(i32 %a, ...) {
142 entry:
143 %va = alloca i8*, align 8
144 %va1 = bitcast i8** %va to i8*
145 call void @llvm.va_start(i8* %va1)
146 %arg = va_arg i8** %va, ppc_fp128
147 %conv = fptrunc ppc_fp128 %arg to double
148 ret double %conv
149 }
150 ; CHECK: @vararg
151 ; CHECK: lfd 1, 0({{[0-9]+}})
152 ; CHECK: blr
153
1515 ; CHECK-NEXT: .size
1616
1717 ; CHECK: varppc128:
18 ; CHECK-NEXT: .quad 0 # ppc_fp128 -0
19 ; CHECK-NEXT: .quad -9223372036854775808
18 ; For ppc_fp128, the high double always comes first.
19 ; CHECK-NEXT: .quad -9223372036854775808 # ppc_fp128 -0
20 ; CHECK-NEXT: .quad 0
2021 ; CHECK-NEXT: .size
2122
2223 ; CHECK: var80: