llvm.org GIT mirror llvm / 1ee2925
Make LABEL a builtin opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Laskey 13 years ago
31 changed file(s) with 62 addition(s) and 91 deletion(s). Raw diff Collapse all Expand all
265265 /// instruction that is an inline asm.
266266 void printInlineAsm(const MachineInstr *MI) const;
267267
268 /// printLabel - This method prints a local label used by debug and
269 /// exception handling tables.
270 void printLabel(const MachineInstr *MI) const;
271
268272 /// printBasicBlockLabel - This method prints the label for the specified
269273 /// MachineBasicBlock
270274 virtual void printBasicBlockLabel(const MachineBasicBlock *MBB,
435435 // Operand #2n+3: A TargetConstant, indicating if the reg is a use/def
436436 // Operand #last: Optional, an incoming flag.
437437 INLINEASM,
438
439 // LABEL - Represents a label in mid basic block used to track
440 // locations needed for debug and exception handling tables. This node
441 // returns a chain.
442 // Operand #0 : input chain.
443 // Operand #1 : module unique number use to identify the label.
444 LABEL,
438445
439446 // STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
440447 // value, the same type as the pointer type for the system, and an output
501508 // number, then a column then a file id (provided by MachineDebugInfo.) It
502509 // produces a token chain as output.
503510 DEBUG_LOC,
504
505 // DEBUG_LABEL - This node is used to mark a location in the code where a
506 // label should be generated for use by the debug information. It takes a
507 // token chain as input and then a unique id (provided by MachineDebugInfo.)
508 // It produces a token chain as output.
509 DEBUG_LABEL,
510511
511512 // BUILTIN_OP_END - This must be the last enum value in this list.
512513 BUILTIN_OP_END
165165 // Invariant opcodes: All instruction sets have these as their low opcodes.
166166 enum {
167167 PHI = 0,
168 INLINEASM = 1
168 INLINEASM = 1,
169 LABEL = 2
169170 };
170171
171172 unsigned getNumOpcodes() const { return NumOpcodes; }
262263 return get(Opcode).getOperandConstraint(OpNum, Constraint);
263264 }
264265
265 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
266 /// instruction if it has one. This is used by codegen passes that update
267 /// DWARF line number info as they modify the code.
268 virtual unsigned getDWARF_LABELOpcode() const {
269 return 0;
270 }
271
272266 /// Return true if the instruction is a register to register move
273267 /// and leave the source and dest operands in the passed parameters.
274268 virtual bool isMoveInstr(const MachineInstr& MI,
10281028 O << "\n\t" << TAI->getInlineAsmEnd() << "\n";
10291029 }
10301030
1031 /// printLabel - This method prints a local label used by debug and
1032 /// exception handling tables.
1033 void AsmPrinter::printLabel(const MachineInstr *MI) const {
1034 if (AsmVerbose) O << "\n";
1035 O << TAI->getPrivateGlobalPrefix()
1036 << "debug_loc"
1037 << MI->getOperand(0).getImmedValue()
1038 << ":\n";
1039 }
1040
10311041 /// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
10321042 /// instruction, using the specified assembler variant. Targets should
10331043 /// overried this to format as appropriate.
7373 while (!MBB->succ_empty())
7474 MBB->removeSuccessor(MBB->succ_end()-1);
7575
76 // If there is DWARF info to active, check to see if there are any DWARF_LABEL
76 // If there is DWARF info to active, check to see if there are any LABEL
7777 // records in the basic block. If so, unregister them from MachineDebugInfo.
7878 if (MDI && !MBB->empty()) {
79 unsigned DWARF_LABELOpc = TII->getDWARF_LABELOpcode();
80 assert(DWARF_LABELOpc &&
81 "Target supports dwarf but didn't implement getDWARF_LABELOpcode!");
82
8379 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
8480 I != E; ++I) {
85 if ((unsigned)I->getOpcode() == DWARF_LABELOpc) {
81 if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
8682 // The label ID # is always operand #0, an immediate.
8783 MDI->InvalidateLabel(I->getOperand(0).getImm());
8884 }
16481648 // Get target instruction info.
16491649 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
16501650 if (!TII) return false;
1651 // Get target version of the debug label opcode.
1652 unsigned DWARF_LABELOpc = TII->getDWARF_LABELOpcode();
1653 if (!DWARF_LABELOpc) return false;
16541651
16551652 // Track if change is made.
16561653 bool MadeChange = false;
16631660 // Iterate through instructions.
16641661 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) {
16651662 // Is it a debug label.
1666 if ((unsigned)I->getOpcode() == DWARF_LABELOpc) {
1663 if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
16671664 // The label ID # is always operand #0, an immediate.
16681665 unsigned NextLabel = I->getOperand(0).getImm();
16691666
736736 case TargetLowering::Expand: {
737737 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
738738 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
739 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
739 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
740740
741 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
741 if (DebugInfo && (useDEBUG_LOC || useLABEL)) {
742742 const std::string &FName =
743743 cast(Node->getOperand(3))->getValue();
744744 const std::string &DirName =
760760 unsigned Col = cast(ColOp)->getValue();
761761 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
762762 Ops.push_back(DAG.getConstant(ID, MVT::i32));
763 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
763 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
764764 }
765765 } else {
766766 Result = Tmp1; // chain
802802 }
803803 break;
804804
805 case ISD::DEBUG_LABEL:
806 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
807 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
805 case ISD::LABEL:
806 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
807 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
808808 default: assert(0 && "This action is not supported yet!");
809809 case TargetLowering::Legal:
810810 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
451451 assert(0 && "This target-independent node should have been selected!");
452452 case ISD::EntryToken: // fall thru
453453 case ISD::TokenFactor:
454 case ISD::LABEL:
454455 break;
455456 case ISD::CopyToReg: {
456457 unsigned InReg;
26902690 case ISD::UNDEF: return "undef";
26912691 case ISD::MERGE_VALUES: return "mergevalues";
26922692 case ISD::INLINEASM: return "inlineasm";
2693 case ISD::LABEL: return "label";
26932694 case ISD::HANDLENODE: return "handlenode";
26942695 case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
26952696 case ISD::CALL: return "call";
28102811 // Debug info
28112812 case ISD::LOCATION: return "location";
28122813 case ISD::DEBUG_LOC: return "debug_loc";
2813 case ISD::DEBUG_LABEL: return "debug_label";
28142814
28152815 case ISD::CONDCODE:
28162816 switch (cast(this)->get()) {
19791979 DbgRegionStartInst &RSI = cast(I);
19801980 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
19811981 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1982 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
1982 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
19831983 DAG.getConstant(LabelID, MVT::i32)));
19841984 }
19851985
19901990 DbgRegionEndInst &REI = cast(I);
19911991 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
19921992 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1993 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1993 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
19941994 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
19951995 }
19961996
20022002 if (DebugInfo && FSI.getSubprogram() &&
20032003 DebugInfo->Verify(FSI.getSubprogram())) {
20042004 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
2005 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
2005 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
20062006 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
20072007 }
20082008
335335 // If this machine instr is an inline asm, measure it.
336336 if (MI->getOpcode() == ARM::INLINEASM)
337337 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
338 if (MI->getOpcode() == ARM::LABEL)
339 return 0;
338340 assert(0 && "Unknown or unset size field for instr!");
339341 break;
340342 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
146146 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
147147 // FIXME - use subtarget debug flags
148148 if (Subtarget->isTargetDarwin())
149 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
149 setOperationAction(ISD::LABEL, MVT::Other, Expand);
150150
151151 setOperationAction(ISD::RET, MVT::Other, Custom);
152152 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
2727 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
2828 : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
2929 RI(*this, STI) {
30 }
31
32 unsigned ARMInstrInfo::getDWARF_LABELOpcode() const {
33 return ARM::DWARF_LABEL;
3430 }
3531
3632 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
7979 /// This is used for addressing modes.
8080 virtual const TargetRegisterClass *getPointerRegClass() const;
8181
82 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
83 /// instruction if it has one. This is used by codegen passes that update
84 /// DWARF line number info as they modify the code.
85 virtual unsigned getDWARF_LABELOpcode() const;
86
8782 /// Return true if the instruction is a register to register move and
8883 /// leave the source and dest operands in the passed parameters.
8984 ///
511511 PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
512512 ".loc $file, $line, $col",
513513 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
514
515 def DWARF_LABEL :
516 PseudoInst<(ops i32imm:$id),
517 "\nLdebug_loc${id:no_hash}:",
518 [(dwarf_label (i32 imm:$id))]>;
519514
520515 def PICADD : AI1<(ops GPR:$dst, GPR:$a, pclabel:$cp),
521516 "\n$cp:\n\tadd $dst, pc, $a",
108108 // We don't have line number support yet.
109109 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
110110 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
111 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
111 setOperationAction(ISD::LABEL, MVT::Other, Expand);
112112
113113 // Not implemented yet.
114114 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
8787 // We don't have line number support yet.
8888 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
8989 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
90 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
90 setOperationAction(ISD::LABEL, MVT::Other, Expand);
9191
9292 //IA64 has these, but they are not implemented
9393 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
6464 MachineFunction *MF = MI->getParent()->getParent();
6565 const char *AsmStr = MI->getOperand(0).getSymbolName();
6666 return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
67 }
68 case PPC::LABEL: {
69 return 0;
6770 }
6871 default:
6972 return 4; // PowerPC instructions are all 4 bytes
146146 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
147147 // FIXME - use subtarget debug flags
148148 if (!TM.getSubtarget().isDarwin())
149 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
149 setOperationAction(ISD::LABEL, MVT::Other, Expand);
150150
151151 // We want to legalize GlobalAddress and ConstantPool nodes into the
152152 // appropriate instructions to materialize the address.
7676 /// This is used for addressing modes.
7777 virtual const TargetRegisterClass *getPointerRegClass() const;
7878
79 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
80 /// instruction if it has one. This is used by codegen passes that update
81 /// DWARF line number info as they modify the code.
82 virtual unsigned getDWARF_LABELOpcode() const {
83 return PPC::DWARF_LABEL;
84 }
85
8679 // Return true if the instruction is a register to register move and
8780 // leave the source and dest operands in the passed parameters.
8881 //
10141014 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
10151015 (i32 imm:$file))]>;
10161016
1017 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
1018 "\n${:private}debug_loc$id:",
1019 [(dwarf_label (i32 imm:$id))]>;
1020
10211017 //===----------------------------------------------------------------------===//
10221018 // PowerPC Instruction Patterns
10231019 //
821821 if (hasInfo) {
822822 // Mark effective beginning of when frame pointer becomes valid.
823823 FrameLabelId = DebugInfo->NextLabelID();
824 BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(FrameLabelId);
824 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
825825 }
826826
827827 // Adjust stack pointer: r1 += NegFrameSize.
901901
902902 // Mark effective beginning of when frame pointer is ready.
903903 unsigned ReadyLabelId = DebugInfo->NextLabelID();
904 BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(ReadyLabelId);
904 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
905905
906906 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
907907 (IsPPC64 ? PPC::X1 : PPC::R1));
206206 // We don't have line number support yet.
207207 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
208208 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
209 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
209 setOperationAction(ISD::LABEL, MVT::Other, Expand);
210210
211211 // RET must be custom lowered, to meet ABI requirements
212212 setOperationAction(ISD::RET , MVT::Other, Custom);
265265 let AsmString = "";
266266 let Namespace = "TargetInstrInfo";
267267 }
268 def LABEL : Instruction {
269 let OperandList = (ops i32imm:$id);
270 let AsmString = "";
271 let Namespace = "TargetInstrInfo";
272 let hasCtrlDep = 1;
273 }
268274
269275 //===----------------------------------------------------------------------===//
270276 // AsmWriter - This class can be implemented by targets that need to customize
754754 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
755755 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
756756
757 def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
758 def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>;
759
760
761
757
758
629629 assert(0 && "psuedo instructions should be removed before code emission");
630630 case TargetInstrInfo::INLINEASM:
631631 assert(0 && "JIT does not support inline asm!\n");
632 case TargetInstrInfo::LABEL:
633 assert(0 && "JIT does not support meta labels!\n");
632634 case X86::IMPLICIT_USE:
633635 case X86::IMPLICIT_DEF:
634636 case X86::IMPLICIT_DEF_GR8:
234234 if (!Subtarget->isTargetDarwin() &&
235235 !Subtarget->isTargetELF() &&
236236 !Subtarget->isTargetCygMing())
237 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
237 setOperationAction(ISD::LABEL, MVT::Other, Expand);
238238
239239 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
240240 setOperationAction(ISD::VASTART , MVT::Other, Custom);
2424 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
2525 TM(tm), RI(tm, *this) {
2626 }
27
28 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
29 /// instruction if it has one. This is used by codegen passes that update
30 /// DWARF line number info as they modify the code.
31 unsigned X86InstrInfo::getDWARF_LABELOpcode() const {
32 return X86::DWARF_LABEL;
33 }
34
3527
3628 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
3729 unsigned& sourceReg,
236236 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
237237 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
238238
239 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
240 /// instruction if it has one. This is used by codegen passes that update
241 /// DWARF line number info as they modify the code.
242 virtual unsigned getDWARF_LABELOpcode() const;
243
244239 /// convertToThreeAddress - This method must be implemented by targets that
245240 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
246241 /// may be able to convert a two-address instruction into a true
24482448 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
24492449 (i32 imm:$file))]>;
24502450
2451 def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
2452 "\n${:private}debug_loc${id:debug}:",
2453 [(dwarf_label (i32 imm:$id))]>;
2454
24552451 //===----------------------------------------------------------------------===//
24562452 // Non-Instruction Patterns
24572453 //===----------------------------------------------------------------------===//
10251025 if (hasInfo) {
10261026 // Mark effective beginning of when frame pointer becomes valid.
10271027 FrameLabelId = DebugInfo->NextLabelID();
1028 BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(FrameLabelId);
1028 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
10291029 }
10301030
10311031 if (hasFP(MF)) {
10771077
10781078 // Mark effective beginning of when frame pointer is ready.
10791079 unsigned ReadyLabelId = DebugInfo->NextLabelID();
1080 BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(ReadyLabelId);
1080 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
10811081
10821082 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
10831083 MachineLocation FPSrc(MachineLocation::VirtualFP);