llvm.org GIT mirror llvm / 1ecbab2
Make HexagonISelLowering not dependent upon a HexagonTargetMachine, but a normal TargetMachine and remove a few cached uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211821 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 6 years ago
2 changed file(s) with 25 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
462462 SmallVector, 16> RegsToPass;
463463 SmallVector MemOpChains;
464464
465 const HexagonRegisterInfo *QRI = static_cast(
466 DAG.getTarget().getRegisterInfo());
465467 SDValue StackPtr =
466 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(),
467 getPointerTy());
468 DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy());
468469
469470 // Walk the register/memloc assignments, inserting copies/loads.
470471 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
719720 cast(Node->getOperand(i))->getReg();
720721
721722 // Check it to be lr
722 if (Reg == TM.getRegisterInfo()->getRARegister()) {
723 const HexagonRegisterInfo *QRI =
724 static_cast(
725 DAG.getTarget().getRegisterInfo());
726 if (Reg == QRI->getRARegister()) {
723727 FuncInfo->setHasClobberLR(true);
724728 break;
725729 }
811815
812816 // The Sub result contains the new stack start address, so it
813817 // must be placed in the stack pointer register.
814 SDValue CopyChain = DAG.getCopyToReg(Chain, dl,
815 TM.getRegisterInfo()->getStackRegister(),
816 Sub);
818 const HexagonRegisterInfo *QRI = static_cast(
819 DAG.getTarget().getRegisterInfo());
820 SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub);
817821
818822 SDValue Ops[2] = { ArgAdjust, CopyChain };
819823 return DAG.getMergeValues(Ops, dl);
959963
960964 SDValue
961965 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
962 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
966 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
963967 MachineFunction &MF = DAG.getMachineFunction();
964968 MachineFrameInfo *MFI = MF.getFrameInfo();
965969 MFI->setReturnAddressIsTaken(true);
985989
986990 SDValue
987991 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
988 const HexagonRegisterInfo *TRI = TM.getRegisterInfo();
992 const HexagonRegisterInfo *TRI =
993 static_cast(DAG.getTarget().getRegisterInfo());
989994 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
990995 MFI->setFrameAddressIsTaken(true);
991996
10371042 // TargetLowering Implementation
10381043 //===----------------------------------------------------------------------===//
10391044
1040 HexagonTargetLowering::HexagonTargetLowering(
1041 HexagonTargetMachine &targetmachine)
1045 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
10421046 : TargetLowering(targetmachine, new HexagonTargetObjectFile()),
10431047 TM(targetmachine) {
10441048
1045 const HexagonRegisterInfo *QRI = TM.getRegisterInfo();
1049 const HexagonSubtarget &Subtarget = TM.getSubtarget();
10461050
10471051 // Set up the register classes.
10481052 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
10491053 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
10501054
1051 if (QRI->Subtarget.hasV5TOps()) {
1055 if (Subtarget.hasV5TOps()) {
10521056 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
10531057 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
10541058 }
11101114 setOperationAction(ISD::FSIN, MVT::f32, Expand);
11111115 setOperationAction(ISD::FSIN, MVT::f64, Expand);
11121116
1113 if (QRI->Subtarget.hasV5TOps()) {
1117 if (Subtarget.hasV5TOps()) {
11141118 // Hexagon V5 Support.
11151119 setOperationAction(ISD::FADD, MVT::f32, Legal);
11161120 setOperationAction(ISD::FADD, MVT::f64, Legal);
13291333 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
13301334 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
13311335
1332 if (QRI->Subtarget.hasV5TOps()) {
1336 if (Subtarget.hasV5TOps()) {
13331337
13341338 // We need to make the operation type of SELECT node to be Custom,
13351339 // such that we don't go into the infinite loop of
14241428
14251429 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
14261430
1427 if (TM.getSubtargetImpl()->isSubtargetV2()) {
1431 if (Subtarget.isSubtargetV2()) {
14281432 setExceptionPointerRegister(Hexagon::R20);
14291433 setExceptionSelectorRegister(Hexagon::R21);
14301434 } else {
14481452 setMinFunctionAlignment(2);
14491453
14501454 // Needed for DYNAMIC_STACKALLOC expansion.
1451 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister();
1452 setStackPointerRegisterToSaveRestore(StackRegister);
1455 const HexagonRegisterInfo *QRI =
1456 static_cast(TM.getRegisterInfo());
1457 setStackPointerRegisterToSaveRestore(QRI->getStackRegister());
14531458 setSchedulingPreference(Sched::VLIW);
14541459 }
14551460
16171622 /// specified FP immediate natively. If false, the legalizer will
16181623 /// materialize the FP immediate as a load from a constant pool.
16191624 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1620 const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
1621 return QRI->Subtarget.hasV5TOps();
1625 return TM.getSubtarget().hasV5TOps();
16221626 }
16231627
16241628 /// isLegalAddressingMode - Return true if the addressing mode represented by
7373 unsigned& RetSize) const;
7474
7575 public:
76 HexagonTargetMachine &TM;
77 explicit HexagonTargetLowering(HexagonTargetMachine &targetmachine);
76 const TargetMachine &TM;
77 explicit HexagonTargetLowering(const TargetMachine &targetmachine);
7878
7979 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
8080 /// for tail call optimization. Targets which want to do tail call