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ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 8 years ago
2 changed file(s) with 20 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
50235023 // VMOVL : Vector Lengthening Move
50245024 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
50255025 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5026 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5027 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5028 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
50265029
50275030 // Vector Conversions.
50285031
380380 store <4 x float> %b, <4 x float> *%p
381381 ret void
382382 }
383
384 ; Vector any_extends must be selected as either vmovl.u or vmovl.s.
385 ; rdar://10723651
386 define void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp {
387 entry:
388 ;CHECK: any_extend
389 ;CHECK: vmovl
390 %and.i186 = zext <4 x i1> %x to <4 x i32>
391 %add.i185 = sub <4 x i32> %and.i186, %y
392 %sub.i = sub <4 x i32> %add.i185, zeroinitializer
393 %add.i = add <4 x i32> %sub.i, zeroinitializer
394 %vmovn.i = trunc <4 x i32> %add.i to <4 x i16>
395 tail call void @llvm.arm.neon.vst1.v4i16(i8* undef, <4 x i16> %vmovn.i, i32 2)
396 unreachable
397 }
398
399 declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind