llvm.org GIT mirror llvm / 1e80f40
enhance new encoder to support prefixes + RawFrm instructions with no operands. It can now handle define void @test2() nounwind { ret void } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95261 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 10 years ago
3 changed file(s) with 134 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
558558 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
559559 --NumOps;
560560
561 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
561 unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(*Desc);
562562 switch (Desc->TSFlags & X86II::FormMask) {
563563 default:
564564 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
639639 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
640640 // specified machine instruction.
641641 //
642 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
643 return TID->TSFlags >> X86II::OpcodeShift;
642 static unsigned char getBaseOpcodeFor(const TargetInstrDesc &TID) {
643 return TID.TSFlags >> X86II::OpcodeShift;
644644 }
645645 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
646 return getBaseOpcodeFor(&get(Opcode));
646 return getBaseOpcodeFor(get(Opcode));
647647 }
648648
649649 static bool isX86_64NonExtLowByteReg(unsigned reg) {
5353 EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
5454 unsigned Opcode = MI.getOpcode();
5555 const TargetInstrDesc &Desc = TII.get(Opcode);
56
56 unsigned TSFlags = Desc.TSFlags;
57
58 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
59 // in order to provide diffability.
60
5761 // Emit the lock opcode prefix as needed.
58 if (Desc.TSFlags & X86II::LOCK)
62 if (TSFlags & X86II::LOCK)
5963 EmitByte(0xF0, OS);
6064
6165 // Emit segment override opcode prefix as needed.
62 switch (Desc.TSFlags & X86II::SegOvrMask) {
66 switch (TSFlags & X86II::SegOvrMask) {
6367 default: assert(0 && "Invalid segment!");
6468 case 0: break; // No segment override!
6569 case X86II::FS:
7074 break;
7175 }
7276
73
77 // Emit the repeat opcode prefix as needed.
78 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
79 EmitByte(0xF3, OS);
80
81 // Emit the operand size opcode prefix as needed.
82 if (TSFlags & X86II::OpSize)
83 EmitByte(0x66, OS);
84
85 // Emit the address size opcode prefix as needed.
86 if (TSFlags & X86II::AdSize)
87 EmitByte(0x67, OS);
88
89 bool Need0FPrefix = false;
90 switch (TSFlags & X86II::Op0Mask) {
91 default: assert(0 && "Invalid prefix!");
92 case 0: break; // No prefix!
93 case X86II::REP: break; // already handled.
94 case X86II::TB: // Two-byte opcode prefix
95 case X86II::T8: // 0F 38
96 case X86II::TA: // 0F 3A
97 Need0FPrefix = true;
98 break;
99 case X86II::TF: // F2 0F 38
100 EmitByte(0xF2, OS);
101 Need0FPrefix = true;
102 break;
103 case X86II::XS: // F3 0F
104 EmitByte(0xF3, OS);
105 Need0FPrefix = true;
106 break;
107 case X86II::XD: // F2 0F
108 EmitByte(0xF2, OS);
109 Need0FPrefix = true;
110 break;
111 case X86II::D8: EmitByte(0xD8, OS); break;
112 case X86II::D9: EmitByte(0xD9, OS); break;
113 case X86II::DA: EmitByte(0xDA, OS); break;
114 case X86II::DB: EmitByte(0xDB, OS); break;
115 case X86II::DC: EmitByte(0xDC, OS); break;
116 case X86II::DD: EmitByte(0xDD, OS); break;
117 case X86II::DE: EmitByte(0xDE, OS); break;
118 case X86II::DF: EmitByte(0xDF, OS); break;
119 }
120
121 // Handle REX prefix.
122 #if 0 // FIXME: Add in, also, can this come before F2 etc to simplify emission?
123 if (Is64BitMode) {
124 if (unsigned REX = X86InstrInfo::determineREX(MI))
125 EmitByte(0x40 | REX, OS);
126 }
127 #endif
128
129 // 0x0F escape code must be emitted just before the opcode.
130 if (Need0FPrefix)
131 EmitByte(0x0F, OS);
132
133 // FIXME: Pull this up into previous switch if REX can be moved earlier.
134 switch (TSFlags & X86II::Op0Mask) {
135 case X86II::TF: // F2 0F 38
136 case X86II::T8: // 0F 38
137 EmitByte(0x38, OS);
138 break;
139 case X86II::TA: // 0F 3A
140 EmitByte(0x3A, OS);
141 break;
142 }
143
144 // If this is a two-address instruction, skip one of the register operands.
145 unsigned NumOps = Desc.getNumOperands();
146 unsigned CurOp = 0;
147 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
148 ++CurOp;
149 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
150 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
151 --NumOps;
152
153 unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(Desc);
154 switch (TSFlags & X86II::FormMask) {
155 default: assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
156 case X86II::RawFrm: {
157 EmitByte(BaseOpcode, OS);
158
159 if (CurOp == NumOps)
160 break;
161
162 assert(0 && "Unimpl");
163 #if 0
164 const MachineOperand &MO = MI.getOperand(CurOp++);
165
166 DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n");
167 DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n");
168 DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n");
169 DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n");
170 DEBUG(dbgs() << "isImm " << MO.isImm() << "\n");
171
172 if (MO.isMBB()) {
173 emitPCRelativeBlockAddress(MO.getMBB());
174 break;
175 }
176
177 if (MO.isGlobal()) {
178 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
179 MO.getOffset(), 0);
180 break;
181 }
182
183 if (MO.isSymbol()) {
184 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
185 break;
186 }
187
188 assert(MO.isImm() && "Unknown RawFrm operand!");
189 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
190 // Fix up immediate operand for pc relative calls.
191 intptr_t Imm = (intptr_t)MO.getImm();
192 Imm = Imm - MCE.getCurrentPCValue() - 4;
193 emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
194 } else
195 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
196 break;
197 #endif
198 }
199 }
74200 }