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[RISCV] Add RISCVInstPrinter and basic MC assembler tests With the addition of RISCVInstPrinter, it is now possible to test the basic operation of the RISCV MC layer. Differential Revision: https://reviews.llvm.org/D23564 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310917 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 2 years ago
11 changed file(s) with 237 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
33 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
44 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
55 tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
6 tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
67
78 add_public_tablegen_target(RISCVCommonTableGen)
89
1112 )
1213
1314 add_subdirectory(AsmParser)
15 add_subdirectory(InstPrinter)
16 add_subdirectory(MCTargetDesc)
1417 add_subdirectory(TargetInfo)
15 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMRISCVAsmPrinter
1 RISCVInstPrinter.cpp
2 )
0 ;===- ./lib/Target/RISCV/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===;
1 ;
2 ; The LLVM Compiler Infrastructure
3 ;
4 ; This file is distributed under the University of Illinois Open Source
5 ; License. See LICENSE.TXT for details.
6 ;
7 ;===------------------------------------------------------------------------===;
8 ;
9 ; This is an LLVMBuild description file for the components in this subdirectory.
10 ;
11 ; For more information on the LLVMBuild system, please see:
12 ;
13 ; http://llvm.org/docs/LLVMBuild.html
14 ;
15 ;===------------------------------------------------------------------------===;
16
17 [component_0]
18 type = Library
19 name = RISCVAsmPrinter
20 parent = RISCV
21 required_libraries = MC Support
22 add_to_library_groups = RISCV
0 //===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an RISCV MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "RISCVInstPrinter.h"
14 #include "llvm/MC/MCAsmInfo.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCSymbol.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Support/FormattedStream.h"
20 using namespace llvm;
21
22 #define DEBUG_TYPE "asm-printer"
23
24 // Include the auto-generated portion of the assembly writer.
25 #include "RISCVGenAsmWriter.inc"
26
27 void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
28 StringRef Annot, const MCSubtargetInfo &STI) {
29 printInstruction(MI, O);
30 printAnnotation(O, Annot);
31 }
32
33 void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
34 O << getRegisterName(RegNo);
35 }
36
37 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
38 raw_ostream &O, const char *Modifier) {
39 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
40 const MCOperand &MO = MI->getOperand(OpNo);
41
42 if (MO.isReg()) {
43 printRegName(O, MO.getReg());
44 return;
45 }
46
47 if (MO.isImm()) {
48 O << MO.getImm();
49 return;
50 }
51
52 assert(MO.isExpr() && "Unknown operand kind in printOperand");
53 MO.getExpr()->print(O, &MAI);
54 }
0 //===-- RISCVInstPrinter.h - Convert RISCV MCInst to asm syntax ---*- C++ -*--//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints a RISCV MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_RISCV_INSTPRINTER_RISCVINSTPRINTER_H
14 #define LLVM_LIB_TARGET_RISCV_INSTPRINTER_RISCVINSTPRINTER_H
15
16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
17 #include "llvm/MC/MCInstPrinter.h"
18
19 namespace llvm {
20 class MCOperand;
21
22 class RISCVInstPrinter : public MCInstPrinter {
23 public:
24 RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
25 const MCRegisterInfo &MRI)
26 : MCInstPrinter(MAI, MII, MRI) {}
27
28 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
29 const MCSubtargetInfo &STI) override;
30 void printRegName(raw_ostream &O, unsigned RegNo) const override;
31
32 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
33 const char *Modifier = nullptr);
34
35 // Autogenerated by tblgen.
36 void printInstruction(const MCInst *MI, raw_ostream &O);
37 static const char *getRegisterName(unsigned RegNo,
38 unsigned AltIdx = RISCV::ABIRegAltName);
39 };
40 }
41
42 #endif
1515 ;===------------------------------------------------------------------------===;
1616
1717 [common]
18 subdirectories = AsmParser TargetInfo MCTargetDesc
18 subdirectories = AsmParser InstPrinter TargetInfo MCTargetDesc
1919
2020 [component_0]
2121 type = TargetGroup
2222 name = RISCV
2323 parent = Target
2424 has_asmparser = 1
25 has_asmprinter = 1
2526
2627 [component_1]
2728 type = Library
2829 name = RISCVCodeGen
2930 parent = RISCV
30 required_libraries = Core CodeGen RISCVInfo Support Target
31 required_libraries = AsmPrinter Core CodeGen MC RISCVAsmPrinter RISCVDesc RISCVInfo Support Target
3132 add_to_library_groups = RISCV
1818 type = Library
1919 name = RISCVDesc
2020 parent = RISCV
21 required_libraries = MC RISCVInfo Support
21 required_libraries = MC RISCVAsmPrinter RISCVInfo Support
2222 add_to_library_groups = RISCV
1212
1313 #include "RISCVMCTargetDesc.h"
1414 #include "RISCVMCAsmInfo.h"
15 #include "InstPrinter/RISCVInstPrinter.h"
1516 #include "llvm/ADT/STLExtras.h"
1617 #include "llvm/MC/MCAsmInfo.h"
1718 #include "llvm/MC/MCInstrInfo.h"
4647 return new RISCVMCAsmInfo(TT);
4748 }
4849
50 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
51 unsigned SyntaxVariant,
52 const MCAsmInfo &MAI,
53 const MCInstrInfo &MII,
54 const MCRegisterInfo &MRI) {
55 return new RISCVInstPrinter(MAI, MII, MRI);
56 }
57
4958 extern "C" void LLVMInitializeRISCVTargetMC() {
5059 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
5160 TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
5362 TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
5463 TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
5564 TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
65 TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
5666 }
5767 }
0 if not 'RISCV' in config.root.targets:
1 config.unsupported = True
2
0 # RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
1
2 # Out of range immediates
3 ori a0, a1, -2049 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-2048, 2047]
4 andi ra, sp, 2048 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [-2048, 2047]
5
6 # Invalid mnemonics
7 subs t0, t2, t1 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
8 nandi t0, zero, 0 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
9
10 # Invalid register names
11 addi foo, sp, 10 # CHECK: :[[@LINE]]:6: error: unknown operand
12 slti a10, a2, 0x20 # CHECK: :[[@LINE]]:6: error: unknown operand
13 slt x32, s0, s0 # CHECK: :[[@LINE]]:5: error: unknown operand
14
15 # RV64I mnemonics
16 addiw a0, sp, 100 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
17 sraw t0, s2, zero # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
18
19 # Invalid operand types
20 xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
21 sub t0, t2, 1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
22
23 # Too many operands
24 add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
25 sltiu s2, s3, 0x50, 0x60 # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
26
27 # Too few operands
28 ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
29 xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
0 # RUN: llvm-mc %s -triple=riscv32 -show-encoding \
1 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
2 # RUN: llvm-mc %s -triple=riscv64 -show-encoding \
3 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
4
5 # CHECK-INST: addi ra, sp, 2
6 # CHECK: encoding: [0x93,0x00,0x21,0x00]
7 addi ra, sp, 2
8 # CHECK-INST: slti a0, a2, -20
9 # CHECK: encoding: [0x13,0x25,0xc6,0xfe]
10 slti a0, a2, -20
11 # CHECK-INST: sltiu s2, s3, 80
12 # CHECK: encoding: [0x13,0xb9,0x09,0x05]
13 sltiu s2, s3, 0x50
14 # CHECK-INST: xori tp, t1, -99
15 # CHECK: encoding: [0x13,0x42,0xd3,0xf9]
16 xori tp, t1, -99
17 # CHECK-INST: ori a0, a1, -2048
18 # CHECK: encoding: [0x13,0xe5,0x05,0x80]
19 ori a0, a1, -2048
20 # CHECK-INST: andi ra, sp, 2047
21 # CHECK: encoding: [0x93,0x70,0xf1,0x7f]
22 andi ra, sp, 2047
23 # CHECK-INST: andi ra, sp, 2047
24 # CHECK: encoding: [0x93,0x70,0xf1,0x7f]
25 andi x1, x2, 2047
26
27 # CHECK-INST: add ra, zero, zero
28 # CHECK: encoding: [0xb3,0x00,0x00,0x00]
29 add ra, zero, zero
30 # CHECK-INST: add ra, zero, zero
31 # CHECK: encoding: [0xb3,0x00,0x00,0x00]
32 add x1, x0, x0
33 # CHECK-INST: sub t0, t2, t1
34 # CHECK: encoding: [0xb3,0x82,0x63,0x40]
35 sub t0, t2, t1
36 # CHECK-INST: sll a5, a4, a3
37 # CHECK: encoding: [0xb3,0x17,0xd7,0x00]
38 sll a5, a4, a3
39 # CHECK-INST: slt s0, s0, s0
40 # CHECK: encoding: [0x33,0x24,0x84,0x00]
41 slt s0, s0, s0
42 # CHECK-INST: sltu gp, a0, a1
43 # CHECK: encoding: [0xb3,0x31,0xb5,0x00]
44 sltu gp, a0, a1
45 # CHECK-INST: xor s2, s2, s8
46 # CHECK: encoding: [0x33,0x49,0x89,0x01]
47 xor s2, s2, s8
48 # CHECK-INST: xor s2, s2, s8
49 # CHECK: encoding: [0x33,0x49,0x89,0x01]
50 xor x18, x18, x24
51 # CHECK-INST: srl a0, s0, t0
52 # CHECK: encoding: [0x33,0x55,0x54,0x00]
53 srl a0, s0, t0
54 # CHECK-INST: sra t0, s2, zero
55 # CHECK: encoding: [0xb3,0x52,0x09,0x40]
56 sra t0, s2, zero
57 # CHECK-INST: or s10, t1, ra
58 # CHECK: encoding: [0x33,0x6d,0x13,0x00]
59 or s10, t1, ra
60 # CHECK-INST: and a0, s2, s3
61 # CHECK: encoding: [0x33,0x75,0x39,0x01]
62 and a0, s2, s3