llvm.org GIT mirror llvm / 1d7e818
Teach BasicAA about arm.neon.vld1 and vst1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130327 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 9 years ago
2 changed file(s) with 36 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
778778 return NoModRef;
779779 break;
780780 }
781 case Intrinsic::arm_neon_vld1: {
782 // LLVM's vld1 and vst1 intrinsics currently only support a single
783 // vector register.
784 uint64_t Size =
785 TD ? TD->getTypeStoreSize(II->getType()) : UnknownSize;
786 if (isNoAlias(Location(II->getArgOperand(0), Size,
787 II->getMetadata(LLVMContext::MD_tbaa)),
788 Loc))
789 return NoModRef;
790 break;
791 }
792 case Intrinsic::arm_neon_vst1: {
793 uint64_t Size =
794 TD ? TD->getTypeStoreSize(II->getArgOperand(1)->getType()) : UnknownSize;
795 if (isNoAlias(Location(II->getArgOperand(0), Size,
796 II->getMetadata(LLVMContext::MD_tbaa)),
797 Loc))
798 return NoModRef;
799 break;
800 }
781801 }
782802
783803 // The AliasAnalysis base class has some smarts, lets use them.
1818 ret <8 x i16> %c
1919 }
2020
21 ; CHECK: define <8 x i16> @test1(i8* %p, <8 x i16> %y) {
22 ; CHECK-NEXT: entry:
23 ; CHECK-NEXT: %q = getelementptr i8* %p, i64 16
24 ; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
25 ; CHECK-NEXT: call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16)
26 ; CHECK-NEXT: %c = add <8 x i16> %a, %a
27 define <8 x i16> @test1(i8* %p, <8 x i16> %y) {
28 entry:
29 %q = getelementptr i8* %p, i64 16
30 %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
31 call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16)
32 %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
33 %c = add <8 x i16> %a, %b
34 ret <8 x i16> %c
35 }
36
2137 declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly
2238 declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind