llvm.org GIT mirror llvm / 1ce666d
Demote vectors to arrays. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229861 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 5 years ago
9 changed file(s) with 79 addition(s) and 153 deletion(s). Raw diff Collapse all Expand all
606606 if (Glue.getNode())
607607 Ops.push_back(Glue);
608608
609 // Compute return values
610 SmallVector ValueVTs;
611 ValueVTs.push_back(MVT::Other);
612 ValueVTs.push_back(MVT::Glue); // provide a glue output since we consume one
613 // as input. This allows someone else to chain
614 // off us as needed.
615 SDVTList NodeTys = DAG.getVTList(ValueVTs);
609 // Compute return values. Provide a glue output since we consume one as
610 // input. This allows someone else to chain off us as needed.
611 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
616612
617613 SDNode *StatepointMCNode = DAG.getMachineNode(TargetOpcode::STATEPOINT,
618614 getCurSDLoc(), NodeTys, Ops);
15271527 bool Stream::failed() { return scanner->failed(); }
15281528
15291529 void Stream::printError(Node *N, const Twine &Msg) {
1530 SmallVector Ranges;
1531 Ranges.push_back(N->getSourceRange());
15321530 scanner->printError( N->getSourceRange().Start
15331531 , SourceMgr::DK_Error
15341532 , Msg
1535 , Ranges);
1533 , N->getSourceRange());
15361534 }
15371535
15381536 document_iterator Stream::begin() {
131131
132132 /// Generic helper for the createDTuple/createQTuple
133133 /// functions. Those should almost always be called instead.
134 SDValue createTuple(ArrayRef Vecs, unsigned RegClassIDs[],
135 unsigned SubRegs[]);
134 SDValue createTuple(ArrayRef Vecs, const unsigned RegClassIDs[],
135 const unsigned SubRegs[]);
136136
137137 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
138138
887887 }
888888
889889 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef Regs) {
890 static unsigned RegClassIDs[] = {
890 static const unsigned RegClassIDs[] = {
891891 AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID};
892 static unsigned SubRegs[] = { AArch64::dsub0, AArch64::dsub1,
893 AArch64::dsub2, AArch64::dsub3 };
892 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1,
893 AArch64::dsub2, AArch64::dsub3};
894894
895895 return createTuple(Regs, RegClassIDs, SubRegs);
896896 }
897897
898898 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef Regs) {
899 static unsigned RegClassIDs[] = {
899 static const unsigned RegClassIDs[] = {
900900 AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
901 static unsigned SubRegs[] = { AArch64::qsub0, AArch64::qsub1,
902 AArch64::qsub2, AArch64::qsub3 };
901 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1,
902 AArch64::qsub2, AArch64::qsub3};
903903
904904 return createTuple(Regs, RegClassIDs, SubRegs);
905905 }
906906
907907 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef Regs,
908 unsigned RegClassIDs[],
909 unsigned SubRegs[]) {
908 const unsigned RegClassIDs[],
909 const unsigned SubRegs[]) {
910910 // There's no special register-class for a vector-list of 1 element: it's just
911911 // a vector.
912912 if (Regs.size() == 1)
10511051 EVT VT = N->getValueType(0);
10521052 SDValue Chain = N->getOperand(0);
10531053
1054 SmallVector Ops;
1055 Ops.push_back(N->getOperand(2)); // Mem operand;
1056 Ops.push_back(Chain);
1057
1058 std::vector ResTys;
1059 ResTys.push_back(MVT::Untyped);
1060 ResTys.push_back(MVT::Other);
1054 SDValue Ops[] = {N->getOperand(2), // Mem operand;
1055 Chain};
1056
1057 EVT ResTys[] = {MVT::Untyped, MVT::Other};
10611058
10621059 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
10631060 SDValue SuperReg = SDValue(Ld, 0);
10751072 EVT VT = N->getValueType(0);
10761073 SDValue Chain = N->getOperand(0);
10771074
1078 SmallVector Ops;
1079 Ops.push_back(N->getOperand(1)); // Mem operand
1080 Ops.push_back(N->getOperand(2)); // Incremental
1081 Ops.push_back(Chain);
1082
1083 std::vector ResTys;
1084 ResTys.push_back(MVT::i64); // Type of the write back register
1085 ResTys.push_back(MVT::Untyped);
1086 ResTys.push_back(MVT::Other);
1075 SDValue Ops[] = {N->getOperand(1), // Mem operand
1076 N->getOperand(2), // Incremental
1077 Chain};
1078
1079 EVT ResTys[] = {MVT::i64, // Type of the write back register
1080 MVT::Untyped, MVT::Other};
10871081
10881082 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
10891083
11141108 SmallVector Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
11151109 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
11161110
1117 SmallVector Ops;
1118 Ops.push_back(RegSeq);
1119 Ops.push_back(N->getOperand(NumVecs + 2));
1120 Ops.push_back(N->getOperand(0));
1111 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
11211112 SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
11221113
11231114 return St;
11271118 unsigned Opc) {
11281119 SDLoc dl(N);
11291120 EVT VT = N->getOperand(2)->getValueType(0);
1130 SmallVector ResTys;
1131 ResTys.push_back(MVT::i64); // Type of the write back register
1132 ResTys.push_back(MVT::Other); // Type for the Chain
1121 EVT ResTys[] = {MVT::i64, // Type of the write back register
1122 MVT::Other}; // Type for the Chain
11331123
11341124 // Form a REG_SEQUENCE to force register allocation.
11351125 bool Is128Bit = VT.getSizeInBits() == 128;
11361126 SmallVector Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
11371127 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
11381128
1139 SmallVector Ops;
1140 Ops.push_back(RegSeq);
1141 Ops.push_back(N->getOperand(NumVecs + 1)); // base register
1142 Ops.push_back(N->getOperand(NumVecs + 2)); // Incremental
1143 Ops.push_back(N->getOperand(0)); // Chain
1129 SDValue Ops[] = {RegSeq,
1130 N->getOperand(NumVecs + 1), // base register
1131 N->getOperand(NumVecs + 2), // Incremental
1132 N->getOperand(0)}; // Chain
11441133 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
11451134
11461135 return St;
11941183
11951184 SDValue RegSeq = createQTuple(Regs);
11961185
1197 std::vector ResTys;
1198 ResTys.push_back(MVT::Untyped);
1199 ResTys.push_back(MVT::Other);
1186 EVT ResTys[] = {MVT::Untyped, MVT::Other};
12001187
12011188 unsigned LaneNo =
12021189 cast(N->getOperand(NumVecs + 2))->getZExtValue();
12031190
1204 SmallVector Ops;
1205 Ops.push_back(RegSeq);
1206 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1207 Ops.push_back(N->getOperand(NumVecs + 3));
1208 Ops.push_back(N->getOperand(0));
1191 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
1192 N->getOperand(NumVecs + 3), N->getOperand(0)};
12091193 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
12101194 SDValue SuperReg = SDValue(Ld, 0);
12111195
12391223
12401224 SDValue RegSeq = createQTuple(Regs);
12411225
1242 std::vector ResTys;
1243 ResTys.push_back(MVT::i64); // Type of the write back register
1244 ResTys.push_back(MVT::Untyped);
1245 ResTys.push_back(MVT::Other);
1226 EVT ResTys[] = {MVT::i64, // Type of the write back register
1227 MVT::Untyped, MVT::Other};
12461228
12471229 unsigned LaneNo =
12481230 cast(N->getOperand(NumVecs + 1))->getZExtValue();
12491231
1250 SmallVector Ops;
1251 Ops.push_back(RegSeq);
1252 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64)); // Lane Number
1253 Ops.push_back(N->getOperand(NumVecs + 2)); // Base register
1254 Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
1255 Ops.push_back(N->getOperand(0));
1232 SDValue Ops[] = {RegSeq,
1233 CurDAG->getTargetConstant(LaneNo, MVT::i64), // Lane Number
1234 N->getOperand(NumVecs + 2), // Base register
1235 N->getOperand(NumVecs + 3), // Incremental
1236 N->getOperand(0)};
12561237 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
12571238
12581239 // Update uses of the write back register
13001281 unsigned LaneNo =
13011282 cast(N->getOperand(NumVecs + 2))->getZExtValue();
13021283
1303 SmallVector Ops;
1304 Ops.push_back(RegSeq);
1305 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1306 Ops.push_back(N->getOperand(NumVecs + 3));
1307 Ops.push_back(N->getOperand(0));
1284 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
1285 N->getOperand(NumVecs + 3), N->getOperand(0)};
13081286 SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
13091287
13101288 // Transfer memoperands.
13301308
13311309 SDValue RegSeq = createQTuple(Regs);
13321310
1333 SmallVector ResTys;
1334 ResTys.push_back(MVT::i64); // Type of the write back register
1335 ResTys.push_back(MVT::Other);
1311 EVT ResTys[] = {MVT::i64, // Type of the write back register
1312 MVT::Other};
13361313
13371314 unsigned LaneNo =
13381315 cast(N->getOperand(NumVecs + 1))->getZExtValue();
13391316
1340 SmallVector Ops;
1341 Ops.push_back(RegSeq);
1342 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1343 Ops.push_back(N->getOperand(NumVecs + 2)); // Base Register
1344 Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
1345 Ops.push_back(N->getOperand(0));
1317 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
1318 N->getOperand(NumVecs + 2), // Base Register
1319 N->getOperand(NumVecs + 3), // Incremental
1320 N->getOperand(0)};
13461321 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
13471322
13481323 // Transfer memoperands.
22472222 SDValue MemAddr = Node->getOperand(4);
22482223
22492224 // Place arguments in the right order.
2250 SmallVector Ops;
2251 Ops.push_back(ValLo);
2252 Ops.push_back(ValHi);
2253 Ops.push_back(MemAddr);
2254 Ops.push_back(Chain);
2225 SDValue Ops[] = {ValLo, ValHi, MemAddr, Chain};
22552226
22562227 SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
22572228 // Transfer memoperands.
978978 } else {
979979 SDValue Zero = DAG.getConstant(0, VT);
980980 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
981 SmallVector Ops;
982 Ops.push_back(One);
983 Ops.push_back(Zero);
984 Ops.push_back(TargetCC);
985 Ops.push_back(Flag);
981 SDValue Ops[] = {One, Zero, TargetCC, Flag};
986982 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
987983 }
988984 }
1000996 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1001997
1002998 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1003 SmallVector Ops;
1004 Ops.push_back(TrueV);
1005 Ops.push_back(FalseV);
1006 Ops.push_back(TargetCC);
1007 Ops.push_back(Flag);
999 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
10081000
10091001 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
10101002 }
14731473 LoadRetVTs.push_back(EltVT);
14741474 LoadRetVTs.push_back(MVT::Other);
14751475 LoadRetVTs.push_back(MVT::Glue);
1476 SmallVector LoadRetOps;
1477 LoadRetOps.push_back(Chain);
1478 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1479 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1480 LoadRetOps.push_back(InFlag);
1476 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
1477 DAG.getConstant(0, MVT::i32), InFlag};
14811478 SDValue retval = DAG.getMemIntrinsicNode(
14821479 NVPTXISD::LoadParam, dl,
14831480 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
15031500 }
15041501 LoadRetVTs.push_back(MVT::Other);
15051502 LoadRetVTs.push_back(MVT::Glue);
1506 SmallVector LoadRetOps;
1507 LoadRetOps.push_back(Chain);
1508 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1509 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1510 LoadRetOps.push_back(InFlag);
1503 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
1504 DAG.getConstant(0, MVT::i32), InFlag};
15111505 SDValue retval = DAG.getMemIntrinsicNode(
15121506 NVPTXISD::LoadParamV2, dl,
15131507 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
15491543 }
15501544 LoadRetVTs.push_back(MVT::Other);
15511545 LoadRetVTs.push_back(MVT::Glue);
1552 SmallVector LoadRetOps;
1553 LoadRetOps.push_back(Chain);
1554 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1555 LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
1556 LoadRetOps.push_back(InFlag);
1546 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
1547 DAG.getConstant(Ofst, MVT::i32), InFlag};
15571548 SDValue retval = DAG.getMemIntrinsicNode(
15581549 Opc, dl, DAG.getVTList(LoadRetVTs),
15591550 LoadRetOps, EltVT, MachinePointerInfo());
16071598 LoadRetVTs.push_back(MVT::Other);
16081599 LoadRetVTs.push_back(MVT::Glue);
16091600
1610 SmallVector LoadRetOps;
1611 LoadRetOps.push_back(Chain);
1612 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1613 LoadRetOps.push_back(DAG.getConstant(Offsets[i], MVT::i32));
1614 LoadRetOps.push_back(InFlag);
1601 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
1602 DAG.getConstant(Offsets[i], MVT::i32), InFlag};
16151603 SDValue retval = DAG.getMemIntrinsicNode(
16161604 NVPTXISD::LoadParam, dl,
16171605 DAG.getVTList(LoadRetVTs), LoadRetOps,
43014289 }
43024290 }
43034291
4304 SmallVector OtherOps;
4305
43064292 // Copy regular operands
4307 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4308 OtherOps.push_back(N->getOperand(i));
4293 SmallVector OtherOps(N->op_begin(), N->op_end());
43094294
43104295 // The select routine does not have access to the LoadSDNode instance, so
43114296 // pass along the extension information
44184403 OtherOps.push_back(Chain); // Chain
44194404 // Skip operand 1 (intrinsic ID)
44204405 // Others
4421 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
4422 OtherOps.push_back(N->getOperand(i));
4406 OtherOps.append(N->op_begin() + 2, N->op_end());
44234407
44244408 MemIntrinsicSDNode *MemSD = cast(N);
44254409
44504434 "Custom handling of non-i8 ldu/ldg?");
44514435
44524436 // Just copy all operands as-is
4453 SmallVector Ops;
4454 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4455 Ops.push_back(N->getOperand(i));
4437 SmallVector Ops(N->op_begin(), N->op_end());
44564438
44574439 // Force output to i16
44584440 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
17791779 }
17801780 }
17811781
1782 SmallVector Ops;
1783 Ops.push_back(TrueOp);
1784 Ops.push_back(FalseOp);
1785 Ops.push_back(DAG.getConstant(C.CCValid, MVT::i32));
1786 Ops.push_back(DAG.getConstant(C.CCMask, MVT::i32));
1787 Ops.push_back(Glue);
1782 SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, MVT::i32),
1783 DAG.getConstant(C.CCMask, MVT::i32), Glue};
17881784
17891785 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
17901786 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
221221
222222 // Now select between End and null, depending on whether the character
223223 // was found.
224 SmallVector Ops;
225 Ops.push_back(End);
226 Ops.push_back(DAG.getConstant(0, PtrVT));
227 Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32));
228 Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32));
229 Ops.push_back(Glue);
224 SDValue Ops[] = {End, DAG.getConstant(0, PtrVT),
225 DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32),
226 DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32), Glue};
230227 VTs = DAG.getVTList(PtrVT, MVT::Glue);
231228 End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
232229 return std::make_pair(End, Chain);
1711417114
1711517115 // Insert VAARG_64 node into the DAG
1711617116 // VAARG_64 returns two values: Variable Argument Address, Chain
17117 SmallVector InstOps;
17118 InstOps.push_back(Chain);
17119 InstOps.push_back(SrcPtr);
17120 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
17121 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
17122 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
17117 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),
17118 DAG.getConstant(ArgMode, MVT::i8),
17119 DAG.getConstant(Align, MVT::i32)};
1712317120 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
1712417121 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
1712517122 VTs, InstOps, MVT::i64,
1803818035 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
1803918036 false, false, false, 0);
1804018037
18041 SmallVector Results;
18042 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
18043 PathThru));
18044 Results.push_back(Chain);
18038 SDValue Results[] = {
18039 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
18040 Chain};
1804518041 return DAG.getMergeValues(Results, dl);
1804618042 }
1804718043 }
25162516 // The weight to CommonDest should be PredCommon * SuccTotal +
25172517 // PredOther * SuccCommon.
25182518 // The weight to OtherDest should be PredOther * SuccOther.
2519 SmallVector NewWeights;
2520 NewWeights.push_back(PredCommon * (SuccCommon + SuccOther) +
2521 PredOther * SuccCommon);
2522 NewWeights.push_back(PredOther * SuccOther);
2519 uint64_t NewWeights[2] = {PredCommon * (SuccCommon + SuccOther) +
2520 PredOther * SuccCommon,
2521 PredOther * SuccOther};
25232522 // Halve the weights if any of them cannot fit in an uint32_t
25242523 FitWeights(NewWeights);
25252524
2526 SmallVector MDWeights(NewWeights.begin(),NewWeights.end());
25272525 PBI->setMetadata(LLVMContext::MD_prof,
2528 MDBuilder(BI->getContext()).
2529 createBranchWeights(MDWeights));
2526 MDBuilder(BI->getContext())
2527 .createBranchWeights(NewWeights[0], NewWeights[1]));
25302528 }
25312529
25322530 // OtherDest may have phi nodes. If so, add an entry from PBI's