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Merging r246675: ------------------------------------------------------------------------ r246675 | hfinkel | 2015-09-02 12:52:37 -0400 (Wed, 02 Sep 2015) | 9 lines [PowerPC] Don't always consider P8Altivec-only masks in LowerVECTOR_SHUFFLE LowerVECTOR_SHUFFLE needs to decide whether to pass a vector shuffle off to the TableGen-generated matching code, and it does this by testing the same predicates used by the TableGen files. Unfortunately, when we added new P8Altivec-only predicates, we started universally testing them in LowerVECTOR_SHUFFLE, and if then matched when targeting a system prior to a P8, we'd end up with a selection failure. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@252479 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
2 changed file(s) with 36 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
71767176 PPC::isSplatShuffleMask(SVOp, 4) ||
71777177 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
71787178 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7179 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
71807179 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
71817180 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
71827181 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
71847183 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
71857184 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
71867185 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7187 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7188 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)) {
7186 (Subtarget.hasP8Altivec() && (
7187 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7188 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7189 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
71897190 return Op;
71907191 }
71917192 }
71967197 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
71977198 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
71987199 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7199 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
72007200 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
72017201 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
72027202 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
72047204 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
72057205 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
72067206 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7207 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7208 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))
7207 (Subtarget.hasP8Altivec() && (
7208 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7209 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7210 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
72097211 return Op;
72107212
72117213 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
0 ; RUN: llc < %s | FileCheck %s
1 target datalayout = "E-m:e-i64:64-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 ; Function Attrs: nounwind
5 define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
6 entry:
7 %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32>
8 ret <2 x i32> %strided.vec
9
10 ; CHECK-LABEL: @test1
11 ; CHECK: vsldoi 2, 2, 2, 12
12 ; CHECK: blr
13 }
14
15 ; Function Attrs: nounwind
16 define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {
17 entry:
18 %strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32>
19 ret <16 x i8> %strided.vec
20
21 ; CHECK-LABEL: @test2
22 ; CHECK: vsldoi 2, 2, 2, 12
23 ; CHECK: blr
24 }
25
26 attributes #0 = { nounwind "target-cpu"="pwr7" }
27