llvm.org GIT mirror llvm / 1cca5e3
Add new TableGen instruction definitions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7537 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 17 years ago
2 changed file(s) with 453 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
1818 // Instruction Descriptions
1919 //===----------------------------------------------------------------------===//
2020
21 include "X86InstrInfo.td"
22
2123 def X86InstrInfo : InstrInfo {
24 set PHIInst = PHI;
25 set NOOPInst = NOOP;
26
27 // Define how we want to layout our TargetSpecific information field... This
28 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
29 set TSFlagsFields = ["FormBits", "isVoid", "hasOpSizePrefix", "Prefix",
30 "TypeBits", "FPFormBits", "printImplicitUses", "Opcode"];
31 set TSFlagsShifts = [ 0, 5, 6, 7,
32 11, 14, 17, 18];
2233 }
2334
2435 def X86 : Target {
0 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
1 //
2 // This file describes the X86 instruction set, defining the instructions, and
3 // properties of the instructions which are needed for code generation, machine
4 // code emission, and analysis.
5 //
6 //===----------------------------------------------------------------------===//
7
8
9
10 // Format specifies the encoding used by the instruction. This is part of the
11 // ad-hoc solution used to emit machine instruction encodings by our machine
12 // code emitter.
13 class Format val> {
14 bits<5> Value = val;
15 }
16
17 def Pseudo : Format<0>; def RawFrm : Format<1>;
18 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
19 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
20 def MRMSrcMem : Format<6>;
21 def MRMS0r : Format<16>; def MRMS1r : Format<17>; def MRMS2r : Format<18>;
22 def MRMS3r : Format<19>; def MRMS4r : Format<20>; def MRMS5r : Format<21>;
23 def MRMS6r : Format<22>; def MRMS7r : Format<23>;
24 def MRMS0m : Format<24>; def MRMS1m : Format<25>; def MRMS2m : Format<26>;
25 def MRMS3m : Format<27>; def MRMS4m : Format<28>; def MRMS5m : Format<29>;
26 def MRMS6m : Format<30>; def MRMS7m : Format<31>;
27
28 // ArgType - This specifies the argument type used by an instruction. This is
29 // part of the ad-hoc solution used to emit machine instruction encodings by our
30 // machine code emitter.
31 class ArgType val> {
32 bits<3> Value = val;
33 }
34 def NoArg : ArgType<0>;
35 def Arg8 : ArgType<1>;
36 def Arg16 : ArgType<2>;
37 def Arg32 : ArgType<3>;
38 def Arg64 : ArgType<4>; // 64 bit int argument for FILD64
39 def ArgF32 : ArgType<5>;
40 def ArgF64 : ArgType<6>;
41 def ArgF80 : ArgType<6>;
42
43 // FPFormat - This specifies what form this FP instruction has. This is used by
44 // the Floating-Point stackifier pass.
45 class FPFormat val> {
46 bits<3> Value = val;
47 }
48 def NotFP : FPFormat<0>;
49 def ZeroArgFP : FPFormat<1>;
50 def OneArgFP : FPFormat<2>;
51 def OneArgFPRW : FPFormat<3>;
52 def TwoArgFP : FPFormat<4>;
53 def SpecialFP : FPFormat<5>;
54
55
56 class X86Inst opcod, Format f, ArgType a> : Instruction {
57 set Namespace = "X86";
58
59 set Name = nam;
60 bits<8> Opcode = opcod;
61 Format Form = f;
62 bits<5> FormBits = Form.Value;
63 ArgType Type = a;
64 bits<3> TypeBits = Type.Value;
65
66 // Attributes specific to X86 instructions...
67 bit isVoid = 0; // Does this inst ignore the return value?
68 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
69 bit printImplicitUses = 0; // Should we print implicit uses of this inst?
70
71 bits<4> Prefix = 0; // Which prefix byte does this inst have?
72 FPFormat FPForm; // What flavor of FP instruction is this?
73 bits<3> FPFormBits = 0;
74 }
75
76 class Imp uses, list defs> {
77 list Uses = uses;
78 list Defs = defs;
79 }
80
81
82 // Prefix byte classes which are used to indicate to the ad-hoc machine code
83 // emitter that various prefix bytes are required.
84 class OpSize { bit hasOpSizePrefix = 1; }
85 class TB { bits<4> Prefix = 1; }
86 class D8 { bits<4> Prefix = 2; }
87 class D9 { bits<4> Prefix = 3; }
88 class DA { bits<4> Prefix = 4; }
89 class DB { bits<4> Prefix = 5; }
90 class DC { bits<4> Prefix = 6; }
91 class DD { bits<4> Prefix = 7; }
92 class DE { bits<4> Prefix = 8; }
93 class DF { bits<4> Prefix = 9; }
94
95
96
97 //===----------------------------------------------------------------------===//
98 // Instruction list...
99 //
100
101 def PHI : X86Inst<"PHI", 0, Pseudo, NoArg>; // PHI node...
102
103 set isVoid = 1 in
104 def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
105
106 def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>;
107 def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>;
108 def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>;
109
110 //===----------------------------------------------------------------------===//
111 // Control Flow Instructions...
112 //
113
114 // Return instruction...
115 set isTerminator = 1, isVoid = 1, isReturn = 1 in
116 def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>;
117
118 // All branches are RawFrm, Void, Branch, and Terminators
119 set isVoid = 1, isBranch = 1, isTerminator = 1 in
120 class IBr opcode> : X86Inst;
121
122 def JMP : IBr<"jmp", 0xE9>;
123 def JB : IBr<"jb" , 0x82>, TB;
124 def JAE : IBr<"jae", 0x83>, TB;
125 def JE : IBr<"je" , 0x84>, TB;
126 def JNE : IBr<"jne", 0x85>, TB;
127 def JBE : IBr<"jbe", 0x86>, TB;
128 def JA : IBr<"ja" , 0x87>, TB;
129 def JL : IBr<"jl" , 0x8C>, TB;
130 def JGE : IBr<"jge", 0x8D>, TB;
131 def JLE : IBr<"jle", 0x8E>, TB;
132 def JG : IBr<"jg" , 0x8F>, TB;
133
134
135 //===----------------------------------------------------------------------===//
136 // Call Instructions...
137 //
138 set isCall = 1, isVoid = 1 in
139 // All calls clobber the non-callee saved registers...
140 set Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
141 def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
142 def CALLr32 : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
143 def CALLm32 : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
144 }
145
146
147 //===----------------------------------------------------------------------===//
148 // Miscellaneous Instructions...
149 //
150 def LEAVE : X86Inst<"leave", 0xC9, RawFrm, NoArg>, Imp<[EBP], [EBP]>;
151
152 set isTwoAddress = 1 in // R32 = bswap R32
153 def BSWAPr32 : X86Inst<"bswap", 0xC8, AddRegFrm, Arg32>, TB;
154
155 def XCHGrr8 : X86Inst<"xchg", 0x86, MRMDestReg, Arg8>; // xchg R8, R8
156 def XCHGrr16 : X86Inst<"xchg", 0x87, MRMDestReg, Arg16>, OpSize;// xchg R16, R16
157 def XCHGrr32 : X86Inst<"xchg", 0x87, MRMDestReg, Arg32>; // xchg R32, R32
158
159 def LEAr16 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg16>, OpSize; // R16 = lea [mem]
160 def LEAr32 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg32>; // R32 = lea [mem]
161
162 //===----------------------------------------------------------------------===//
163 // Move Instructions...
164 //
165 def MOVrr8 : X86Inst<"mov", 0x88, MRMDestReg, Arg8>; // R8 = R8
166 def MOVrr16 : X86Inst<"mov", 0x89, MRMDestReg, Arg16>, OpSize; // R16 = R16
167 def MOVrr32 : X86Inst<"mov", 0x89, MRMDestReg, Arg32>; // R32 = R32
168 def MOVir8 : X86Inst<"mov", 0xB0, AddRegFrm , Arg8>; // R8 = imm8
169 def MOVir16 : X86Inst<"mov", 0xB8, AddRegFrm , Arg16>, OpSize; // R16 = imm16
170 def MOVir32 : X86Inst<"mov", 0xB8, AddRegFrm , Arg32>; // R32 = imm32
171 def MOVim8 : X86Inst<"mov", 0xC6, MRMS0m , Arg8>; // [mem] = imm8
172 def MOVim16 : X86Inst<"mov", 0xC7, MRMS0m , Arg16>, OpSize; // [mem] = imm16
173 def MOVim32 : X86Inst<"mov", 0xC7, MRMS0m , Arg32>; // [mem] = imm32
174
175 def MOVmr8 : X86Inst<"mov", 0x8A, MRMSrcMem , Arg8>; // R8 = [mem]
176 def MOVmr16 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg16>, OpSize; // R16 = [mem]
177 def MOVmr32 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg32>; // R32 = [mem]
178
179 set isVoid = 1 in {
180 def MOVrm8 : X86Inst<"mov", 0x88, MRMDestMem, Arg8>; // R8 = [mem]
181 def MOVrm16 : X86Inst<"mov", 0x89, MRMDestMem, Arg16>, OpSize; // R16 = [mem]
182 def MOVrm32 : X86Inst<"mov", 0x89, MRMDestMem, Arg32>; // R32 = [mem]
183 }
184
185 //===----------------------------------------------------------------------===//
186 // Fixed-Register Multiplication and Division Instructions...
187 //
188 set isVoid = 1 in {
189 // Extra precision multiplication
190 def MULr8 : X86Inst<"mul", 0xF6, MRMS4r, Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*R8
191 def MULr16 : X86Inst<"mul", 0xF7, MRMS4r, Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
192 def MULr32 : X86Inst<"mul", 0xF7, MRMS4r, Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
193
194 // unsigned division/remainder
195 def DIVr8 : X86Inst<"div", 0xF6, MRMS6r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
196 def DIVr16 : X86Inst<"div", 0xF7, MRMS6r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
197 def DIVr32 : X86Inst<"div", 0xF7, MRMS6r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
198
199 // signed division/remainder
200 def IDIVr8 : X86Inst<"idiv",0xF6, MRMS7r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
201 def IDIVr16: X86Inst<"idiv",0xF7, MRMS7r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
202 def IDIVr32: X86Inst<"idiv",0xF7, MRMS7r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
203
204 // Sign-extenders for division
205 def CBW : X86Inst<"cbw", 0x98, RawFrm, Arg8 >, Imp<[AL],[AH]>; // AX = signext(AL)
206 def CWD : X86Inst<"cwd", 0x99, RawFrm, Arg8 >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
207 def CDQ : X86Inst<"cdq", 0x99, RawFrm, Arg8 >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
208 }
209
210
211 //===----------------------------------------------------------------------===//
212 // Two address Instructions...
213 //
214 set isTwoAddress = 1 in { // Define some helper classes to make defs shorter.
215 class I2A8 o, Format F> : X86Inst;
216 class I2A16 o, Format F> : X86Inst;
217 class I2A32 o, Format F> : X86Inst;
218 }
219
220 // Arithmetic...
221 def ADDrr8 : I2A8 <"add", 0x00, MRMDestReg>; // R8 += R8 (set r8 (plus r8 r8))
222 def ADDrr16 : I2A16<"add", 0x01, MRMDestReg>, OpSize; // R16 += R16 (set r16 (plus r16 r16))
223 def ADDrr32 : I2A32<"add", 0x01, MRMDestReg>; // R32 += R32 (set r32 (plus r32 r32))
224 def ADDri8 : I2A8 <"add", 0x80, MRMS0r >; // R8 += imm8 (set r8 (plus r8 imm8))
225 def ADDri16 : I2A16<"add", 0x81, MRMS0r >, OpSize; // R16 += imm16 (set r16 (plus r16 imm16))
226 def ADDri32 : I2A32<"add", 0x81, MRMS0r >; // R32 += imm32 (set r32 (plus r32 imm32))
227
228 def ADCrr32 : I2A32<"adc", 0x11, MRMDestReg>; // R32 += imm32+Carry
229
230 def SUBrr8 : I2A8 <"sub", 0x28, MRMDestReg>; // R8 -= R8
231 def SUBrr16 : I2A16<"sub", 0x29, MRMDestReg>, OpSize; // R16 -= R16
232 def SUBrr32 : I2A32<"sub", 0x29, MRMDestReg>; // R32 -= R32
233 def SUBri8 : I2A8 <"sub", 0x80, MRMS5r >; // R8 -= imm8
234 def SUBri16 : I2A16<"sub", 0x81, MRMS5r >, OpSize; // R16 -= imm16
235 def SUBri32 : I2A32<"sub", 0x81, MRMS5r >; // R32 -= imm32
236
237 def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry
238
239 def IMULr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize; // R16 *= R16
240 def IMULr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB; // R32 *= R32
241
242 // Logical operators...
243 def ANDrr8 : I2A8 <"and", 0x20, MRMDestReg>; // R8 &= R8
244 def ANDrr16 : I2A16<"and", 0x21, MRMDestReg>, OpSize; // R16 &= R16
245 def ANDrr32 : I2A32<"and", 0x21, MRMDestReg>; // R32 &= R32
246 def ANDri8 : I2A8 <"and", 0x80, MRMS4r >; // R8 &= imm8
247 def ANDri16 : I2A16<"and", 0x81, MRMS4r >, OpSize; // R16 &= imm16
248 def ANDri32 : I2A32<"and", 0x81, MRMS4r >; // R32 &= imm32
249
250 def ORrr8 : I2A8 <"or" , 0x08, MRMDestReg>; // R8 |= R8
251 def ORrr16 : I2A16<"or" , 0x09, MRMDestReg>, OpSize; // R16 |= R16
252 def ORrr32 : I2A32<"or" , 0x09, MRMDestReg>; // R32 |= R32
253 def ORri8 : I2A8 <"or" , 0x80, MRMS1r >; // R8 |= imm8
254 def ORri16 : I2A16<"or" , 0x81, MRMS1r >, OpSize; // R16 |= imm16
255 def ORri32 : I2A32<"or" , 0x81, MRMS1r >; // R32 |= imm32
256
257 def XORrr8 : I2A8 <"xor", 0x30, MRMDestReg>; // R8 ^= R8
258 def XORrr16 : I2A16<"xor", 0x31, MRMDestReg>, OpSize; // R16 ^= R16
259 def XORrr32 : I2A32<"xor", 0x31, MRMDestReg>; // R32 ^= R32
260 def XORri8 : I2A8 <"xor", 0x80, MRMS6r >; // R8 ^= imm8
261 def XORri16 : I2A16<"xor", 0x81, MRMS6r >, OpSize; // R16 ^= imm16
262 def XORri32 : I2A32<"xor", 0x81, MRMS6r >; // R32 ^= imm32
263
264 // Test instructions are just like AND, except they don't generate a result.
265 def TESTrr8 : X86Inst<"test", 0x84, MRMDestReg, Arg8 >; // flags = R8 & R8
266 def TESTrr16 : X86Inst<"test", 0x85, MRMDestReg, Arg16>, OpSize; // flags = R16 & R16
267 def TESTrr32 : X86Inst<"test", 0x85, MRMDestReg, Arg32>; // flags = R32 & R32
268 def TESTri8 : X86Inst<"test", 0xF6, MRMS0r , Arg8 >; // flags = R8 & imm8
269 def TESTri16 : X86Inst<"test", 0xF7, MRMS0r , Arg16>, OpSize; // flags = R16 & imm16
270 def TESTri32 : X86Inst<"test", 0xF7, MRMS0r , Arg32>; // flags = R32 & imm32
271
272 // Shift instructions
273 class UsesCL { list Uses = [CL]; bit printImplicitUses = 1; }
274
275 def SHLrr8 : I2A8 <"shl", 0xD2, MRMS4r > , UsesCL; // R8 <<= cl
276 def SHLrr16 : I2A8 <"shl", 0xD3, MRMS4r >, OpSize, UsesCL; // R16 <<= cl
277 def SHLrr32 : I2A8 <"shl", 0xD3, MRMS4r > , UsesCL; // R32 <<= cl
278 def SHLir8 : I2A8 <"shl", 0xC0, MRMS4r >; // R8 <<= imm8
279 def SHLir16 : I2A8 <"shl", 0xC1, MRMS4r >, OpSize; // R16 <<= imm16
280 def SHLir32 : I2A8 <"shl", 0xC1, MRMS4r >; // R32 <<= imm32
281 def SHRrr8 : I2A8 <"shr", 0xD2, MRMS5r > , UsesCL; // R8 >>= cl
282 def SHRrr16 : I2A8 <"shr", 0xD3, MRMS5r >, OpSize, UsesCL; // R16 >>= cl
283 def SHRrr32 : I2A8 <"shr", 0xD3, MRMS5r > , UsesCL; // R32 >>= cl
284 def SHRir8 : I2A8 <"shr", 0xC0, MRMS5r >; // R8 >>= imm8
285 def SHRir16 : I2A8 <"shr", 0xC1, MRMS5r >, OpSize; // R16 >>= imm16
286 def SHRir32 : I2A8 <"shr", 0xC1, MRMS5r >; // R32 >>= imm32
287 def SARrr8 : I2A8 <"sar", 0xD2, MRMS7r > , UsesCL; // R8 >>>= cl
288 def SARrr16 : I2A8 <"sar", 0xD3, MRMS7r >, OpSize, UsesCL; // R16 >>>= cl
289 def SARrr32 : I2A8 <"sar", 0xD3, MRMS7r > , UsesCL; // R32 >>>= cl
290 def SARir8 : I2A8 <"sar", 0xC0, MRMS7r >; // R8 >>>= imm8
291 def SARir16 : I2A8 <"sar", 0xC1, MRMS7r >, OpSize; // R16 >>>= imm16
292 def SARir32 : I2A8 <"sar", 0xC1, MRMS7r >; // R32 >>>= imm32
293
294 def SHLDrr32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
295 def SHLDir32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
296 def SHRDrr32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
297 def SHRDir32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
298
299 // Condition code ops, incl. set if equal/not equal/...
300 def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH
301 def SETBr : X86Inst<"setb" , 0x92, MRMS0r, Arg8>, TB; // R8 = < unsign
302 def SETAEr : X86Inst<"setae", 0x93, MRMS0r, Arg8>, TB; // R8 = >= unsign
303 def SETEr : X86Inst<"sete" , 0x94, MRMS0r, Arg8>, TB; // R8 = ==
304 def SETNEr : X86Inst<"setne", 0x95, MRMS0r, Arg8>, TB; // R8 = !=
305 def SETBEr : X86Inst<"setbe", 0x96, MRMS0r, Arg8>, TB; // R8 = <= unsign
306 def SETAr : X86Inst<"seta" , 0x97, MRMS0r, Arg8>, TB; // R8 = > signed
307 def SETLr : X86Inst<"setl" , 0x9C, MRMS0r, Arg8>, TB; // R8 = < signed
308 def SETGEr : X86Inst<"setge", 0x9D, MRMS0r, Arg8>, TB; // R8 = >= signed
309 def SETLEr : X86Inst<"setle", 0x9E, MRMS0r, Arg8>, TB; // R8 = <= signed
310 def SETGr : X86Inst<"setg" , 0x9F, MRMS0r, Arg8>, TB; // R8 = < signed
311
312 // Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
313 // register allocated to cmovXX XY, Z
314 def CMOVErr16 : I2A16<"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
315 def CMOVNErr32: I2A32<"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
316
317 // Integer comparisons
318 set isVoid = 1 in {
319 def CMPrr8 : X86Inst<"cmp", 0x38, MRMDestReg, Arg8 >; // compare R8, R8
320 def CMPrr16 : X86Inst<"cmp", 0x39, MRMDestReg, Arg16>, OpSize; // compare R16, R16
321 def CMPrr32 : X86Inst<"cmp", 0x39, MRMDestReg, Arg32>; // compare R32, R32
322 def CMPri8 : X86Inst<"cmp", 0x80, MRMS7r , Arg8 >; // compare R8, imm8
323 def CMPri16 : X86Inst<"cmp", 0x81, MRMS7r , Arg16>, OpSize; // compare R16, imm16
324 def CMPri32 : X86Inst<"cmp", 0x81, MRMS7r , Arg32>; // compare R32, imm32
325 }
326
327 // Sign/Zero extenders
328 def MOVSXr16r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB, OpSize; // R16 = signext(R8)
329 def MOVSXr32r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB; // R32 = signext(R8)
330 def MOVSXr32r16: X86Inst<"movsx", 0xBF, MRMSrcReg, Arg8>, TB; // R32 = signext(R16)
331 def MOVZXr16r8 : X86Inst<"movzx", 0xB6, MRMSrcReg, Arg8>, TB, OpSize; // R16 = zeroext(R8)
332 def MOVZXr32r8 : X86Inst<"movzx", 0xB6, MRMSrcReg, Arg8>, TB; // R32 = zeroext(R8)
333 def MOVZXr32r16: X86Inst<"movzx", 0xB7, MRMSrcReg, Arg8>, TB; // R32 = zeroext(R16)
334
335
336 //===----------------------------------------------------------------------===//
337 // Floating point support
338 //===----------------------------------------------------------------------===//
339
340 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
341
342 // Floating point pseudo instructions...
343 class FPInst o, Format F, ArgType t, FPFormat fp>
344 : X86Inst { set FPForm = fp; set FPFormBits = FPForm.Value; }
345
346 def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>; // f1 = fmov f2
347 def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fadd f2, f3
348 def FpSUB : FPInst<"FSUB", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fsub f2, f3
349 def FpMUL : FPInst<"FMUL", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fmul f2, f3
350 def FpDIV : FPInst<"FDIV", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fdiv f2, f3
351
352 set isVoid = 1 in
353 def FpUCOM : FPInst<"FUCOM", 0, Pseudo, ArgF80, TwoArgFP>; // FPSW = fucom f1, f2
354
355 def FpGETRESULT : FPInst<"FGETRESULT",0, Pseudo, ArgF80, SpecialFP>; // FPR = ST(0)
356
357 set isVoid = 1 in
358 def FpSETRESULT : FPInst<"FSETRESULT",0, Pseudo, ArgF80, SpecialFP>; // ST(0) = FPR
359
360 // Floating point loads & stores...
361 def FLDrr : FPInst<"fld" , 0xC0, AddRegFrm, ArgF80, NotFP>, D9; // push(ST(i))
362 def FLDr32 : FPInst<"fld" , 0xD9, MRMS0m , ArgF32, ZeroArgFP>; // load float
363 def FLDr64 : FPInst<"fld" , 0xDD, MRMS0m , ArgF64, ZeroArgFP>; // load double
364 def FLDr80 : FPInst<"fld" , 0xDB, MRMS5m , ArgF80, ZeroArgFP>; // load extended
365 def FILDr16 : FPInst<"fild" , 0xDF, MRMS0m , Arg16 , ZeroArgFP>; // load signed short
366 def FILDr32 : FPInst<"fild" , 0xDB, MRMS0m , Arg32 , ZeroArgFP>; // load signed int
367 def FILDr64 : FPInst<"fild" , 0xDF, MRMS5m , Arg64 , ZeroArgFP>; // load signed long
368
369 set isVoid = 1 in {
370 def FSTr32 : FPInst<"fst" , 0xD9, MRMS2m , ArgF32, OneArgFP>; // store float
371 def FSTr64 : FPInst<"fst" , 0xDD, MRMS2m , ArgF64, OneArgFP>; // store double
372 def FSTPr32 : FPInst<"fstp", 0xD9, MRMS3m , ArgF32, OneArgFP>; // store float, pop
373 def FSTPr64 : FPInst<"fstp", 0xDD, MRMS3m , ArgF64, OneArgFP>; // store double, pop
374 def FSTPr80 : FPInst<"fstp", 0xDB, MRMS7m , ArgF80, OneArgFP>; // store extended, pop
375 def FSTrr : FPInst<"fst" , 0xD0, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0)
376 def FSTPrr : FPInst<"fstp", 0xD8, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0), pop
377
378 def FISTr16 : FPInst<"fist", 0xDF, MRMS2m, Arg16 , OneArgFP>; // store signed short
379 def FISTr32 : FPInst<"fist", 0xDB, MRMS2m, Arg32 , OneArgFP>; // store signed int
380 def FISTPr16 : FPInst<"fistp", 0xDF, MRMS3m, Arg16 , NotFP >; // store signed short, pop
381 def FISTPr32 : FPInst<"fistp", 0xDB, MRMS3m, Arg32 , NotFP >; // store signed int, pop
382 def FISTPr64 : FPInst<"fistpll", 0xDF, MRMS7m, Arg64 , OneArgFP>; // store signed long, pop
383
384 def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fxch ST(i), ST(0)
385 }
386
387 // Floating point constant loads...
388 def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9;
389 def FLD1 : FPInst<"fld1", 0xE8, RawFrm, ArgF80, ZeroArgFP>, D9;
390
391 // Binary arithmetic operations...
392 class FPST0rInst o>
393 : X86Inst, D8 {
394 list Uses = [ST0];
395 list Defs = [ST0];
396 }
397 class FPrST0Inst o>
398 : X86Inst, DC {
399 bit printImplicitUses = 1;
400 list Uses = [ST0];
401 }
402 class FPrST0PInst o>
403 : X86Inst, DE {
404 list Uses = [ST0];
405 }
406
407 def FADDST0r : FPST0rInst <"fadd", 0xC0>;
408 def FADDrST0 : FPrST0Inst <"fadd", 0xC0>;
409 def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
410
411 def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
412 def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>;
413 def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
414
415 def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
416 def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>;
417 def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
418
419 def FMULST0r : FPST0rInst <"fmul", 0xC8>;
420 def FMULrST0 : FPrST0Inst <"fmul", 0xC8>;
421 def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
422
423 def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
424 def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>;
425 def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
426
427 def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
428 def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
429 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
430
431 // Floating point compares
432 set isVoid = 1 in {
433 def FUCOMr : X86Inst<"fucom" , 0xE0, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
434 def FUCOMPr : X86Inst<"fucomp" , 0xE8, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
435 def FUCOMPPr : X86Inst<"fucompp", 0xE9, RawFrm , ArgF80>, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
436
437 // Floating point flag ops
438 def FNSTSWr8 : X86Inst<"fnstsw" , 0xE0, RawFrm , ArgF80>, DF, Imp<[],[AX]>; // AX = fp flags
439 def FNSTCWm16 : X86Inst<"fnstcw" , 0xD9, MRMS7m , Arg16 >; // [mem16] = X87 control world
440 def FLDCWm16 : X86Inst<"fldcw" , 0xD9, MRMS5m , Arg16 >; // X87 control world = [mem16]
441 }