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Test case hygiene. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176772 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 6 years ago
18 changed file(s) with 50 addition(s) and 51 deletion(s). Raw diff Collapse all Expand all
44 define void @foo() {
55 ; CHECK: foo:
66
7 ; CHECK stp d14, d15, [sp
8 ; CHECK stp d12, d13, [sp
9 ; CHECK stp d10, d11, [sp
10 ; CHECK stp d8, d9, [sp
7 ; CHECK: stp d14, d15, [sp
8 ; CHECK: stp d12, d13, [sp
9 ; CHECK: stp d10, d11, [sp
10 ; CHECK: stp d8, d9, [sp
1111
1212 ; Create lots of live variables to exhaust the supply of
1313 ; caller-saved registers
1212
1313 ; Normal frame setup stuff:
1414 ; CHECK: sub sp, sp,
15 ; CHECK stp x29, x30
15 ; CHECK: stp x29, x30
1616
1717 ; Reserve space for call-frame:
1818 ; CHECK: sub sp, sp, #16
3737
3838 %addr = alloca i8, i32 %in
3939 ; Normal frame setup again
40 ; CHECK sub sp, sp,
41 ; CHECK stp x29, x30
40 ; CHECK: sub sp, sp,
41 ; CHECK: stp x29, x30
4242
4343 ; Reserve space for call-frame
44 ; CHECK sub sp, sp, #16
44 ; CHECK: sub sp, sp, #16
4545
4646 call void @wont_pop([8 x i32] undef, i32 42)
47 ; CHECK bl wont_pop
47 ; CHECK: bl wont_pop
4848
4949 ; This time we *do* need to unreserve the call-frame
50 ; CHECK add sp, sp, #16
50 ; CHECK: add sp, sp, #16
5151
5252 ; Check for epilogue (primarily to make sure sp spotted above wasn't
5353 ; part of it).
4343 %val1 = load i64* %addr1
4444 ; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}]
4545 store i64 %val1, i64* @var64
46 ; CHECK str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
46 ; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
4747
4848 ret void
4949 }
6565 %val1 = load i64* %addr1
6666 ; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16]
6767 store i64 %val1, i64* @var64
68 ; CHECK str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
68 ; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
6969
7070 ret void
7171 }
6060
6161 call void @return_large_struct(%myStruct* sret @varstruct)
6262 ; CHECK: add x8, {{x[0-9]+}}, #:lo12:varstruct
63 ; CHECK bl return_large_struct
63 ; CHECK: bl return_large_struct
6464
6565 ret void
6666 }
9292 ; CHECK: ldr s[[STACKEDREG:[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI
9393 ; CHECK: mov x0, sp
9494 ; CHECK: str d[[STACKEDREG]], [x0]
95 ; CHECK bl stacked_fpu
95 ; CHECK: bl stacked_fpu
9696 ret void
9797 }
9898
7474
7575 define void @test11() {
7676 ; CHECK: test11:
77 ; CHECK movz {{w[0-9]+}}, #0
77 ; CHECK: mov {{w[0-9]+}}, wzr
7878 store i32 0, i32* @var32
7979 ret void
8080 }
44
55 define void @test_w29_reserved() {
66 ; CHECK: test_w29_reserved:
7 ; CHECK add x29, sp, #{{[0-9]+}}
7 ; CHECK: add x29, sp, #{{[0-9]+}}
88
99 %val1 = load volatile i32* @var
1010 %val2 = load volatile i32* @var
102102 entry:
103103 ; CHECKT2D: t8:
104104 ; CHECKT2D-NOT: push
105 ; CHECKT2D-NOT
106105 %and = and i32 %x, 1
107106 %tobool = icmp eq i32 %and, 0
108107 br i1 %tobool, label %if.end, label %if.then
1414 declare void @__cxa_call_unexpected(i8*)
1515
1616 define i32 @main() {
17 ; CHECK main:
17 ; CHECK: main:
1818 entry:
1919 %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
2020 %0 = bitcast i8* %exception.i to i32*
102102 ; ARM: t11
103103 %add.ptr = getelementptr inbounds i16* %a, i64 8
104104 store i16 0, i16* %add.ptr, align 2
105 ; ARM strh r{{[1-9]}}, [r0, #16]
105 ; ARM: strh r{{[1-9]}}, [r0, #16]
106106 ret void
107107 }
108108
5555 ret void
5656 }
5757
58 ; CHECK-STATIC16 li ${{[0-9]+}}, %hi($JTI{{[0-9]+}}_{{[0-9]+}})
59 ; CHECK-STATIC16 lw ${{[0-9]+}}, %lo($JTI{{[0-9]+}}_{{[0-9]+}})({{[0-9]+}})
58 ; CHECK-STATIC16: li ${{[0-9]+}}, %hi($JTI{{[0-9]+}}_{{[0-9]+}})
59 ; CHECK-STATIC16: lw ${{[0-9]+}}, %lo($JTI{{[0-9]+}}_{{[0-9]+}})(${{[0-9]+}})
6060 ; CHECK-STATIC16: $JTI{{[0-9]+}}_{{[0-9]+}}:
6161 ; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}})
6262 ; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}})
44
55 ; Check that %add is not passed in an integer register.
66 ;
7 ; HARD : callfloor:
7 ; HARD: callfloor:
88 ; HARD-NOT: dmfc1 $4
99
1010 define double @callfloor(double %d) nounwind readnone {
5353 }
5454 ; CHECK: v16si8_cmp_ne:
5555 ; CHECK: vcmpequb [[RET:[0-9]+]], 2, 3
56 ; CHECK-NOR: vnor 2, [[RET]], [[RET]]
56 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
5757
5858 define <16 x i8> @v16si8_cmp_le(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
5959 entry:
33 ;to a SETNE_INT. There should only be one SETNE_INT instruction.
44
55 ;CHECK: SETNE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ;CHECK_NOT: SETNE_INT
6 ;CHECK-NOT: SETNE_INT
77
88 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
99 entry:
55 ; or
66 ; ADD_INT literal.x REG, 5
77
8 ; CHECK; @i32_literal
8 ; CHECK: @i32_literal
99 ; CHECK: ADD_INT {{[A-Z0-9,. ]*}}literal.x,{{[A-Z0-9,. ]*}} 5
1010 define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
1111 entry:
3737 ; CHECK: test4
3838 define float @test4(float %a) {
3939 ; CHECK-NOT: fma
40 ; CHECK-NOT mul
40 ; CHECK-NOT: mul
4141 ; CHECK-NOT: add
4242 ; CHECK: ret
4343 %t1 = fmul float %a, 0.0
1515 define <4 x i32> @sdiv_zero(<4 x i32> %var) {
1616 entry:
1717 ; CHECK: sdiv_zero
18 ; CHECK-NOT sra
18 ; CHECK-NOT: sra
1919 ; CHECK: ret
2020 %0 = sdiv <4 x i32> %var,
2121 ret <4 x i32> %0
11 ;; check that global opt turns integers that only hold 0 or 1 into bools.
22
33 @G = internal addrspace(1) global i32 0
4 ; CHECK @G.b
5 ; CHECK addrspace(1)
6 ; CHECK global i1 0
4 ; CHECK: @G.b
5 ; CHECK: addrspace(1)
6 ; CHECK: global i1 0
77
88 define void @set1() {
99 store i32 0, i32 addrspace(1)* @G
1818 }
1919
2020 define i1 @get() {
21 ; CHECK @get
21 ; CHECK: @get
2222 %A = load i32 addrspace(1) * @G
2323 %C = icmp slt i32 %A, 2
2424 ret i1 %C
2323 ; }
2424 ; CHECK: define i32 @noAlias01
2525 ; CHECK: add nsw <4 x i32>
26 ; CHECK ret
26 ; CHECK: ret
2727
2828 define i32 @noAlias01(i32 %a) nounwind {
2929 entry:
7171 ; }
7272 ; CHECK: define i32 @noAlias02
7373 ; CHECK: add nsw <4 x i32>
74 ; CHECK ret
74 ; CHECK: ret
7575
7676 define i32 @noAlias02(i32 %a) {
7777 entry:
120120 ; }
121121 ; CHECK: define i32 @noAlias03
122122 ; CHECK: add nsw <4 x i32>
123 ; CHECK ret
123 ; CHECK: ret
124124
125125 define i32 @noAlias03(i32 %a) {
126126 entry:
169169 ; }
170170 ; CHECK: define i32 @noAlias04
171171 ; CHECK-NOT: add nsw <4 x i32>
172 ; CHECK ret
172 ; CHECK: ret
173173 ;
174174 ; TODO: This test vectorizes (with run-time check) on real targets with -O3)
175175 ; Check why it's not being vectorized even when forcing vectorization
223223 ; }
224224 ; CHECK: define i32 @noAlias05
225225 ; CHECK: add nsw <4 x i32>
226 ; CHECK ret
226 ; CHECK: ret
227227
228228 define i32 @noAlias05(i32 %a) #0 {
229229 entry:
279279 ; }
280280 ; CHECK: define i32 @noAlias06
281281 ; CHECK: add nsw <4 x i32>
282 ; CHECK ret
282 ; CHECK: ret
283283
284284 define i32 @noAlias06(i32 %a) #0 {
285285 entry:
336336 ; }
337337 ; CHECK: define i32 @noAlias07
338338 ; CHECK: sub nsw <4 x i32>
339 ; CHECK ret
339 ; CHECK: ret
340340
341341 define i32 @noAlias07(i32 %a) #0 {
342342 entry:
388388 ; }
389389 ; CHECK: define i32 @noAlias08
390390 ; CHECK: sub nsw <4 x i32>
391 ; CHECK ret
391 ; CHECK: ret
392392
393393 define i32 @noAlias08(i32 %a) #0 {
394394 entry:
440440 ; }
441441 ; CHECK: define i32 @noAlias09
442442 ; CHECK: sub nsw <4 x i32>
443 ; CHECK ret
443 ; CHECK: ret
444444
445445 define i32 @noAlias09(i32 %a) #0 {
446446 entry:
492492 ; }
493493 ; CHECK: define i32 @noAlias10
494494 ; CHECK-NOT: sub nsw <4 x i32>
495 ; CHECK ret
495 ; CHECK: ret
496496 ;
497497 ; TODO: This test vectorizes (with run-time check) on real targets with -O3)
498498 ; Check why it's not being vectorized even when forcing vectorization
552552 ; }
553553 ; CHECK: define i32 @noAlias11
554554 ; CHECK: sub nsw <4 x i32>
555 ; CHECK ret
555 ; CHECK: ret
556556
557557 define i32 @noAlias11(i32 %a) #0 {
558558 entry:
612612 ; }
613613 ; CHECK: define i32 @noAlias12
614614 ; CHECK: sub nsw <4 x i32>
615 ; CHECK ret
615 ; CHECK: ret
616616
617617 define i32 @noAlias12(i32 %a) #0 {
618618 entry:
673673 ; }
674674 ; CHECK: define i32 @noAlias13
675675 ; CHECK: add nsw <4 x i32>
676 ; CHECK ret
676 ; CHECK: ret
677677
678678 define i32 @noAlias13(i32 %a) #0 {
679679 entry:
722722 ; }
723723 ; CHECK: define i32 @noAlias14
724724 ; CHECK: sub nsw <4 x i32>
725 ; CHECK ret
725 ; CHECK: ret
726726
727727 define i32 @noAlias14(i32 %a) #0 {
728728 entry:
778778 ; }
779779 ; CHECK: define i32 @mayAlias01
780780 ; CHECK-NOT: add nsw <4 x i32>
781 ; CHECK ret
781 ; CHECK: ret
782782
783783 define i32 @mayAlias01(i32 %a) nounwind {
784784 entry:
828828 ; }
829829 ; CHECK: define i32 @mayAlias02
830830 ; CHECK-NOT: add nsw <4 x i32>
831 ; CHECK ret
831 ; CHECK: ret
832832
833833 define i32 @mayAlias02(i32 %a) nounwind {
834834 entry:
878878 ; }
879879 ; CHECK: define i32 @mayAlias03
880880 ; CHECK-NOT: add nsw <4 x i32>
881 ; CHECK ret
881 ; CHECK: ret
882882
883883 define i32 @mayAlias03(i32 %a) nounwind {
884884 entry:
935935 ; }
936936 ; CHECK: define i32 @mustAlias01
937937 ; CHECK-NOT: add nsw <4 x i32>
938 ; CHECK ret
938 ; CHECK: ret
939939
940940 define i32 @mustAlias01(i32 %a) nounwind {
941941 entry:
985985 ; }
986986 ; CHECK: define i32 @mustAlias02
987987 ; CHECK-NOT: add nsw <4 x i32>
988 ; CHECK ret
988 ; CHECK: ret
989989
990990 define i32 @mustAlias02(i32 %a) nounwind {
991991 entry:
10341034 ; }
10351035 ; CHECK: define i32 @mustAlias03
10361036 ; CHECK-NOT: add nsw <4 x i32>
1037 ; CHECK ret
1037 ; CHECK: ret
10381038
10391039 define i32 @mustAlias03(i32 %a) nounwind {
10401040 entry: