llvm.org GIT mirror llvm / 1c76d0e
Add explicit types for shift count constants. This is in preparation for another change that makes the types ambiguous (at least as far as tablegen is concerned). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73909 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
2 changed file(s) with 52 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
854854 defm UXTB16 : AI_unary_rrot<0b01101100,
855855 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
856856
857 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
857 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
858858 (UXTB16r_rot GPR:$Src, 24)>;
859 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
859 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
860860 (UXTB16r_rot GPR:$Src, 8)>;
861861
862862 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
10371037 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
10381038 !strconcat(opc, "bt"), " $dst, $a, $b",
10391039 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1040 (sra GPR:$b, 16)))]>,
1040 (sra GPR:$b, (i32 16))))]>,
10411041 Requires<[IsARM, HasV5TE]> {
10421042 let Inst{5} = 0;
10431043 let Inst{6} = 1;
10451045
10461046 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
10471047 !strconcat(opc, "tb"), " $dst, $a, $b",
1048 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1048 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
10491049 (sext_inreg GPR:$b, i16)))]>,
10501050 Requires<[IsARM, HasV5TE]> {
10511051 let Inst{5} = 1;
10541054
10551055 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
10561056 !strconcat(opc, "tt"), " $dst, $a, $b",
1057 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1058 (sra GPR:$b, 16)))]>,
1057 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1058 (sra GPR:$b, (i32 16))))]>,
10591059 Requires<[IsARM, HasV5TE]> {
10601060 let Inst{5} = 1;
10611061 let Inst{6} = 1;
10641064 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
10651065 !strconcat(opc, "wb"), " $dst, $a, $b",
10661066 [(set GPR:$dst, (sra (opnode GPR:$a,
1067 (sext_inreg GPR:$b, i16)), 16))]>,
1067 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
10681068 Requires<[IsARM, HasV5TE]> {
10691069 let Inst{5} = 1;
10701070 let Inst{6} = 0;
10731073 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
10741074 !strconcat(opc, "wt"), " $dst, $a, $b",
10751075 [(set GPR:$dst, (sra (opnode GPR:$a,
1076 (sra GPR:$b, 16)), 16))]>,
1076 (sra GPR:$b, (i32 16))), (i32 16)))]>,
10771077 Requires<[IsARM, HasV5TE]> {
10781078 let Inst{5} = 1;
10791079 let Inst{6} = 1;
10951095 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
10961096 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
10971097 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1098 (sra GPR:$b, 16))))]>,
1098 (sra GPR:$b, (i32 16)))))]>,
10991099 Requires<[IsARM, HasV5TE]> {
11001100 let Inst{5} = 0;
11011101 let Inst{6} = 1;
11031103
11041104 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
11051105 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1106 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1106 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
11071107 (sext_inreg GPR:$b, i16))))]>,
11081108 Requires<[IsARM, HasV5TE]> {
11091109 let Inst{5} = 1;
11121112
11131113 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
11141114 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1115 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1116 (sra GPR:$b, 16))))]>,
1115 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1116 (sra GPR:$b, (i32 16)))))]>,
11171117 Requires<[IsARM, HasV5TE]> {
11181118 let Inst{5} = 1;
11191119 let Inst{6} = 1;
11221122 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
11231123 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
11241124 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1125 (sext_inreg GPR:$b, i16)), 16)))]>,
1125 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
11261126 Requires<[IsARM, HasV5TE]> {
11271127 let Inst{5} = 0;
11281128 let Inst{6} = 0;
11311131 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
11321132 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
11331133 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1134 (sra GPR:$b, 16)), 16)))]>,
1134 (sra GPR:$b, (i32 16))), (i32 16))))]>,
11351135 Requires<[IsARM, HasV5TE]> {
11361136 let Inst{5} = 0;
11371137 let Inst{6} = 1;
11671167 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
11681168 "rev16", " $dst, $src",
11691169 [(set GPR:$dst,
1170 (or (and (srl GPR:$src, 8), 0xFF),
1171 (or (and (shl GPR:$src, 8), 0xFF00),
1172 (or (and (srl GPR:$src, 8), 0xFF0000),
1173 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1170 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1171 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1172 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1173 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
11741174 Requires<[IsARM, HasV6]> {
11751175 let Inst{7-4} = 0b1011;
11761176 let Inst{11-8} = 0b1111;
11811181 "revsh", " $dst, $src",
11821182 [(set GPR:$dst,
11831183 (sext_inreg
1184 (or (srl (and GPR:$src, 0xFF00), 8),
1185 (shl GPR:$src, 8)), i16))]>,
1184 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1185 (shl GPR:$src, (i32 8))), i16))]>,
11861186 Requires<[IsARM, HasV6]> {
11871187 let Inst{7-4} = 0b1011;
11881188 let Inst{11-8} = 0b1111;
12171217
12181218 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
12191219 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1220 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1220 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
12211221 (PKHTB GPR:$src1, GPR:$src2, 16)>;
12221222 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
12231223 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
13691369 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
13701370
13711371 // smul* and smla*
1372 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1372 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1373 (sra (shl GPR:$b, (i32 16)), (i32 16))),
13731374 (SMULBB GPR:$a, GPR:$b)>;
13741375 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
13751376 (SMULBB GPR:$a, GPR:$b)>;
1376 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1377 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1378 (sra GPR:$b, (i32 16))),
13771379 (SMULBT GPR:$a, GPR:$b)>;
1378 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1380 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
13791381 (SMULBT GPR:$a, GPR:$b)>;
1380 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1382 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1383 (sra (shl GPR:$b, (i32 16)), (i32 16))),
13811384 (SMULTB GPR:$a, GPR:$b)>;
1382 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1385 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
13831386 (SMULTB GPR:$a, GPR:$b)>;
1384 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1387 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1388 (i32 16)),
13851389 (SMULWB GPR:$a, GPR:$b)>;
1386 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1390 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
13871391 (SMULWB GPR:$a, GPR:$b)>;
13881392
13891393 def : ARMV5TEPat<(add GPR:$acc,
1390 (mul (sra (shl GPR:$a, 16), 16),
1391 (sra (shl GPR:$b, 16), 16))),
1394 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1395 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
13921396 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
13931397 def : ARMV5TEPat<(add GPR:$acc,
13941398 (mul sext_16_node:$a, sext_16_node:$b)),
13951399 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
13961400 def : ARMV5TEPat<(add GPR:$acc,
1397 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1401 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1402 (sra GPR:$b, (i32 16)))),
13981403 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
13991404 def : ARMV5TEPat<(add GPR:$acc,
1400 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1405 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
14011406 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
14021407 def : ARMV5TEPat<(add GPR:$acc,
1403 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1408 (mul (sra GPR:$a, (i32 16)),
1409 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
14041410 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
14051411 def : ARMV5TEPat<(add GPR:$acc,
1406 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1412 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
14071413 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
14081414 def : ARMV5TEPat<(add GPR:$acc,
1409 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1415 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1416 (i32 16))),
14101417 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
14111418 def : ARMV5TEPat<(add GPR:$acc,
1412 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1419 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
14131420 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
14141421
14151422 //===----------------------------------------------------------------------===//
318318
319319 def tASRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
320320 "asr $dst, $lhs, $rhs",
321 [(set tGPR:$dst, (sra tGPR:$lhs, imm:$rhs))]>;
321 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
322322
323323 def tASRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
324324 "asr $dst, $rhs",
366366
367367 def tLSLri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
368368 "lsl $dst, $lhs, $rhs",
369 [(set tGPR:$dst, (shl tGPR:$lhs, imm:$rhs))]>;
369 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
370370
371371 def tLSLrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
372372 "lsl $dst, $rhs",
374374
375375 def tLSRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
376376 "lsr $dst, $lhs, $rhs",
377 [(set tGPR:$dst, (srl tGPR:$lhs, imm:$rhs))]>;
377 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
378378
379379 def tLSRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
380380 "lsr $dst, $rhs",
428428 def tREV16 : TI<(outs tGPR:$dst), (ins tGPR:$src),
429429 "rev16 $dst, $src",
430430 [(set tGPR:$dst,
431 (or (and (srl tGPR:$src, 8), 0xFF),
432 (or (and (shl tGPR:$src, 8), 0xFF00),
433 (or (and (srl tGPR:$src, 8), 0xFF0000),
434 (and (shl tGPR:$src, 8), 0xFF000000)))))]>,
431 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
432 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
433 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
434 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
435435 Requires<[IsThumb, HasV6]>;
436436
437437 def tREVSH : TI<(outs tGPR:$dst), (ins tGPR:$src),
438438 "revsh $dst, $src",
439439 [(set tGPR:$dst,
440440 (sext_inreg
441 (or (srl (and tGPR:$src, 0xFFFF), 8),
442 (shl tGPR:$src, 8)), i16))]>,
441 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
442 (shl tGPR:$src, (i32 8))), i16))]>,
443443 Requires<[IsThumb, HasV6]>;
444444
445445 def tROR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),