llvm.org GIT mirror llvm / 1c6936f
Fully fix Bug #22115. Summary: In the previous commit, the register was saved, but space was not allocated. This resulted in the parameter save area potentially clobbering r30, leading to nasty results. Test Plan: Tests updated Reviewers: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6906 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225573 91177308-0d34-0410-b5e6-96231b3b80d8 Justin Hibbits 5 years ago
4 changed file(s) with 68 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
610610 }
611611 }
612612
613 int PBPOffset = 0;
614 if (FI->usesPICBase()) {
615 MachineFrameInfo *FFI = MF.getFrameInfo();
616 int PBPIndex = FI->getPICBasePointerSaveIndex();
617 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
618 PBPOffset = FFI->getObjectOffset(PBPIndex);
619 }
620
613621 // Get stack alignments.
614622 unsigned MaxAlign = MFI->getMaxAlignment();
615623 if (HasBP && MaxAlign > 1)
643651 .addImm(FPOffset)
644652 .addReg(SPReg);
645653
646 if (isPIC && !isDarwinABI && !isPPC64 &&
647 MF.getInfo()->usesPICBase())
654 if (FI->usesPICBase())
648655 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
649656 BuildMI(MBB, MBBI, dl, StoreInst)
650657 .addReg(PPC::R30)
651 .addImm(-8U)
658 .addImm(PBPOffset)
652659 .addReg(SPReg);
653660
654661 if (HasBP)
762769 .addCFIIndex(CFIIndex);
763770 }
764771
772 if (FI->usesPICBase()) {
773 // Describe where FP was saved, at a fixed offset from CFA.
774 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
775 CFIIndex = MMI.addFrameInst(
776 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
777 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
778 .addCFIIndex(CFIIndex);
779 }
780
765781 if (HasBP) {
766782 // Describe where BP was saved, at a fixed offset from CFA.
767783 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
929945 isDarwinABI,
930946 isPIC);
931947 }
948 }
949
950 int PBPOffset = 0;
951 if (FI->usesPICBase()) {
952 MachineFrameInfo *FFI = MF.getFrameInfo();
953 int PBPIndex = FI->getPICBasePointerSaveIndex();
954 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
955 PBPOffset = FFI->getObjectOffset(PBPIndex);
932956 }
933957
934958 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
10101034 .addImm(FPOffset)
10111035 .addReg(SPReg);
10121036
1013 if (isPIC && !isDarwinABI && !isPPC64 &&
1014 MF.getInfo()->usesPICBase())
1037 if (FI->usesPICBase())
10151038 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
10161039 BuildMI(MBB, MBBI, dl, LoadInst)
10171040 .addReg(PPC::R30)
1018 .addImm(-8U)
1041 .addImm(PBPOffset)
10191042 .addReg(SPReg);
10201043
10211044 if (HasBP)
11341157 FI->setBasePointerSaveIndex(BPSI);
11351158 }
11361159
1160 // Reserve stack space for the PIC Base register (R30).
1161 // Only used in SVR4 32-bit.
1162 if (FI->usesPICBase()) {
1163 int PBPSI = FI->getPICBasePointerSaveIndex();
1164 PBPSI = MFI->CreateFixedObject(4, -8, true);
1165 FI->setPICBasePointerSaveIndex(PBPSI);
1166 }
1167
11371168 // Reserve stack space to move the linkage area to in case of a tail call.
11381169 int TCSPDelta = 0;
11391170 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
12611292
12621293 int FI = PFI->getFramePointerSaveIndex();
12631294 assert(FI && "No Frame Pointer Save Slot!");
1295
1296 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1297 }
1298
1299 if (PFI->usesPICBase()) {
1300 HasGPSaveArea = true;
1301
1302 int FI = PFI->getPICBasePointerSaveIndex();
1303 assert(FI && "No PIC Base Pointer Save Slot!");
12641304
12651305 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
12661306 }
3333
3434 /// Frame index where the old base pointer is stored.
3535 int BasePointerSaveIndex;
36
37 /// Frame index where the old PIC base pointer is stored.
38 int PICBasePointerSaveIndex;
3639
3740 /// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current
3841 /// function. This is only valid after the initial scan of the function by
102105 : FramePointerSaveIndex(0),
103106 ReturnAddrSaveIndex(0),
104107 BasePointerSaveIndex(0),
108 PICBasePointerSaveIndex(0),
105109 HasSpills(false),
106110 HasNonRISpills(false),
107111 SpillsCR(false),
126130
127131 int getBasePointerSaveIndex() const { return BasePointerSaveIndex; }
128132 void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; }
133
134 int getPICBasePointerSaveIndex() const { return PICBasePointerSaveIndex; }
135 void setPICBasePointerSaveIndex(int Idx) { PICBasePointerSaveIndex = Idx; }
129136
130137 unsigned getMinReservedArea() const { return MinReservedArea; }
131138 void setMinReservedArea(unsigned size) { MinReservedArea = size; }
0 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=LARGE-BSS %s
11 @bar = common global i32 0, align 4
2
3 declare i32 @call_foo(i32, ...)
24
35 define i32 @foo() {
46 entry:
57 %0 = load i32* @bar, align 4
8 %call = call i32 (i32, ...)* @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64)
69 ret i32 %0
710 }
811
1720 ; LARGE-BSS: mflr 30
1821 ; LARGE-BSS: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30)
1922 ; LARGE-BSS-NEXT: add 30, [[REG]], 30
20 ; LARGE-BSS: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
23 ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
2124 ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
22 ; LARGE-BSS-DAG: lwz 30, -8(1)
25 ; LARGE-BSS-DAG: stw {{[0-9]+}}, 8(1)
26 ; LARGE-BSS: lwz 30, -8(1)
2327 ; LARGE-BSS: [[VREF]]:
2428 ; LARGE-BSS-NEXT: .long bar
0 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=SMALL-BSS %s
11 @bar = common global i32 0, align 4
2
3 declare i32 @call_foo(i32, ...)
24
35 define i32 @foo() {
46 entry:
57 %0 = load i32* @bar, align 4
6 ret i32 %0
8 %call = call i32 (i32, ...)* @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64)
9 ret i32 0
710 }
811
912 !llvm.module.flags = !{!0}
1013 !0 = !{i32 1, !"PIC Level", i32 1}
1114 ; SMALL-BSS-LABEL:foo:
1215 ; SMALL-BSS: stw 30, -8(1)
16 ; SMALL-BSS: stwu 1, -32(1)
1317 ; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_@local-4
1418 ; SMALL-BSS: mflr 30
15 ; SMALL-BSS: lwz [[VREG:[0-9]+]], bar@GOT(30)
19 ; SMALL-BSS-DAG: stw {{[0-9]+}}, 8(1)
20 ; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30)
1621 ; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
17 ; SMALL-BSS-DAG: lwz 30, -8(1)
22 ; SMALL-BSS: bl call_foo@PLT
23 ; SMALL-BSS: lwz 30, -8(1)