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Merging r202774: ------------------------------------------------------------------------ r202774 | reid | 2014-03-03 19:33:17 -0500 (Mon, 03 Mar 2014) | 7 lines MC: Fix Intel assembly parser for [global + offset] We were dropping the displacement on the floor if we also had some immediate offset. Should fix PR19033. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206061 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
2 changed file(s) with 35 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
11801180 unsigned Scale, SMLoc Start, SMLoc End,
11811181 unsigned Size, StringRef Identifier,
11821182 InlineAsmIdentifierInfo &Info){
1183 if (isa(Disp)) {
1184 // If this is not a VarDecl then assume it is a FuncDecl or some other label
1185 // reference. We need an 'r' constraint here, so we need to create register
1186 // operand to ensure proper matching. Just pick a GPR based on the size of
1187 // a pointer.
1188 if (!Info.IsVarDecl) {
1189 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1190 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,
1191 SMLoc(), Identifier, Info.OpDecl);
1192 }
1183 // If this is not a VarDecl then assume it is a FuncDecl or some other label
1184 // reference. We need an 'r' constraint here, so we need to create register
1185 // operand to ensure proper matching. Just pick a GPR based on the size of
1186 // a pointer.
1187 if (isa(Disp) && !Info.IsVarDecl) {
1188 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1189 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,
1190 SMLoc(), Identifier, Info.OpDecl);
1191 }
1192
1193 // We either have a direct symbol reference, or an offset from a symbol. The
1194 // parser always puts the symbol on the LHS, so look there for size
1195 // calculation purposes.
1196 const MCBinaryExpr *BinOp = dyn_cast(Disp);
1197 bool IsSymRef =
1198 isa(BinOp ? BinOp->getLHS() : Disp);
1199 if (IsSymRef) {
11931200 if (!Size) {
11941201 Size = Info.Type * 8; // Size is in terms of bits in this context.
11951202 if (Size)
13701377 if (ParseIntelExpression(SM, End))
13711378 return 0;
13721379
1373 const MCExpr *Disp;
1380 const MCExpr *Disp = 0;
13741381 if (const MCExpr *Sym = SM.getSym()) {
13751382 // A symbolic displacement.
13761383 Disp = Sym;
13781385 RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),
13791386 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
13801387 End);
1381 } else {
1382 // An immediate displacement only.
1383 Disp = MCConstantExpr::Create(SM.getImm(), getContext());
1388 }
1389
1390 if (SM.getImm() || !Disp) {
1391 const MCExpr *Imm = MCConstantExpr::Create(SM.getImm(), getContext());
1392 if (Disp)
1393 Disp = MCBinaryExpr::CreateAdd(Disp, Imm, getContext());
1394 else
1395 Disp = Imm; // An immediate displacement only.
13841396 }
13851397
13861398 // Parse struct field access. Intel requires a dot, but MSVC doesn't. MSVC
583583 fsubr ST(1)
584584 fdiv ST(1)
585585 fdivr ST(1)
586
587 .bss
588 .globl _g0
589 .text
590
591 // CHECK: movq _g0, %rbx
592 // CHECK: movq _g0+8, %rcx
593 mov rbx, qword ptr [_g0]
594 mov rcx, qword ptr [_g0 + 8]