llvm.org GIT mirror llvm / 1c038cf
[AMDGPU] Assembler: Basic support for MIMG Add parsing and printing of image operands. Matches legacy sp3 assembler. Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last. Update SITargetLowering for new order. Add basic MC test. Update CodeGen tests. Review: http://reviews.llvm.org/D17574 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261995 91177308-0d34-0410-b5e6-96231b3b80d8 Nikolay Haustov 4 years ago
17 changed file(s) with 322 addition(s) and 164 deletion(s). Raw diff Collapse all Expand all
6666 ImmTySLC,
6767 ImmTyTFE,
6868 ImmTyClamp,
69 ImmTyOMod
69 ImmTyOMod,
70 ImmTyDMask,
71 ImmTyUNorm,
72 ImmTyDA,
73 ImmTyR128,
74 ImmTyLWE,
7075 };
7176
7277 struct TokOp {
193198 return Kind == Register || isInlinableImm();
194199 }
195200
201 bool isImmTy(ImmTy ImmT) const {
202 return isImm() && Imm.Type == ImmT;
203 }
204
196205 bool isClamp() const {
197 return isImm() && Imm.Type == ImmTyClamp;
206 return isImmTy(ImmTyClamp);
198207 }
199208
200209 bool isOMod() const {
201 return isImm() && Imm.Type == ImmTyOMod;
202 }
210 return isImmTy(ImmTyOMod);
211 }
212
213 bool isImmModifier() const {
214 return Kind == Immediate && Imm.Type != ImmTyNone;
215 }
216
217 bool isDMask() const {
218 return isImmTy(ImmTyDMask);
219 }
220
221 bool isUNorm() const { return isImmTy(ImmTyUNorm); }
222 bool isDA() const { return isImmTy(ImmTyDA); }
223 bool isR128() const { return isImmTy(ImmTyUNorm); }
224 bool isLWE() const { return isImmTy(ImmTyLWE); }
203225
204226 bool isMod() const {
205227 return isClamp() || isOMod();
496518
497519 OperandMatchResultTy parseDMask(OperandVector &Operands);
498520 OperandMatchResultTy parseUNorm(OperandVector &Operands);
521 OperandMatchResultTy parseDA(OperandVector &Operands);
499522 OperandMatchResultTy parseR128(OperandVector &Operands);
523 OperandMatchResultTy parseLWE(OperandVector &Operands);
500524
501525 void cvtId(MCInst &Inst, const OperandVector &Operands);
502526 void cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands);
503527 void cvtVOP3_2_nomod(MCInst &Inst, const OperandVector &Operands);
504528 void cvtVOP3_only(MCInst &Inst, const OperandVector &Operands);
505529 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
530
531 void cvtMIMG(MCInst &Inst, const OperandVector &Operands);
506532 OperandMatchResultTy parseVOP3OptionalOps(OperandVector &Operands);
507533 };
508534
17501776
17511777 AMDGPUAsmParser::OperandMatchResultTy
17521778 AMDGPUAsmParser::parseDMask(OperandVector &Operands) {
1753 return parseIntWithPrefix("dmask", Operands);
1779 return parseIntWithPrefix("dmask", Operands, AMDGPUOperand::ImmTyDMask);
17541780 }
17551781
17561782 AMDGPUAsmParser::OperandMatchResultTy
17571783 AMDGPUAsmParser::parseUNorm(OperandVector &Operands) {
1758 return parseNamedBit("unorm", Operands);
1784 return parseNamedBit("unorm", Operands, AMDGPUOperand::ImmTyUNorm);
1785 }
1786
1787 AMDGPUAsmParser::OperandMatchResultTy
1788 AMDGPUAsmParser::parseDA(OperandVector &Operands) {
1789 return parseNamedBit("da", Operands, AMDGPUOperand::ImmTyDA);
17591790 }
17601791
17611792 AMDGPUAsmParser::OperandMatchResultTy
17621793 AMDGPUAsmParser::parseR128(OperandVector &Operands) {
1763 return parseNamedBit("r128", Operands);
1794 return parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128);
1795 }
1796
1797 AMDGPUAsmParser::OperandMatchResultTy
1798 AMDGPUAsmParser::parseLWE(OperandVector &Operands) {
1799 return parseNamedBit("lwe", Operands, AMDGPUOperand::ImmTyLWE);
17641800 }
17651801
17661802 //===----------------------------------------------------------------------===//
19301966 }
19311967 }
19321968
1969 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
1970 OptionalImmIndexMap OptionalIdx;
1971
1972 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
1973 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1974
1975 // Add the register arguments
1976 if (Op.isRegOrImm()) {
1977 Op.addRegOrImmOperands(Inst, 1);
1978 continue;
1979 } else if (Op.isImmModifier()) {
1980 OptionalIdx[Op.getImmTy()] = i;
1981 } else {
1982 assert(false);
1983 }
1984 }
1985
1986 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
1987 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
1988 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
1989 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
1990 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
1991 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
1992 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
1993 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
1994 }
1995
1996
19331997 /// Force static initialization.
19341998 extern "C" void LLVMInitializeAMDGPUAsmParser() {
19351999 RegisterMCAsmParser A(TheAMDGPUTarget);
5252 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
5353 }
5454
55 void AMDGPUInstPrinter::printNamedBit(const MCInst* MI, unsigned OpNo, raw_ostream& O, const char* BitName) {
56 if (MI->getOperand(OpNo).getImm()) {
57 O << " " << BitName;
58 }
59 }
60
5561 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
5662 raw_ostream &O) {
57 if (MI->getOperand(OpNo).getImm())
58 O << " offen";
63 printNamedBit(MI, OpNo, O, "offen");
5964 }
6065
6166 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
6267 raw_ostream &O) {
63 if (MI->getOperand(OpNo).getImm())
64 O << " idxen";
68 printNamedBit(MI, OpNo, O, "idxen");
6569 }
6670
6771 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
6872 raw_ostream &O) {
69 if (MI->getOperand(OpNo).getImm())
70 O << " addr64";
73 printNamedBit(MI, OpNo, O, "addr64");
7174 }
7275
7376 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
105108
106109 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
107110 raw_ostream &O) {
108 if (MI->getOperand(OpNo).getImm())
109 O << " gds";
111 printNamedBit(MI, OpNo, O, "gds");
110112 }
111113
112114 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
113115 raw_ostream &O) {
114 if (MI->getOperand(OpNo).getImm())
115 O << " glc";
116 printNamedBit(MI, OpNo, O, "glc");
116117 }
117118
118119 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
119120 raw_ostream &O) {
120 if (MI->getOperand(OpNo).getImm())
121 O << " slc";
121 printNamedBit(MI, OpNo, O, "slc");
122122 }
123123
124124 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
125125 raw_ostream &O) {
126 if (MI->getOperand(OpNo).getImm())
127 O << " tfe";
126 printNamedBit(MI, OpNo, O, "tfe");
127 }
128
129 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
130 raw_ostream &O) {
131 if (MI->getOperand(OpNo).getImm()) {
132 O << " dmask:";
133 printU16ImmOperand(MI, OpNo, O);
134 }
135 }
136
137 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
138 raw_ostream &O) {
139 printNamedBit(MI, OpNo, O, "unorm");
140 }
141
142 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
143 raw_ostream &O) {
144 printNamedBit(MI, OpNo, O, "da");
145 }
146
147 void AMDGPUInstPrinter::printR128(const MCInst *MI, unsigned OpNo,
148 raw_ostream &O) {
149 printNamedBit(MI, OpNo, O, "r128");
150 }
151
152 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
153 raw_ostream &O) {
154 printNamedBit(MI, OpNo, O, "lwe");
128155 }
129156
130157 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
3737 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
3838 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
3939 void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
40 void printNamedBit(const MCInst* MI, unsigned OpNo, raw_ostream& O, const char* BitName);
4041 void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4142 void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4243 void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4849 void printGLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4950 void printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
5051 void printTFE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
52 void printDMask(const MCInst *MI, unsigned OpNo, raw_ostream &O);
53 void printUNorm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
54 void printDA(const MCInst *MI, unsigned OpNo, raw_ostream &O);
55 void printR128(const MCInst *MI, unsigned OpNo, raw_ostream &O);
56 void printLWE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
5157 void printRegOperand(unsigned RegNo, raw_ostream &O);
5258 void printVOPDst(const MCInst *MI, unsigned OpNo, raw_ostream &O);
5359 void printImmediate32(uint32_t I, raw_ostream &O);
26562656 SelectionDAG &DAG) const {
26572657 SDNode *Users[4] = { };
26582658 unsigned Lane = 0;
2659 unsigned OldDmask = Node->getConstantOperandVal(0);
2659 unsigned DmaskIdx = (Node->getNumOperands() - Node->getNumValues() == 9) ? 2 : 3;
2660 unsigned OldDmask = Node->getConstantOperandVal(DmaskIdx);
26602661 unsigned NewDmask = 0;
26612662
26622663 // Try to figure out the used register components
26962697
26972698 // Adjust the writemask in the node
26982699 std::vector Ops;
2700 Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
26992701 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
2700 Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
2702 Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
27012703 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
27022704
27032705 // If we only got one lane, replace it with a copy
27952797
27962798 if (TII->isMIMG(*MI)) {
27972799 unsigned VReg = MI->getOperand(0).getReg();
2798 unsigned Writemask = MI->getOperand(1).getImm();
2800 unsigned DmaskIdx = MI->getNumOperands() == 12 ? 3 : 4;
2801 unsigned Writemask = MI->getOperand(DmaskIdx).getImm();
27992802 unsigned BitsSet = 0;
28002803 for (unsigned i = 0; i < 4; ++i)
28012804 BitsSet += Writemask & (1 << i) ? 1 : 0;
532532 class OptionalImmAsmOperand : AsmOperandClass {
533533 let Name = "Imm"#OpName;
534534 let PredicateMethod = "isImm";
535 let RenderMethod = "addImmOperands";
535536 let IsOptional = 1;
537 }
538
539 def DMaskMatchClass : AsmOperandClass {
540 let Name = "DMask";
541 let PredicateMethod = "isDMask";
542 let ParserMethod = "parseDMask";
543 let RenderMethod = "addImmOperands";
544 let IsOptional = 1;
545 }
546
547 class NamedBitMatchClass : AsmOperandClass {
548 let Name = "Imm"#BitName;
549 let PredicateMethod = "is"#BitName;
550 let ParserMethod = "parse"#BitName;
551 let RenderMethod = "addImmOperands";
552 let IsOptional = 1;
553 }
554
555 class NamedBitOperand : Operand {
556 let PrintMethod = "print"#BitName;
536557 }
537558
538559 let OperandType = "OPERAND_IMMEDIATE" in {
621642 let ParserMatchClass = SMRDLiteralOffsetMatchClass;
622643 }
623644
645 def dmask : Operand {
646 let PrintMethod = "printDMask";
647 let ParserMatchClass = DMaskMatchClass;
648 }
649
650 def unorm : NamedBitOperand<"UNorm"> {
651 let ParserMatchClass = NamedBitMatchClass<"UNorm">;
652 }
653
654 def da : NamedBitOperand<"DA"> {
655 let ParserMatchClass = NamedBitMatchClass<"DA">;
656 }
657
658 def r128 : NamedBitOperand<"R128"> {
659 let ParserMatchClass = NamedBitMatchClass<"R128">;
660 }
661
662 def lwe : NamedBitOperand<"LWE"> {
663 let ParserMatchClass = NamedBitMatchClass<"LWE">;
664 }
665
624666 } // End OperandType = "OPERAND_IMMEDIATE"
667
625668
626669 def VOPDstS64 : VOPDstOperand ;
627670
29222965 let hasPostISelHook = 1;
29232966 let DecoderNamespace = dns;
29242967 let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
2968 let AsmMatchConverter = "cvtMIMG";
29252969 }
29262970
29272971 class MIMG_NoSampler_Helper op, string asm,
29302974 string dns=""> : MIMG_Helper <
29312975 op,
29322976 (outs dst_rc:$vdata),
2933 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2934 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, addr_rc:$vaddr,
2935 SReg_256:$srsrc),
2936 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2937 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2977 (ins addr_rc:$vaddr, SReg_256:$srsrc,
2978 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc,
2979 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
2980 asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da",
29382981 dns> {
29392982 let ssamp = 0;
29402983 }
29633006 RegisterClass addr_rc> : MIMG_Helper <
29643007 op,
29653008 (outs),
2966 (ins data_rc:$vdata, i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2967 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, addr_rc:$vaddr,
2968 SReg_256:$srsrc),
2969 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2970 #" $tfe, $lwe, $slc, $vaddr, $srsrc"> {
3009 (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
3010 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc,
3011 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
3012 asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
3013 > {
29713014 let ssamp = 0;
29723015 let mayLoad = 1; // TableGen requires this for matching with the intrinsics
29733016 let mayStore = 1;
30003043 string dns=""> : MIMG_Helper <
30013044 op,
30023045 (outs dst_rc:$vdata),
3003 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
3004 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
3005 SReg_256:$srsrc, SReg_128:$ssamp),
3006 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
3007 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
3046 (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
3047 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc,
3048 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
3049 asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da",
30083050 dns> {
30093051 let WQM = wqm;
30103052 }
30393081 RegisterClass src_rc, int wqm> : MIMG <
30403082 op,
30413083 (outs dst_rc:$vdata),
3042 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
3043 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
3044 SReg_256:$srsrc, SReg_128:$ssamp),
3045 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
3046 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
3084 (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
3085 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc,
3086 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
3087 asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da",
30473088 []> {
30483089 let mayLoad = 1;
30493090 let mayStore = 0;
22142214 class SampleRawPattern : Pat <
22152215 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
22162216 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2217 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2218 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2219 $addr, $rsrc, $sampler)
2217 (opcode $addr, $rsrc, $sampler,
2218 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
2219 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
22202220 >;
22212221
22222222 multiclass SampleRawPatterns {
22312231 class ImagePattern : Pat <
22322232 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm,
22332233 imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe),
2234 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2235 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2236 $addr, $rsrc)
2234 (opcode $addr, $rsrc,
2235 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
2236 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
22372237 >;
22382238
22392239 multiclass ImagePatterns {
22452245 class ImageLoadPattern : Pat <
22462246 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc,
22472247 imm:$slc),
2248 (opcode (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $da),
2249 (as_i1imm $r128), 0, 0, (as_i1imm $slc), $addr, $rsrc)
2248 (opcode $addr, $rsrc,
2249 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
2250 (as_i1imm $r128), 0, 0, (as_i1imm $da))
22502251 >;
22512252
22522253 multiclass ImageLoadPatterns {
22582259 class ImageStorePattern : Pat <
22592260 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da,
22602261 imm:$glc, imm:$slc),
2261 (opcode $data, (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $da),
2262 (as_i1imm $r128), 0, 0, (as_i1imm $slc), $addr, $rsrc)
2262 (opcode $data, $addr, $rsrc,
2263 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
2264 (as_i1imm $r128), 0, 0, (as_i1imm $da))
22632265 >;
22642266
22652267 multiclass ImageStorePatterns {
23722374 /* SIsample for simple 1D texture lookup */
23732375 def : Pat <
23742376 (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
2375 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2377 (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
23762378 >;
23772379
23782380 class SamplePattern : Pat <
23792381 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
2380 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2382 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
23812383 >;
23822384
23832385 class SampleRectPattern : Pat <
23842386 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT),
2385 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2387 (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0)
23862388 >;
23872389
23882390 class SampleArrayPattern : Pat <
23892391 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY),
2390 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2392 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
23912393 >;
23922394
23932395 class SampleShadowPattern
23942396 ValueType vt> : Pat <
23952397 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW),
2396 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2398 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
23972399 >;
23982400
23992401 class SampleShadowArrayPattern
24002402 ValueType vt> : Pat <
24012403 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2402 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2404 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
24032405 >;
24042406
24052407 /* SIsample* for texture lookups consuming more address parameters */
11 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
22
33 ;CHECK-LABEL: {{^}}gather4_v2:
4 ;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
4 ;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
55 define void @gather4_v2() #0 {
66 main_body:
77 %r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
1414 }
1515
1616 ;CHECK-LABEL: {{^}}gather4:
17 ;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
17 ;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
1818 define void @gather4() #0 {
1919 main_body:
2020 %r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
2727 }
2828
2929 ;CHECK-LABEL: {{^}}gather4_cl:
30 ;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
30 ;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
3131 define void @gather4_cl() #0 {
3232 main_body:
3333 %r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
4040 }
4141
4242 ;CHECK-LABEL: {{^}}gather4_l:
43 ;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
43 ;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
4444 define void @gather4_l() #0 {
4545 main_body:
4646 %r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
5353 }
5454
5555 ;CHECK-LABEL: {{^}}gather4_b:
56 ;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
56 ;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
5757 define void @gather4_b() #0 {
5858 main_body:
5959 %r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
6666 }
6767
6868 ;CHECK-LABEL: {{^}}gather4_b_cl:
69 ;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
69 ;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
7070 define void @gather4_b_cl() #0 {
7171 main_body:
7272 %r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
7979 }
8080
8181 ;CHECK-LABEL: {{^}}gather4_b_cl_v8:
82 ;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
82 ;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
8383 define void @gather4_b_cl_v8() #0 {
8484 main_body:
8585 %r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
9292 }
9393
9494 ;CHECK-LABEL: {{^}}gather4_lz_v2:
95 ;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
95 ;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
9696 define void @gather4_lz_v2() #0 {
9797 main_body:
9898 %r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
105105 }
106106
107107 ;CHECK-LABEL: {{^}}gather4_lz:
108 ;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
108 ;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
109109 define void @gather4_lz() #0 {
110110 main_body:
111111 %r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
120120
121121
122122 ;CHECK-LABEL: {{^}}gather4_o:
123 ;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
123 ;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
124124 define void @gather4_o() #0 {
125125 main_body:
126126 %r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
133133 }
134134
135135 ;CHECK-LABEL: {{^}}gather4_cl_o:
136 ;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
136 ;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
137137 define void @gather4_cl_o() #0 {
138138 main_body:
139139 %r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
146146 }
147147
148148 ;CHECK-LABEL: {{^}}gather4_cl_o_v8:
149 ;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
149 ;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
150150 define void @gather4_cl_o_v8() #0 {
151151 main_body:
152152 %r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
159159 }
160160
161161 ;CHECK-LABEL: {{^}}gather4_l_o:
162 ;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
162 ;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
163163 define void @gather4_l_o() #0 {
164164 main_body:
165165 %r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
172172 }
173173
174174 ;CHECK-LABEL: {{^}}gather4_l_o_v8:
175 ;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
175 ;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
176176 define void @gather4_l_o_v8() #0 {
177177 main_body:
178178 %r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
185185 }
186186
187187 ;CHECK-LABEL: {{^}}gather4_b_o:
188 ;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
188 ;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
189189 define void @gather4_b_o() #0 {
190190 main_body:
191191 %r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
198198 }
199199
200200 ;CHECK-LABEL: {{^}}gather4_b_o_v8:
201 ;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
201 ;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
202202 define void @gather4_b_o_v8() #0 {
203203 main_body:
204204 %r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
211211 }
212212
213213 ;CHECK-LABEL: {{^}}gather4_b_cl_o:
214 ;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
214 ;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
215215 define void @gather4_b_cl_o() #0 {
216216 main_body:
217217 %r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
224224 }
225225
226226 ;CHECK-LABEL: {{^}}gather4_lz_o:
227 ;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
227 ;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
228228 define void @gather4_lz_o() #0 {
229229 main_body:
230230 %r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
239239
240240
241241 ;CHECK-LABEL: {{^}}gather4_c:
242 ;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
242 ;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
243243 define void @gather4_c() #0 {
244244 main_body:
245245 %r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
252252 }
253253
254254 ;CHECK-LABEL: {{^}}gather4_c_cl:
255 ;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
255 ;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
256256 define void @gather4_c_cl() #0 {
257257 main_body:
258258 %r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
265265 }
266266
267267 ;CHECK-LABEL: {{^}}gather4_c_cl_v8:
268 ;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
268 ;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
269269 define void @gather4_c_cl_v8() #0 {
270270 main_body:
271271 %r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
278278 }
279279
280280 ;CHECK-LABEL: {{^}}gather4_c_l:
281 ;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
281 ;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
282282 define void @gather4_c_l() #0 {
283283 main_body:
284284 %r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
291291 }
292292
293293 ;CHECK-LABEL: {{^}}gather4_c_l_v8:
294 ;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
294 ;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
295295 define void @gather4_c_l_v8() #0 {
296296 main_body:
297297 %r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
304304 }
305305
306306 ;CHECK-LABEL: {{^}}gather4_c_b:
307 ;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
307 ;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
308308 define void @gather4_c_b() #0 {
309309 main_body:
310310 %r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
317317 }
318318
319319 ;CHECK-LABEL: {{^}}gather4_c_b_v8:
320 ;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
320 ;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
321321 define void @gather4_c_b_v8() #0 {
322322 main_body:
323323 %r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
330330 }
331331
332332 ;CHECK-LABEL: {{^}}gather4_c_b_cl:
333 ;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
333 ;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
334334 define void @gather4_c_b_cl() #0 {
335335 main_body:
336336 %r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
343343 }
344344
345345 ;CHECK-LABEL: {{^}}gather4_c_lz:
346 ;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
346 ;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
347347 define void @gather4_c_lz() #0 {
348348 main_body:
349349 %r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
358358
359359
360360 ;CHECK-LABEL: {{^}}gather4_c_o:
361 ;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
361 ;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
362362 define void @gather4_c_o() #0 {
363363 main_body:
364364 %r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
371371 }
372372
373373 ;CHECK-LABEL: {{^}}gather4_c_o_v8:
374 ;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
374 ;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
375375 define void @gather4_c_o_v8() #0 {
376376 main_body:
377377 %r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
384384 }
385385
386386 ;CHECK-LABEL: {{^}}gather4_c_cl_o:
387 ;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
387 ;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
388388 define void @gather4_c_cl_o() #0 {
389389 main_body:
390390 %r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
397397 }
398398
399399 ;CHECK-LABEL: {{^}}gather4_c_l_o:
400 ;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
400 ;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
401401 define void @gather4_c_l_o() #0 {
402402 main_body:
403403 %r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
410410 }
411411
412412 ;CHECK-LABEL: {{^}}gather4_c_b_o:
413 ;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
413 ;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
414414 define void @gather4_c_b_o() #0 {
415415 main_body:
416416 %r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
423423 }
424424
425425 ;CHECK-LABEL: {{^}}gather4_c_b_cl_o:
426 ;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
426 ;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
427427 define void @gather4_c_b_cl_o() #0 {
428428 main_body:
429429 %r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
436436 }
437437
438438 ;CHECK-LABEL: {{^}}gather4_c_lz_o:
439 ;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
439 ;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
440440 define void @gather4_c_lz_o() #0 {
441441 main_body:
442442 %r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
449449 }
450450
451451 ;CHECK-LABEL: {{^}}gather4_c_lz_o_v8:
452 ;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
452 ;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
453453 define void @gather4_c_lz_o_v8() #0 {
454454 main_body:
455455 %r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
11 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
22
33 ;CHECK-LABEL: {{^}}getlod:
4 ;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
4 ;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da
55 define void @getlod() #0 {
66 main_body:
77 %r = call <4 x float> @llvm.SI.getlod.i32(i32 undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
1212 }
1313
1414 ;CHECK-LABEL: {{^}}getlod_v2:
15 ;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
15 ;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da
1616 define void @getlod_v2() #0 {
1717 main_body:
1818 %r = call <4 x float> @llvm.SI.getlod.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
2323 }
2424
2525 ;CHECK-LABEL: {{^}}getlod_v4:
26 ;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
26 ;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da
2727 define void @getlod_v4() #0 {
2828 main_body:
2929 %r = call <4 x float> @llvm.SI.getlod.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
11 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
22
33 ;CHECK-LABEL: {{^}}image_load:
4 ;CHECK: image_load {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
4 ;CHECK: image_load {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
55 define void @image_load() #0 {
66 main_body:
77 %r = call <4 x float> @llvm.SI.image.load.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
1414 }
1515
1616 ;CHECK-LABEL: {{^}}image_load_mip:
17 ;CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
17 ;CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
1818 define void @image_load_mip() #0 {
1919 main_body:
2020 %r = call <4 x float> @llvm.SI.image.load.mip.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
2727 }
2828
2929 ;CHECK-LABEL: {{^}}getresinfo:
30 ;CHECK: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
30 ;CHECK: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
3131 define void @getresinfo() #0 {
3232 main_body:
3333 %r = call <4 x float> @llvm.SI.getresinfo.i32(i32 undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
11 ;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s
22
33 ; CHECK-LABEL: {{^}}v1:
4 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 13
4 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd
55 define void @v1(i32 %a1) #0 {
66 entry:
77 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
1414 }
1515
1616 ; CHECK-LABEL: {{^}}v2:
17 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 11
17 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb
1818 define void @v2(i32 %a1) #0 {
1919 entry:
2020 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
2727 }
2828
2929 ; CHECK-LABEL: {{^}}v3:
30 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14
30 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe
3131 define void @v3(i32 %a1) #0 {
3232 entry:
3333 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
4040 }
4141
4242 ; CHECK-LABEL: {{^}}v4:
43 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 7
43 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7
4444 define void @v4(i32 %a1) #0 {
4545 entry:
4646 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
5353 }
5454
5555 ; CHECK-LABEL: {{^}}v5:
56 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10
56 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa
5757 define void @v5(i32 %a1) #0 {
5858 entry:
5959 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
6565 }
6666
6767 ; CHECK-LABEL: {{^}}v6:
68 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 6
68 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6
6969 define void @v6(i32 %a1) #0 {
7070 entry:
7171 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
7777 }
7878
7979 ; CHECK-LABEL: {{^}}v7:
80 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 9
80 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9
8181 define void @v7(i32 %a1) #0 {
8282 entry:
8383 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
22
33 ;CHECK-LABEL: {{^}}sample:
44 ;CHECK: s_wqm
5 ;CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
5 ;CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
66 define void @sample() #0 {
77 main_body:
88 %r = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
1616
1717 ;CHECK-LABEL: {{^}}sample_cl:
1818 ;CHECK: s_wqm
19 ;CHECK: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
19 ;CHECK: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
2020 define void @sample_cl() #0 {
2121 main_body:
2222 %r = call <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
3030
3131 ;CHECK-LABEL: {{^}}sample_d:
3232 ;CHECK-NOT: s_wqm
33 ;CHECK: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
33 ;CHECK: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
3434 define void @sample_d() #0 {
3535 main_body:
3636 %r = call <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
4444
4545 ;CHECK-LABEL: {{^}}sample_d_cl:
4646 ;CHECK-NOT: s_wqm
47 ;CHECK: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
47 ;CHECK: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
4848 define void @sample_d_cl() #0 {
4949 main_body:
5050 %r = call <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
5858
5959 ;CHECK-LABEL: {{^}}sample_l:
6060 ;CHECK-NOT: s_wqm
61 ;CHECK: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
61 ;CHECK: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
6262 define void @sample_l() #0 {
6363 main_body:
6464 %r = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
7272
7373 ;CHECK-LABEL: {{^}}sample_b:
7474 ;CHECK: s_wqm
75 ;CHECK: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
75 ;CHECK: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
7676 define void @sample_b() #0 {
7777 main_body:
7878 %r = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
8686
8787 ;CHECK-LABEL: {{^}}sample_b_cl:
8888 ;CHECK: s_wqm
89 ;CHECK: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
89 ;CHECK: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
9090 define void @sample_b_cl() #0 {
9191 main_body:
9292 %r = call <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
100100
101101 ;CHECK-LABEL: {{^}}sample_lz:
102102 ;CHECK-NOT: s_wqm
103 ;CHECK: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
103 ;CHECK: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
104104 define void @sample_lz() #0 {
105105 main_body:
106106 %r = call <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
114114
115115 ;CHECK-LABEL: {{^}}sample_cd:
116116 ;CHECK-NOT: s_wqm
117 ;CHECK: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
117 ;CHECK: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
118118 define void @sample_cd() #0 {
119119 main_body:
120120 %r = call <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
128128
129129 ;CHECK-LABEL: {{^}}sample_cd_cl:
130130 ;CHECK-NOT: s_wqm
131 ;CHECK: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
131 ;CHECK: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
132132 define void @sample_cd_cl() #0 {
133133 main_body:
134134 %r = call <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
142142
143143 ;CHECK-LABEL: {{^}}sample_c:
144144 ;CHECK: s_wqm
145 ;CHECK: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
145 ;CHECK: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
146146 define void @sample_c() #0 {
147147 main_body:
148148 %r = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
156156
157157 ;CHECK-LABEL: {{^}}sample_c_cl:
158158 ;CHECK: s_wqm
159 ;CHECK: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
159 ;CHECK: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
160160 define void @sample_c_cl() #0 {
161161 main_body:
162162 %r = call <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
170170
171171 ;CHECK-LABEL: {{^}}sample_c_d:
172172 ;CHECK-NOT: s_wqm
173 ;CHECK: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
173 ;CHECK: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
174174 define void @sample_c_d() #0 {
175175 main_body:
176176 %r = call <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
184184
185185 ;CHECK-LABEL: {{^}}sample_c_d_cl:
186186 ;CHECK-NOT: s_wqm
187 ;CHECK: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
187 ;CHECK: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
188188 define void @sample_c_d_cl() #0 {
189189 main_body:
190190 %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
198198
199199 ;CHECK-LABEL: {{^}}sample_c_l:
200200 ;CHECK-NOT: s_wqm
201 ;CHECK: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
201 ;CHECK: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
202202 define void @sample_c_l() #0 {
203203 main_body:
204204 %r = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
212212
213213 ;CHECK-LABEL: {{^}}sample_c_b:
214214 ;CHECK: s_wqm
215 ;CHECK: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
215 ;CHECK: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
216216 define void @sample_c_b() #0 {
217217 main_body:
218218 %r = call <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
226226
227227 ;CHECK-LABEL: {{^}}sample_c_b_cl:
228228 ;CHECK: s_wqm
229 ;CHECK: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
229 ;CHECK: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
230230 define void @sample_c_b_cl() #0 {
231231 main_body:
232232 %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
240240
241241 ;CHECK-LABEL: {{^}}sample_c_lz:
242242 ;CHECK-NOT: s_wqm
243 ;CHECK: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
243 ;CHECK: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
244244 define void @sample_c_lz() #0 {
245245 main_body:
246246 %r = call <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
254254
255255 ;CHECK-LABEL: {{^}}sample_c_cd:
256256 ;CHECK-NOT: s_wqm
257 ;CHECK: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
257 ;CHECK: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
258258 define void @sample_c_cd() #0 {
259259 main_body:
260260 %r = call <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
268268
269269 ;CHECK-LABEL: {{^}}sample_c_cd_cl:
270270 ;CHECK-NOT: s_wqm
271 ;CHECK: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
271 ;CHECK: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
272272 define void @sample_c_cd_cl() #0 {
273273 main_body:
274274 %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
22
33 ;CHECK-LABEL: {{^}}sample:
44 ;CHECK: s_wqm
5 ;CHECK: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
5 ;CHECK: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
66 define void @sample() #0 {
77 main_body:
88 %r = call <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
1616
1717 ;CHECK-LABEL: {{^}}sample_cl:
1818 ;CHECK: s_wqm
19 ;CHECK: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
19 ;CHECK: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
2020 define void @sample_cl() #0 {
2121 main_body:
2222 %r = call <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
3030
3131 ;CHECK-LABEL: {{^}}sample_d:
3232 ;CHECK-NOT: s_wqm
33 ;CHECK: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
33 ;CHECK: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
3434 define void @sample_d() #0 {
3535 main_body:
3636 %r = call <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
4444
4545 ;CHECK-LABEL: {{^}}sample_d_cl:
4646 ;CHECK-NOT: s_wqm
47 ;CHECK: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
47 ;CHECK: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
4848 define void @sample_d_cl() #0 {
4949 main_body:
5050 %r = call <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
5858
5959 ;CHECK-LABEL: {{^}}sample_l:
6060 ;CHECK-NOT: s_wqm
61 ;CHECK: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
61 ;CHECK: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
6262 define void @sample_l() #0 {
6363 main_body:
6464 %r = call <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
7272
7373 ;CHECK-LABEL: {{^}}sample_b:
7474 ;CHECK: s_wqm
75 ;CHECK: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
75 ;CHECK: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
7676 define void @sample_b() #0 {
7777 main_body:
7878 %r = call <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
8686
8787 ;CHECK-LABEL: {{^}}sample_b_cl:
8888 ;CHECK: s_wqm
89 ;CHECK: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
89 ;CHECK: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
9090 define void @sample_b_cl() #0 {
9191 main_body:
9292 %r = call <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
100100
101101 ;CHECK-LABEL: {{^}}sample_lz:
102102 ;CHECK-NOT: s_wqm
103 ;CHECK: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
103 ;CHECK: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
104104 define void @sample_lz() #0 {
105105 main_body:
106106 %r = call <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
114114
115115 ;CHECK-LABEL: {{^}}sample_cd:
116116 ;CHECK-NOT: s_wqm
117 ;CHECK: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
117 ;CHECK: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
118118 define void @sample_cd() #0 {
119119 main_body:
120120 %r = call <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
128128
129129 ;CHECK-LABEL: {{^}}sample_cd_cl:
130130 ;CHECK-NOT: s_wqm
131 ;CHECK: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
131 ;CHECK: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
132132 define void @sample_cd_cl() #0 {
133133 main_body:
134134 %r = call <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
142142
143143 ;CHECK-LABEL: {{^}}sample_c:
144144 ;CHECK: s_wqm
145 ;CHECK: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
145 ;CHECK: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
146146 define void @sample_c() #0 {
147147 main_body:
148148 %r = call <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
156156
157157 ;CHECK-LABEL: {{^}}sample_c_cl:
158158 ;CHECK: s_wqm
159 ;CHECK: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
159 ;CHECK: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
160160 define void @sample_c_cl() #0 {
161161 main_body:
162162 %r = call <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
170170
171171 ;CHECK-LABEL: {{^}}sample_c_d:
172172 ;CHECK-NOT: s_wqm
173 ;CHECK: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
173 ;CHECK: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
174174 define void @sample_c_d() #0 {
175175 main_body:
176176 %r = call <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
184184
185185 ;CHECK-LABEL: {{^}}sample_c_d_cl:
186186 ;CHECK-NOT: s_wqm
187 ;CHECK: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
187 ;CHECK: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
188188 define void @sample_c_d_cl() #0 {
189189 main_body:
190190 %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
198198
199199 ;CHECK-LABEL: {{^}}sample_c_l:
200200 ;CHECK-NOT: s_wqm
201 ;CHECK: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
201 ;CHECK: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
202202 define void @sample_c_l() #0 {
203203 main_body:
204204 %r = call <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
212212
213213 ;CHECK-LABEL: {{^}}sample_c_b:
214214 ;CHECK: s_wqm
215 ;CHECK: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
215 ;CHECK: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
216216 define void @sample_c_b() #0 {
217217 main_body:
218218 %r = call <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
226226
227227 ;CHECK-LABEL: {{^}}sample_c_b_cl:
228228 ;CHECK: s_wqm
229 ;CHECK: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
229 ;CHECK: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
230230 define void @sample_c_b_cl() #0 {
231231 main_body:
232232 %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
240240
241241 ;CHECK-LABEL: {{^}}sample_c_lz:
242242 ;CHECK-NOT: s_wqm
243 ;CHECK: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
243 ;CHECK: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
244244 define void @sample_c_lz() #0 {
245245 main_body:
246246 %r = call <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
254254
255255 ;CHECK-LABEL: {{^}}sample_c_cd:
256256 ;CHECK-NOT: s_wqm
257 ;CHECK: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
257 ;CHECK: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
258258 define void @sample_c_cd() #0 {
259259 main_body:
260260 %r = call <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
268268
269269 ;CHECK-LABEL: {{^}}sample_c_cd_cl:
270270 ;CHECK-NOT: s_wqm
271 ;CHECK: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
271 ;CHECK: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
272272 define void @sample_c_cd_cl() #0 {
273273 main_body:
274274 %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
11 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
22
33 ;CHECK-LABEL: {{^}}image_load_v4i32:
4 ;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
4 ;CHECK: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm
55 ;CHECK: s_waitcnt vmcnt(0)
66 define <4 x float> @image_load_v4i32(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
77 main_body:
1010 }
1111
1212 ;CHECK-LABEL: {{^}}image_load_v2i32:
13 ;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[0:7]
13 ;CHECK: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm
1414 ;CHECK: s_waitcnt vmcnt(0)
1515 define <4 x float> @image_load_v2i32(<8 x i32> inreg %rsrc, <2 x i32> %c) #0 {
1616 main_body:
1919 }
2020
2121 ;CHECK-LABEL: {{^}}image_load_i32:
22 ;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v0, s[0:7]
22 ;CHECK: image_load v[0:3], v0, s[0:7] dmask:0xf unorm
2323 ;CHECK: s_waitcnt vmcnt(0)
2424 define <4 x float> @image_load_i32(<8 x i32> inreg %rsrc, i32 %c) #0 {
2525 main_body:
2828 }
2929
3030 ;CHECK-LABEL: {{^}}image_load_mip:
31 ;CHECK: image_load_mip v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
31 ;CHECK: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm
3232 ;CHECK: s_waitcnt vmcnt(0)
3333 define <4 x float> @image_load_mip(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
3434 main_body:
3737 }
3838
3939 ;CHECK-LABEL: {{^}}image_load_1:
40 ;CHECK: image_load v0, 1, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
40 ;CHECK: image_load v0, v[0:3], s[0:7] dmask:0x1 unorm
4141 ;CHECK: s_waitcnt vmcnt(0)
4242 define float @image_load_1(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
4343 main_body:
4848 }
4949
5050 ;CHECK-LABEL: {{^}}image_store_v4i32:
51 ;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:7], s[0:7]
51 ;CHECK: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm
5252 define void @image_store_v4i32(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 {
5353 main_body:
5454 call void @llvm.amdgcn.image.store.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
5656 }
5757
5858 ;CHECK-LABEL: {{^}}image_store_v2i32:
59 ;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:5], s[0:7]
59 ;CHECK: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm
6060 define void @image_store_v2i32(<8 x i32> inreg %rsrc, <4 x float> %data, <2 x i32> %coords) #0 {
6161 main_body:
6262 call void @llvm.amdgcn.image.store.v2i32(<4 x float> %data, <2 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
6464 }
6565
6666 ;CHECK-LABEL: {{^}}image_store_i32:
67 ;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[0:7]
67 ;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
6868 define void @image_store_i32(<8 x i32> inreg %rsrc, <4 x float> %data, i32 %coords) #0 {
6969 main_body:
7070 call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
7272 }
7373
7474 ;CHECK-LABEL: {{^}}image_store_mip:
75 ;CHECK: image_store_mip v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:7], s[0:7]
75 ;CHECK: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm
7676 define void @image_store_mip(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 {
7777 main_body:
7878 call void @llvm.amdgcn.image.store.mip.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
8282 ; Ideally, the register allocator would avoid the wait here
8383 ;
8484 ;CHECK-LABEL: {{^}}image_store_wait:
85 ;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[0:7]
85 ;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
8686 ;CHECK: s_waitcnt vmcnt(0) expcnt(0)
87 ;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[8:15]
87 ;CHECK: image_load v[0:3], v4, s[8:15] dmask:0xf unorm
8888 ;CHECK: s_waitcnt vmcnt(0)
89 ;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[16:23]
89 ;CHECK: image_store v[0:3], v4, s[16:23] dmask:0xf unorm
9090 define void @image_store_wait(<8 x i32> inreg, <8 x i32> inreg, <8 x i32> inreg, <4 x float>, i32) #0 {
9191 main_body:
9292 call void @llvm.amdgcn.image.store.i32(<4 x float> %3, i32 %4, <8 x i32> %0, i32 15, i1 0, i1 0, i1 0, i1 0)
363363
364364 ; Check the the resource descriptor is stored in an sgpr.
365365 ; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
366 ; CHECK: image_sample v{{[0-9]+}}, 1, 0, 0, 0, 0, 0, 0, 0, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
366 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
367367 define void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
368368 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
369369 %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
378378
379379 ; Check the the sampler is stored in an sgpr.
380380 ; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
381 ; CHECK: image_sample v{{[0-9]+}}, 1, 0, 0, 0, 0, 0, 0, 0, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
381 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
382382 define void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 {
383383 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
384384 %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
44 ; the wrong register class is used for the REG_SEQUENCE instructions.
55
66 ; CHECK: {{^}}main:
7 ; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, 15, 0, 0, 0, 0, 0, 0, 0, v{{\[[0-9]:[0-9]\]}}
7 ; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf
88 define void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
99 main_body:
1010 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
33 ; Make sure that when we split an smrd instruction in order to move it to
44 ; the VALU, we are also moving its users to the VALU.
55 ; CHECK-LABEL: {{^}}split_smrd_add_worklist:
6 ; CHECK: image_sample v{{[0-9]+}}, 1, 0, 0, 0, 0, 0, 0, 0, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
6 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
77
88 define void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
99 bb:
0 // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
1 // RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI
2 // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
3
4 image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm
5 // SICI: image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xed,0x04,0x07,0x00]
6 // VI: image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xed,0x04,0x07,0x00]
7
8 image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm
9 // SICI: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
10 // VI : image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
11
12 image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm
13 // SICI: image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x80,0xf0,0xed,0xc1,0x27,0x00]
14 // VI : image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x80,0xf0,0xed,0xc1,0x27,0x00]