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[NFC][InstCombine] Autogenerate a few tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366643 91177308-0d34-0410-b5e6-96231b3b80d8 Roman Lebedev a month ago
4 changed file(s) with 53 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
None ; RUN: opt < %s -instcombine -S | grep "i8 2, i8 2"
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt < %s -instcombine -S | FileCheck %s
12 ; PR2756
23
34 define <2 x i8> @foo(<2 x i8> %x) {
5 ; CHECK-LABEL: @foo(
6 ; CHECK-NEXT: [[A:%.*]] = srem <2 x i8> [[X:%.*]],
7 ; CHECK-NEXT: ret <2 x i8> [[A]]
8 ;
49 %A = srem <2 x i8> %x,
510 ret <2 x i8> %A
611 }
None ; RUN: opt < %s -instcombine -S | grep srem
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt < %s -instcombine -S | FileCheck %s
12 ; PR3439
23
34 define i32 @a(i32 %x) nounwind {
5 ; CHECK-LABEL: @a(
6 ; CHECK-NEXT: entry:
7 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[X:%.*]], 2
8 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[REM]], 2
9 ; CHECK-NEXT: ret i32 [[AND]]
10 ;
411 entry:
5 %rem = srem i32 %x, 2
6 %and = and i32 %rem, 2
7 ret i32 %and
12 %rem = srem i32 %x, 2
13 %and = and i32 %rem, 2
14 ret i32 %and
815 }
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt < %s -instcombine -S | FileCheck %s
12 ; PR6165
23
34 define i32 @f() {
5 ; CHECK-LABEL: @f(
6 ; CHECK-NEXT: entry:
7 ; CHECK-NEXT: br label [[BB1:%.*]]
8 ; CHECK: BB1:
9 ; CHECK-NEXT: [[X:%.*]] = phi i32 [ -29, [[ENTRY:%.*]] ], [ 0, [[BB1]] ]
10 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[X]], 2
11 ; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[REM]], -1
12 ; CHECK-NEXT: br i1 [[T]], label [[BB2:%.*]], label [[BB1]]
13 ; CHECK: BB2:
14 ; CHECK-NEXT: ret i32 [[X]]
15 ;
416 entry:
517 br label %BB1
618
719 BB1: ; preds = %BB1, %entry
8 ; CHECK: BB1:
920 %x = phi i32 [ -29, %entry ], [ 0, %BB1 ] ; [#uses=2]
1021 %rem = srem i32 %x, 2 ; [#uses=1]
1122 %t = icmp eq i32 %rem, -1 ; [#uses=1]
1223 br i1 %t, label %BB2, label %BB1
13 ; CHECK-NOT: br i1 false
1424
1525 BB2: ; preds = %BB1
16 ; CHECK: BB2:
1726 ret i32 %x
1827 }
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt < %s -instcombine -S | FileCheck %s
12 ; ModuleID = 'test/Transforms/InstCombine/add4.ll'
23 source_filename = "test/Transforms/InstCombine/add4.ll"
34
45 define i64 @match_unsigned(i64 %x) {
56 ; CHECK-LABEL: @match_unsigned(
6 ; CHECK-NEXT: bb:
7 ; CHECK-NEXT: bb:
78 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 19136
89 ; CHECK-NEXT: ret i64 [[UREM]]
910 ;
1819
1920 define i64 @match_andAsRem_lshrAsDiv_shlAsMul(i64 %x) {
2021 ; CHECK-LABEL: @match_andAsRem_lshrAsDiv_shlAsMul(
21 ; CHECK-NEXT: bb:
22 ; CHECK-NEXT: bb:
2223 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 576
2324 ; CHECK-NEXT: ret i64 [[UREM]]
2425 ;
3334
3435 define i64 @match_signed(i64 %x) {
3536 ; CHECK-LABEL: @match_signed(
36 ; CHECK-NEXT: bb:
37 ; CHECK-NEXT: bb:
3738 ; CHECK-NEXT: [[SREM1:%.*]] = srem i64 [[X:%.*]], 172224
3839 ; CHECK-NEXT: ret i64 [[SREM1]]
3940 ;
5253
5354 define i64 @not_match_inconsistent_signs(i64 %x) {
5455 ; CHECK-LABEL: @not_match_inconsistent_signs(
55 ; CHECK: [[TMP:%.*]] = add
56 ; CHECK-NEXT: ret i64 [[TMP]]
56 ; CHECK-NEXT: bb:
57 ; CHECK-NEXT: [[TMP:%.*]] = urem i64 [[X:%.*]], 299
58 ; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[X]], 299
59 ; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], 63
60 ; CHECK-NEXT: [[TMP3:%.*]] = mul nuw nsw i64 [[TMP2]], 299
61 ; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP]], [[TMP3]]
62 ; CHECK-NEXT: ret i64 [[TMP4]]
5763 ;
5864 bb:
5965 %tmp = urem i64 %x, 299
6672
6773 define i64 @not_match_inconsistent_values(i64 %x) {
6874 ; CHECK-LABEL: @not_match_inconsistent_values(
69 ; CHECK: [[TMP:%.*]] = add
70 ; CHECK-NEXT: ret i64 [[TMP]]
75 ; CHECK-NEXT: bb:
76 ; CHECK-NEXT: [[TMP:%.*]] = urem i64 [[X:%.*]], 299
77 ; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[X]], 29
78 ; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], 63
79 ; CHECK-NEXT: [[TMP3:%.*]] = mul nuw nsw i64 [[TMP2]], 299
80 ; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP]], [[TMP3]]
81 ; CHECK-NEXT: ret i64 [[TMP4]]
7182 ;
7283 bb:
7384 %tmp = urem i64 %x, 299
8091
8192 define i32 @not_match_overflow(i32 %x) {
8293 ; CHECK-LABEL: @not_match_overflow(
83 ; CHECK: [[TMP:%.*]] = add
84 ; CHECK-NEXT: ret i32 [[TMP]]
94 ; CHECK-NEXT: bb:
95 ; CHECK-NEXT: [[TMP:%.*]] = urem i32 [[X:%.*]], 299
96 ; CHECK-NEXT: [[TMP0:%.*]] = urem i32 [[X]], 299
97 ; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[X]], [[TMP0]]
98 ; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP]], [[TMP3]]
99 ; CHECK-NEXT: ret i32 [[TMP4]]
85100 ;
86101 bb:
87102 %tmp = urem i32 %x, 299