llvm.org GIT mirror llvm / 1b54c7f
Pass MemOperand through for 64-bit atomics on 32-bit, incidentally making the case where the memop is a pointer deref work. Fix cmp-and-swap regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57027 91177308-0d34-0410-b5e6-96231b3b80d8 Dale Johannesen 12 years ago
4 changed file(s) with 27 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
62116211 break;
62126212 }
62136213
6214 case ISD::ATOMIC_CMP_SWAP_64: {
6215 // This operation does not need a loop.
6216 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6217 assert(Tmp.getNode() && "Node must be custom expanded!");
6218 ExpandOp(Tmp.getValue(0), Lo, Hi);
6219 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6220 LegalizeOp(Tmp.getValue(1)));
6221 break;
6222 }
6223
62146224 case ISD::ATOMIC_LOAD_ADD_64:
62156225 case ISD::ATOMIC_LOAD_SUB_64:
62166226 case ISD::ATOMIC_LOAD_AND_64:
62176227 case ISD::ATOMIC_LOAD_OR_64:
62186228 case ISD::ATOMIC_LOAD_XOR_64:
62196229 case ISD::ATOMIC_LOAD_NAND_64:
6220 case ISD::ATOMIC_SWAP_64:
6221 case ISD::ATOMIC_CMP_SWAP_64: {
6230 case ISD::ATOMIC_SWAP_64: {
6231 // These operations require a loop to be generated. We can't do that yet,
6232 // so substitute a target-dependent pseudo and expand that later.
62226233 SDValue In2Lo, In2Hi, In2;
62236234 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
62246235 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6225 SDValue Result = TLI.LowerOperation(
6226 DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), Op.getOperand(1), In2),
6227 DAG);
6236 AtomicSDNode* Anode = cast(Node);
6237 SDValue Replace =
6238 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
6239 Anode->getSrcValue(), Anode->getAlignment());
6240 SDValue Result = TLI.LowerOperation(Replace, DAG);
62286241 ExpandOp(Result.getValue(0), Lo, Hi);
62296242 // Remember that we legalized the chain.
62306243 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
12081208 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
12091209 if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
12101210 return NULL;
1211 SDValue LSI = Node->getOperand(4); // MemOperand
12111212 AddToISelQueue(Tmp0);
12121213 AddToISelQueue(Tmp1);
12131214 AddToISelQueue(Tmp2);
12141215 AddToISelQueue(Tmp3);
12151216 AddToISelQueue(In2L);
12161217 AddToISelQueue(In2H);
1218 // For now, don't select the MemOperand object, we don't know how.
12171219 AddToISelQueue(Chain);
1218 SDValue LSI = CurDAG->getMemOperand(cast(In1)->getMemOperand());
12191220 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
12201221 return CurDAG->getTargetNode(Opc, MVT::i32, MVT::i32, MVT::Other, Ops, 8);
12211222 }
60256025 assert(Node->getOperand(2).getNode()->getOpcode()==ISD::BUILD_PAIR);
60266026 SDValue In2L = Node->getOperand(2).getNode()->getOperand(0);
60276027 SDValue In2H = Node->getOperand(2).getNode()->getOperand(1);
6028 SDValue Ops[] = { Chain, In1, In2L, In2H };
6028 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6029 // have a MemOperand. Pass the info through as a normal operand.
6030 SDValue LSI = DAG.getMemOperand(cast(Node)->getMemOperand());
6031 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
60296032 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6030 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 4);
6033 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
60316034 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
60326035 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
60336036 SDValue Vals[2] = { ResultVal, Result.getValue(2) };
64146417 return nextMBB;
64156418 }
64166419
6417 // private utility function
6420 // private utility function: 64 bit atomics on 32 bit host.
64186421 MachineBasicBlock *
64196422 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
64206423 MachineBasicBlock *MBB,
27512751 let Constraints = "$val1 = $dst1, $val2 = $dst2",
27522752 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
27532753 Uses = [EAX, EBX, ECX, EDX],
2754 mayLoad = 1, mayStore = 1,
27542755 usesCustomDAGSchedInserter = 1 in {
27552756 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
27562757 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),