llvm.org GIT mirror llvm / 1b19ef0
Note that ADDC and company don't actually expand yet (missing in legalize git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57226 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Lenharth 12 years ago
4 changed file(s) with 65 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
359359 include "llvm/IntrinsicsX86.td"
360360 include "llvm/IntrinsicsARM.td"
361361 include "llvm/IntrinsicsCellSPU.td"
362 include "llvm/IntrinsicsAlpha.td"
0 //===- IntrinsicsAlpha.td - Defines Alpha intrinsics -------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines all of the Alpha-specific intrinsics.
10 //
11 //===----------------------------------------------------------------------===//
12
13
14 let TargetPrefix = "alpha" in { // All intrinsics start with "llvm.alpha.".
15 def int_alpha_umulh : GCCBuiltin<"__builtin_alpha_umulh">,
16 Intrinsic<[llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
17
18 }
322322 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
323323 CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
324324 }
325 case ISD::TargetConstantFP: {
325 case ISD::TargetConstantFP:
326 case ISD::ConstantFP: {
326327 ConstantFPSDNode *CN = cast(N);
327328 bool isDouble = N->getValueType(0) == MVT::f64;
328329 MVT T = isDouble ? MVT::f64 : MVT::f32;
2121 #include "llvm/Constants.h"
2222 #include "llvm/Function.h"
2323 #include "llvm/Module.h"
24 #include "llvm/Intrinsics.h"
2425 #include "llvm/Support/CommandLine.h"
2526 using namespace llvm;
2627
4647 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
4748 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
4849 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
49
50
51 // We want to custom lower some of our intrinsics.
52 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
53
5054 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
5155 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
5256
8589 setOperationAction(ISD::UREM , MVT::i64, Custom);
8690 setOperationAction(ISD::SDIV , MVT::i64, Custom);
8791 setOperationAction(ISD::UDIV , MVT::i64, Custom);
92
93 setOperationAction(ISD::ADDC , MVT::i64, Expand);
94 setOperationAction(ISD::ADDE , MVT::i64, Expand);
95 setOperationAction(ISD::SUBC , MVT::i64, Expand);
96 setOperationAction(ISD::SUBE , MVT::i64, Expand);
97
8898
8999 // We don't support sin/cos/sqrt/pow
90100 setOperationAction(ISD::FSIN , MVT::f64, Expand);
308318 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
309319 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
310320 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
321 break;
322 }
323 case 5: {
324 MVT ArgVT = Op.getOperand(1).getValueType();
325 unsigned ArgReg1, ArgReg2;
326 if (ArgVT.isInteger()) {
327 ArgReg1 = Alpha::R0;
328 ArgReg2 = Alpha::R1;
329 } else {
330 assert(ArgVT.isFloatingPoint());
331 ArgReg1 = Alpha::F0;
332 ArgReg2 = Alpha::F1;
333 }
334 Copy = DAG.getCopyToReg(Copy, ArgReg1, Op.getOperand(1), Copy.getValue(1));
335 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
336 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
337 == DAG.getMachineFunction().getRegInfo().liveout_end())
338 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
339 Copy = DAG.getCopyToReg(Copy, ArgReg2, Op.getOperand(3), Copy.getValue(1));
340 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
341 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
342 == DAG.getMachineFunction().getRegInfo().liveout_end())
343 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
311344 break;
312345 }
313346 }
430463
431464 case ISD::RET: return LowerRET(Op,DAG);
432465 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
466
467 case ISD::INTRINSIC_WO_CHAIN: {
468 unsigned IntNo = cast(Op.getOperand(0))->getZExtValue();
469 switch (IntNo) {
470 default: break; // Don't custom lower most intrinsics.
471 case Intrinsic::alpha_umulh:
472 return DAG.getNode(ISD::MULHU, MVT::i64, Op.getOperand(1), Op.getOperand(2));
473 }
474 }
433475
434476 case ISD::SINT_TO_FP: {
435477 assert(Op.getOperand(0).getValueType() == MVT::i64 &&