llvm.org GIT mirror llvm / 1b133a4
Extract a function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179086 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
1 changed file(s) with 17 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
146146 }
147147
148148 #include "SparcGenCallingConv.inc"
149
150 // The calling conventions in SparcCallingConv.td are described in terms of the
151 // callee's register window. This function translates registers to the
152 // corresponding caller window %o register.
153 static unsigned toCallerWindow(unsigned Reg) {
154 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
155 if (Reg >= SP::I0 && Reg <= SP::I7)
156 return Reg - SP::I0 + SP::O0;
157 return Reg;
158 }
149159
150160 SDValue
151161 SparcTargetLowering::LowerReturn(SDValue Chain,
804814 // stuck together.
805815 SDValue InFlag;
806816 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
807 unsigned Reg = RegsToPass[i].first;
808 // Remap I0->I7 -> O0->O7.
809 if (Reg >= SP::I0 && Reg <= SP::I7)
810 Reg = Reg-SP::I0+SP::O0;
811
817 unsigned Reg = toCallerWindow(RegsToPass[i].first);
812818 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
813819 InFlag = Chain.getValue(1);
814820 }
830836 Ops.push_back(Callee);
831837 if (hasStructRetAttr)
832838 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
833 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
834 unsigned Reg = RegsToPass[i].first;
835 if (Reg >= SP::I0 && Reg <= SP::I7)
836 Reg = Reg-SP::I0+SP::O0;
837
838 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
839 }
839 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
840 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
841 RegsToPass[i].second.getValueType()));
840842 if (InFlag.getNode())
841843 Ops.push_back(InFlag);
842844
856858
857859 // Copy all of the result registers out of their specified physreg.
858860 for (unsigned i = 0; i != RVLocs.size(); ++i) {
859 unsigned Reg = RVLocs[i].getLocReg();
860
861 // Remap I0->I7 -> O0->O7.
862 if (Reg >= SP::I0 && Reg <= SP::I7)
863 Reg = Reg-SP::I0+SP::O0;
864
865 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
861 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
866862 RVLocs[i].getValVT(), InFlag).getValue(1);
867863 InFlag = Chain.getValue(2);
868864 InVals.push_back(Chain.getValue(0));
975971 ++i;
976972 }
977973 }
978
979 // The argument registers are described in term of the callee's register
980 // window, so translate I0-I7 -> O0-O7.
981 unsigned Reg = VA.getLocReg();
982 if (Reg >= SP::I0 && Reg <= SP::I7)
983 Reg = Reg - SP::I0 + SP::O0;
984 RegsToPass.push_back(std::make_pair(Reg, Arg));
974 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
985975 continue;
986976 }
987977
10601050 // Copy all of the result registers out of their specified physreg.
10611051 for (unsigned i = 0; i != RVLocs.size(); ++i) {
10621052 CCValAssign &VA = RVLocs[i];
1063 unsigned Reg = VA.getLocReg();
1064
1065 // Remap I0-I7 -> O0-O7.
1066 if (Reg >= SP::I0 && Reg <= SP::I7)
1067 Reg = Reg - SP::I0 + SP::O0;
1053 unsigned Reg = toCallerWindow(VA.getLocReg());
10681054
10691055 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
10701056 // reside in the same register in the high and low bits. Reuse the