llvm.org GIT mirror llvm / 1b051fc
Start making use of RegScavenger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34708 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
1 changed file(s) with 12 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
8484 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
8585 TII(tii), STI(sti),
8686 FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
87 RS = new RegScavenger();
87 RS = (EnableScavenging) ? new RegScavenger() : NULL;
8888 }
8989
9090 ARMRegisterInfo::~ARMRegisterInfo() {
9191 delete RS;
92 }
93
94 RegScavenger *ARMRegisterInfo::getRegScavenger() const {
95 return EnableScavenging ? RS : NULL;
9692 }
9793
9894 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
329325 return Reserved;
330326 }
331327
328 bool ARMRegisterInfo::requiresRegisterScavenging() const {
329 return EnableScavenging;
330 }
331
332332 /// hasFP - Return true if the specified function should have a dedicated frame
333333 /// pointer register. This is true if the function has variable sized allocas
334334 /// or if frame pointer elimination is disabled.
615615 .addReg(DestReg, false, false, true);
616616 }
617617
618 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
618 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
619 RegScavenger *RS) const{
619620 unsigned i = 0;
620621 MachineInstr &MI = *II;
621622 MachineBasicBlock &MBB = *MI.getParent();
897898 // If the offset we have is too large to fit into the instruction, we need
898899 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
899900 // out of 'Offset'.
900 emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg,
901 unsigned ScratchReg = RS
902 ? RS->FindUnusedReg(&ARM::GPRRegClass, true) : (unsigned)ARM::R12;
903 assert(ScratchReg != 0 && "Unable to find a free call-clobbered register!");
904 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
901905 isSub ? -Offset : Offset, TII);
902 MI.getOperand(i).ChangeToRegister(ARM::R12, false, false, true);
906 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
903907 }
904908 }
905909