llvm.org GIT mirror llvm / 1adc40c
Cleaned up the for-disassembly-only entries in the arm instruction table so that the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8 Johnny Chen 10 years ago
8 changed file(s) with 75 addition(s) and 49 deletion(s). Raw diff Collapse all Expand all
8989 }
9090 }
9191
92 namespace ARM_MB {
93 // The Memory Barrier Option constants map directly to the 4-bit encoding of
94 // the option field for memory barrier operations.
95 enum MemBOpt {
96 ST = 14,
97 ISH = 11,
98 ISHST = 10,
99 NSH = 7,
100 NSHST = 6,
101 OSH = 3,
102 OSHST = 2
103 };
104
105 inline static const char *MemBOptToString(unsigned val) {
106 switch (val) {
107 default: llvm_unreachable("Unknown memory opetion");
108 case ST: return "st";
109 case ISH: return "ish";
110 case ISHST: return "ishst";
111 case NSH: return "nsh";
112 case NSHST: return "nshst";
113 case OSH: return "osh";
114 case OSHST: return "oshst";
115 }
116 }
117 } // namespace ARM_MB
118
92119 FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
93120 CodeGenOpt::Level OptLevel);
94121
121121 const char *Modifier = 0);
122122 void printBitfieldInvMaskImmOperand(const MachineInstr *MI, int OpNum,
123123 raw_ostream &O);
124 void printMemBOption(const MachineInstr *MI, int OpNum,
125 raw_ostream &O);
124126 void printSatShiftOperand(const MachineInstr *MI, int OpNum,
125127 raw_ostream &O);
126128
668670 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
669671 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
670672 O << "#" << lsb << ", #" << width;
673 }
674
675 void
676 ARMAsmPrinter::printMemBOption(const MachineInstr *MI, int OpNum,
677 raw_ostream &O) {
678 unsigned val = MI->getOperand(OpNum).getImm();
679 O << ARM_MB::MemBOptToString(val);
671680 }
672681
673682 void ARMAsmPrinter::printSatShiftOperand(const MachineInstr *MI, int OpNum,
23882388 }
23892389 }
23902390
2391 // Helper class for multiclass MemB -- for disassembly only
2392 class AMBI
2393 : AInoP<(outs), (ins), MiscFrm, NoItinerary, opc, asm,
2391 // Memory Barrier Operations Variants -- for disassembly only
2392
2393 def memb_opt : Operand {
2394 let PrintMethod = "printMemBOption";
2395 }
2396
2397 class AMBI op7_4, string opc>
2398 : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, opc, "\t$opt",
23942399 [/* For disassembly only; pattern left blank */]>,
2395 Requires<[IsARM, HasV7]> {
2396 let Inst{31-20} = 0xf57;
2397 }
2398
2399 multiclass MemB op7_4, string opc> {
2400
2401 def st : AMBI {
2402 let Inst{7-4} = op7_4;
2403 let Inst{3-0} = 0b1110;
2404 }
2405
2406 def ish : AMBI {
2407 let Inst{7-4} = op7_4;
2408 let Inst{3-0} = 0b1011;
2409 }
2410
2411 def ishst : AMBI {
2412 let Inst{7-4} = op7_4;
2413 let Inst{3-0} = 0b1010;
2414 }
2415
2416 def nsh : AMBI {
2417 let Inst{7-4} = op7_4;
2418 let Inst{3-0} = 0b0111;
2419 }
2420
2421 def nshst : AMBI {
2422 let Inst{7-4} = op7_4;
2423 let Inst{3-0} = 0b0110;
2424 }
2425
2426 def osh : AMBI {
2427 let Inst{7-4} = op7_4;
2428 let Inst{3-0} = 0b0011;
2429 }
2430
2431 def oshst : AMBI {
2432 let Inst{7-4} = op7_4;
2433 let Inst{3-0} = 0b0010;
2434 }
2400 Requires<[IsARM, HasDB]> {
2401 let Inst{31-8} = 0xf57ff0;
2402 let Inst{7-4} = op7_4;
24352403 }
24362404
24372405 // These DMB variants are for disassembly only.
2438 defm DMB : MemB<0b0101, "dmb">;
2406 def DMBvar : AMBI<0b0101, "dmb">;
24392407
24402408 // These DSB variants are for disassembly only.
2441 defm DSB : MemB<0b0100, "dsb">;
2409 def DSBvar : AMBI<0b0100, "dsb">;
24422410
24432411 // ISB has only full system option -- for disassembly only
2444 def ISBsy : AMBI<"isb", ""> {
2445 let Inst{7-4} = 0b0110;
2412 def ISBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2413 Requires<[IsARM, HasDB]> {
2414 let Inst{31-4} = 0xf57ff06;
24462415 let Inst{3-0} = 0b1111;
24472416 }
24482417
471471 O << '#' << lsb << ", #" << width;
472472 }
473473
474 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
475 raw_ostream &O) {
476 unsigned val = MI->getOperand(OpNum).getImm();
477 O << ARM_MB::MemBOptToString(val);
478 }
479
474480 void ARMInstPrinter::printSatShiftOperand(const MCInst *MI, unsigned OpNum,
475481 raw_ostream &O) {
476482 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
5656
5757 void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum,
5858 raw_ostream &O);
59 void printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
5960 void printSatShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
6061
6162 void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
29342934 // A8.6.49 ISB
29352935 static inline bool MemBarrierInstr(uint32_t insn) {
29362936 unsigned op7_4 = slice(insn, 7, 4);
2937 if (slice(insn, 31, 20) == 0xf57 && (op7_4 >= 4 && op7_4 <= 6))
2937 if (slice(insn, 31, 8) == 0xf57ff0 && (op7_4 >= 4 && op7_4 <= 6))
29382938 return true;
29392939
29402940 return false;
29912991 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
29922992 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
29932993
2994 if (MemBarrierInstr(insn))
2994 if (MemBarrierInstr(insn)) {
2995 // DMBsy, DSBsy, and ISBsy instructions have zero operand and are taken care
2996 // of within the generic ARMBasicMCBuilder::BuildIt() method.
2997 //
2998 // Inst{3-0} encodes the memory barrier option for the variants.
2999 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
3000 NumOpsAdded = 1;
29953001 return true;
3002 }
29963003
29973004 switch (Opcode) {
29983005 case ARM::CLREX:
1919
2020 # CHECK: dsb
2121 0x4f 0xf0 0x7f 0xf5
22
23 # CHECK: dsb st
24 0x4e 0xf0 0x7f 0xf5
25
26 # CHECK: isb
27 0x6f 0xf0 0x7f 0xf5
2228
2329 # CHECK: ldclvc p5, cr15, [r8], #-0
2430 0x00 0xf5 0x78 0x7c
598598 IMM("cps_opt");
599599 IMM("vfp_f64imm");
600600 IMM("vfp_f32imm");
601 IMM("memb_opt");
601602 IMM("msr_mask");
602603 IMM("neg_zero");
603604 IMM("imm0_31");