llvm.org GIT mirror llvm / 1ab7989
Avoid storing and reloading zeros and other constants from stack slots by flagging the associated instructions as being trivially rematerializable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41775 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 13 years ago
4 changed file(s) with 22 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
23122312
23132313 // Alias instructions that map movr0 to xor.
23142314 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2315 let isReMaterializable = 1 in {
23152316 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
23162317 "xor{b}\t$dst, $dst",
23172318 [(set GR8:$dst, 0)]>;
23212322 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
23222323 "xor{l}\t$dst, $dst",
23232324 [(set GR32:$dst, 0)]>;
2325 }
23242326
23252327 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
23262328 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
398398 // start with 'Fs'.
399399
400400 // Alias instructions that map fld0 to pxor for sse.
401 let isReMaterializable = 1 in
401402 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
402403 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
403404 Requires<[HasSSE1]>, TB, OpSize;
10621063 // start with 'Fs'.
10631064
10641065 // Alias instructions that map fld0 to pxor for sse.
1066 let isReMaterializable = 1 in
10651067 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
10661068 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
10671069 Requires<[HasSSE2]>, TB, OpSize;
155155 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
156156 "mov{q}\t{$src, $dst|$dst, $src}", []>;
157157
158 let isReMaterializable = 1 in {
158159 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
159160 "movabs{q}\t{$src, $dst|$dst, $src}",
160161 [(set GR64:$dst, imm:$src)]>;
161162 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
162163 "mov{q}\t{$src, $dst|$dst, $src}",
163164 [(set GR64:$dst, i64immSExt32:$src)]>;
165 }
164166
165167 let isLoad = 1 in
166168 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
989991 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
990992 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
991993 // when we have a better way to specify isel priority.
992 let AddedComplexity = 1 in
994 let AddedComplexity = 1, isReMaterializable = 1 in
993995 def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins),
994996 "xor{q}\t$dst, $dst",
995997 [(set GR64:$dst, 0)]>;
996998
997999 // Materialize i64 constant where top 32-bits are zero.
998 let AddedComplexity = 1 in
1000 let AddedComplexity = 1, isReMaterializable = 1 in
9991001 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
10001002 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
10011003 [(set GR64:$dst, i64immZExt32:$src)]>;
0 ; RUN: llvm-as < %s | llc -march=x86-64 | grep xor | count 4
1 ; RUN: llvm-as < %s | llc -march=x86-64 -stats -info-output-file - | grep asm-printer | grep 12
2
3 declare void @bar(double %x)
4 declare void @barf(float %x)
5
6 define double @foo() {
7 call void @bar(double 0.0)
8 ret double 0.0
9 }
10 define float @foof() {
11 call void @barf(float 0.0)
12 ret float 0.0
13 }