llvm.org GIT mirror llvm / 1a6ed75
[esan|wset] Fix incorrect memory size assert Summary: Fixes an incorrect assert that fails on 128-bit-sized loads or stores. Augments the wset tests to include this case. Reviewers: aizatsky Subscribers: vitalybuka, zhaoqin, kcc, eugenis, llvm-commits Differential Revision: http://reviews.llvm.org/D22062 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274666 91177308-0d34-0410-b5e6-96231b3b80d8 Derek Bruening 4 years ago
3 changed file(s) with 75 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
670670 NumFastpaths++;
671671 return true;
672672 }
673 if (Alignment == 0 || Alignment >= 8 || (Alignment % TypeSizeBytes) == 0)
673 if (Alignment == 0 || (Alignment % TypeSizeBytes) == 0)
674674 OnAccessFunc = IsStore ? EsanAlignedStore[Idx] : EsanAlignedLoad[Idx];
675675 else
676676 OnAccessFunc = IsStore ? EsanUnalignedStore[Idx] : EsanUnalignedLoad[Idx];
831831 // getMemoryAccessFuncIndex has already ruled out a size larger than 16
832832 // and thus larger than a cache line for platforms this tool targets
833833 // (and our shadow memory setup assumes 64-byte cache lines).
834 assert(TypeSize <= 64);
834 assert(TypeSize <= 128);
835835 if (!(TypeSize == 8 ||
836836 (Alignment % (TypeSize / 8)) == 0)) {
837837 if (ClAssumeIntraCacheLine)
8989 ; CHECK-NEXT: ret i64 %tmp1
9090 }
9191
92 define i128 @aligned16(i128* %a) {
93 entry:
94 %tmp1 = load i128, i128* %a, align 16
95 ret i128 %tmp1
96 ; CHECK: %0 = ptrtoint i128* %a to i64
97 ; CHECK-NEXT: %1 = and i64 %0, 17592186044415
98 ; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
99 ; CHECK-NEXT: %3 = lshr i64 %2, 6
100 ; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
101 ; CHECK-NEXT: %5 = load i8, i8* %4
102 ; CHECK-NEXT: %6 = and i8 %5, -127
103 ; CHECK-NEXT: %7 = icmp ne i8 %6, -127
104 ; CHECK-NEXT: br i1 %7, label %8, label %11
105 ; CHECK: %9 = or i8 %5, -127
106 ; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
107 ; CHECK-NEXT: store i8 %9, i8* %10
108 ; CHECK-NEXT: br label %11
109 ; CHECK: %tmp1 = load i128, i128* %a, align 16
110 ; CHECK-NEXT: ret i128 %tmp1
111 }
112
92113 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
93114 ; Not guaranteed to be intra-cache-line, but our defaults are to
94115 ; assume they are:
154175 ; CHECK-NEXT: br label %11
155176 ; CHECK: %tmp1 = load i64, i64* %a, align 4
156177 ; CHECK-NEXT: ret i64 %tmp1
178 }
179
180 define i128 @unaligned16(i128* %a) {
181 entry:
182 %tmp1 = load i128, i128* %a, align 8
183 ret i128 %tmp1
184 ; CHECK: %0 = ptrtoint i128* %a to i64
185 ; CHECK-NEXT: %1 = and i64 %0, 17592186044415
186 ; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
187 ; CHECK-NEXT: %3 = lshr i64 %2, 6
188 ; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
189 ; CHECK-NEXT: %5 = load i8, i8* %4
190 ; CHECK-NEXT: %6 = and i8 %5, -127
191 ; CHECK-NEXT: %7 = icmp ne i8 %6, -127
192 ; CHECK-NEXT: br i1 %7, label %8, label %11
193 ; CHECK: %9 = or i8 %5, -127
194 ; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
195 ; CHECK-NEXT: store i8 %9, i8* %10
196 ; CHECK-NEXT: br label %11
197 ; CHECK: %tmp1 = load i128, i128* %a, align 8
198 ; CHECK-NEXT: ret i128 %tmp1
157199 }
158200
159201 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9090 ; CHECK-NEXT: ret i64 %tmp1
9191 }
9292
93 define i128 @aligned16(i128* %a) {
94 entry:
95 %tmp1 = load i128, i128* %a, align 16
96 ret i128 %tmp1
97 ; CHECK: %0 = ptrtoint i128* %a to i64
98 ; CHECK-NEXT: %1 = and i64 %0, 17592186044415
99 ; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
100 ; CHECK-NEXT: %3 = lshr i64 %2, 6
101 ; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
102 ; CHECK-NEXT: %5 = load i8, i8* %4
103 ; CHECK-NEXT: %6 = and i8 %5, -127
104 ; CHECK-NEXT: %7 = icmp ne i8 %6, -127
105 ; CHECK-NEXT: br i1 %7, label %8, label %11
106 ; CHECK: %9 = or i8 %5, -127
107 ; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
108 ; CHECK-NEXT: store i8 %9, i8* %10
109 ; CHECK-NEXT: br label %11
110 ; CHECK: %tmp1 = load i128, i128* %a, align 16
111 ; CHECK-NEXT: ret i128 %tmp1
112 }
113
93114 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
94115 ; Not guaranteed to be intra-cache-line
95116
122143 ; CHECK-NEXT: %tmp1 = load i64, i64* %a, align 4
123144 ; CHECK-NEXT: ret i64 %tmp1
124145 }
146
147 define i128 @unaligned16(i128* %a) {
148 entry:
149 %tmp1 = load i128, i128* %a, align 8
150 ret i128 %tmp1
151 ; CHECK: %0 = bitcast i128* %a to i8*
152 ; CHECK-NEXT: call void @__esan_unaligned_load16(i8* %0)
153 ; CHECK-NEXT: %tmp1 = load i128, i128* %a, align 8
154 ; CHECK-NEXT: ret i128 %tmp1
155 }