llvm.org GIT mirror llvm / 1a4e1d8
Merging r281479: ------------------------------------------------------------------------ r281479 | nemanja.i.ibm | 2016-09-14 07:19:09 -0700 (Wed, 14 Sep 2016) | 9 lines Fix code-gen crash on Power9 for insert_vector_elt with variable index (PR30189) This patch corresponds to review: https://reviews.llvm.org/D24021 In the initial implementation of this instruction, I forgot to account for variable indices. This patch fixes PR30189 and should probably be merged into 3.9.1 (I'll open a bug according to the new instructions). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@287809 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
3 changed file(s) with 38 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
664664 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
665665 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
666666 }
667
667668 if (Subtarget.hasP9Vector()) {
668 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
669 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Legal);
669 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
670 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
670671 }
671672 }
672673
78457846 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo());
78467847 }
78477848
7849 SDValue PPCTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
7850 SelectionDAG &DAG) const {
7851 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&
7852 "Should only be called for ISD::INSERT_VECTOR_ELT");
7853 ConstantSDNode *C = dyn_cast(Op.getOperand(2));
7854 // We have legal lowering for constant indices but not for variable ones.
7855 if (C)
7856 return Op;
7857 return SDValue();
7858 }
7859
78487860 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
78497861 SelectionDAG &DAG) const {
78507862 SDLoc dl(Op);
82478259 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
82488260 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
82498261 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8262 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
82508263 case ISD::MUL: return LowerMUL(Op, DAG);
82518264
82528265 // For counter-based loop handling.
823823 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
824824 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
825825 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
826827 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
827828 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
828829 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
967967 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32>
968968 ret <4 x float> %vecins
969969 }
970 define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {
971 entry:
972 ; CHECK-LABEL: insertVarF
973 ; CHECK: stxsspx 1,
974 ; CHECK: lxvd2x
975 ; CHECK-BE-LABEL: insertVarF
976 ; CHECK-BE: stxsspx 1,
977 ; CHECK-BE: lxvw4x
978 %vecins = insertelement <4 x float> %a, float %f, i32 %el
979 ret <4 x float> %vecins
980 }
981 define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {
982 entry:
983 ; CHECK-LABEL: insertVarI
984 ; CHECK: stwx
985 ; CHECK: lxvd2x
986 ; CHECK-BE-LABEL: insertVarI
987 ; CHECK-BE: stwx
988 ; CHECK-BE: lxvw4x
989 %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el
990 ret <4 x i32> %vecins
991 }