llvm.org GIT mirror llvm / 1a08936
[Hexagon] Add a target feature for memop generation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332285 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 1 year, 5 months ago
5 changed file(s) with 55 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
4747 "Use constant-extended calls">;
4848 def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
4949 "Supports mem_noshuf feature">;
50 def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true",
51 "Use memop instructions">;
5052 def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",
5153 "Support for new-value jumps", [FeaturePackets]>;
5254 def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
5860 // Hexagon Instruction Predicate Definitions.
5961 //===----------------------------------------------------------------------===//
6062
61 def UseMEMOP : Predicate<"HST->useMemOps()">;
63 def UseMEMOPS : Predicate<"HST->useMemops()">;
6264 def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;
6365 def UseHVX64B : Predicate<"HST->useHVX64BOps()">,
6466 AssemblerPredicate<"ExtensionHVX64B">;
317319 : ProcessorModel;
318320
319321 def : Proc<"hexagonv4", HexagonModelV4,
320 [ArchV4, FeaturePackets, FeatureNVJ, FeatureDuplex]>;
322 [ArchV4,
323 FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>;
321324 def : Proc<"hexagonv5", HexagonModelV4,
322 [ArchV4, ArchV5, FeaturePackets, FeatureNVJ, FeatureDuplex]>;
325 [ArchV4, ArchV5,
326 FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>;
323327 def : Proc<"hexagonv55", HexagonModelV55,
324 [ArchV4, ArchV5, ArchV55, FeaturePackets, FeatureNVJ,
325 FeatureDuplex]>;
328 [ArchV4, ArchV5, ArchV55,
329 FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>;
326330 def : Proc<"hexagonv60", HexagonModelV60,
327 [ArchV4, ArchV5, ArchV55, ArchV60, FeaturePackets, FeatureNVJ,
328 FeatureDuplex]>;
331 [ArchV4, ArchV5, ArchV55, ArchV60,
332 FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>;
329333 def : Proc<"hexagonv62", HexagonModelV62,
330 [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeaturePackets,
331 FeatureNVJ, FeatureDuplex]>;
334 [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62,
335 FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>;
332336 def : Proc<"hexagonv65", HexagonModelV65,
333337 [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
334 FeatureMemNoShuf, FeaturePackets, FeatureNVJ, FeatureDuplex]>;
338 FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
339 FeaturePackets]>;
335340
336341 //===----------------------------------------------------------------------===//
337342 // Declare the target which we are implementing
25802580
25812581 multiclass Memopxr_pat
25822582 SDNode Oper, InstHexagon MI> {
2583 defm: Memopxr_base_pat ;
2584 defm: Memopxr_add_pat ;
2583 let Predicates = [UseMEMOPS] in {
2584 defm: Memopxr_base_pat ;
2585 defm: Memopxr_add_pat ;
2586 }
25852587 }
25862588
25872589 let AddedComplexity = 200 in {
26792681 multiclass Memopxi_pat
26802682 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod,
26812683 InstHexagon MI> {
2682 defm: Memopxi_base_pat ;
2683 defm: Memopxi_add_pat ;
2684 let Predicates = [UseMEMOPS] in {
2685 defm: Memopxi_base_pat ;
2686 defm: Memopxi_add_pat ;
2687 }
26842688 }
26852689
26862690 let AddedComplexity = 220 in {
3838 #define GET_SUBTARGETINFO_TARGET_DESC
3939 #include "HexagonGenSubtargetInfo.inc"
4040
41 static cl::opt EnableMemOps("enable-hexagon-memops",
42 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
43 cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
44
45 static cl::opt DisableMemOps("disable-hexagon-memops",
46 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
47 cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"));
4841
4942 static cl::opt EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
5043 cl::Hidden, cl::ZeroOrMore, cl::init(false),
5952 static cl::opt EnableDotCurSched("enable-cur-sched",
6053 cl::Hidden, cl::ZeroOrMore, cl::init(true),
6154 cl::desc("Enable the scheduler to generate .cur"));
62
63 static cl::opt EnableVecFrwdSched("enable-evec-frwd-sched",
64 cl::Hidden, cl::ZeroOrMore, cl::init(true));
6555
6656 static cl::opt DisableHexagonMISched("disable-hexagon-misched",
6757 cl::Hidden, cl::ZeroOrMore, cl::init(false),
123113 UseHVX64BOps = false;
124114 UseLongCalls = false;
125115
126 UseMemOps = DisableMemOps ? false : EnableMemOps;
127116 ModeIEEERndNear = EnableIEEERndNear;
128117 UseBSBScheduling = hasV60TOps() && EnableBSBSched;
129118
4545 class HexagonSubtarget : public HexagonGenSubtargetInfo {
4646 virtual void anchor();
4747
48 bool UseMemOps, UseHVX64BOps, UseHVX128BOps;
49 bool UseLongCalls;
48 bool UseHVX64BOps = false;
49 bool UseHVX128BOps = false;
50 bool ModeIEEERndNear = false;
51
52 bool UseLongCalls = false;
53 bool UseMemops = false;
5054 bool UsePackets = false;
5155 bool UseNewValueJumps = false;
52 bool ModeIEEERndNear;
5356
5457 bool HasMemNoShuf = false;
5558 bool EnableDuplex = false;
118121 /// subtarget options. Definition of function is auto generated by tblgen.
119122 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
120123
121 bool useMemOps() const { return UseMemOps; }
122124 bool hasV5TOps() const {
123125 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
124126 }
149151 bool hasV65TOpsOnly() const {
150152 return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
151153 }
154 bool useMemops() const { return UseMemops; }
155 bool usePackets() const { return UsePackets; }
156 bool useNewValueJumps() const { return UseNewValueJumps; }
152157
153158 bool modeIEEERndNear() const { return ModeIEEERndNear; }
154159 bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
155160 bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
156161 bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
157 bool usePackets() const { return UsePackets; }
158 bool useNewValueJumps() const { return UseNewValueJumps; }
159162
160163 bool hasMemNoShuf() const { return HasMemNoShuf; }
161164 bool hasReservedR19() const { return ReservedR19; }
0 ; RUN: llc -march=hexagon < %s | FileCheck %s
1
2 ; CHECK-LABEL: enabled:
3 ; CHECK: memw({{.*}}) += #1
4 define void @enabled(i32* %p) #0 {
5 %v0 = load i32, i32* %p
6 %v1 = add i32 %v0, 1
7 store i32 %v1, i32* %p
8 ret void
9 }
10
11 ; CHECK-LABEL: disabled:
12 ; CHECK-NOT: memw({{.*}}) += #1
13 define void @disabled(i32* %p) #1 {
14 %v0 = load i32, i32* %p
15 %v1 = add i32 %v0, 1
16 store i32 %v1, i32* %p
17 ret void
18 }
19
20 attributes #0 = { nounwind }
21 attributes #1 = { nounwind "target-features"="-memops" }
22