llvm.org GIT mirror llvm / 19cf5bf
[ARM][AArch64] Add CSDB speculation barrier instruction This adds the CSDB instruction, which is a new barrier instruction described by the whitepaper at [1]. This is in encoding space which was previously executed as a NOP, so it is available for all targets that have the relevant NOP encoding space. This matches the binutils behaviour for these instructions [2][3]. [1] https://developer.arm.com/support/security-update [2] https://sourceware.org/ml/binutils/2018-01/msg00116.html [3] https://sourceware.org/ml/binutils/2018-01/msg00120.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324324 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 2 years ago
10 changed file(s) with 48 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
419419 def : InstAlias<"sev", (HINT 0b100)>;
420420 def : InstAlias<"sevl", (HINT 0b101)>;
421421 def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;
422 def : InstAlias<"csdb", (HINT 20)>;
422423
423424 // v8.2a Statistical Profiling extension
424425 def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
20032003 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
20042004 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
20052005 def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>;
2006 def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>;
20062007
20072008 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
20082009 "\t$Rd, $Rn, $Rm",
36993699 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
37003700 let Predicates = [IsThumb2, HasRAS];
37013701 }
3702 def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
3703 def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>;
37023704
37033705 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
37043706 [(int_arm_dbg imm0_15:$opt)]> {
66156615 break;
66166616 }
66176617 case ARM::HINT:
6618 case ARM::t2HINT:
6619 if (hasRAS()) {
6620 // ESB is not predicable (pred must be AL)
6621 unsigned Imm8 = Inst.getOperand(0).getImm();
6622 unsigned Pred = Inst.getOperand(1).getImm();
6623 if (Imm8 == 0x10 && Pred != ARMCC::AL)
6624 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
6625 "predicable, but condition "
6626 "code specified");
6627 }
6628 // Without the RAS extension, this behaves as any other unallocated hint.
6618 case ARM::t2HINT: {
6619 unsigned Imm8 = Inst.getOperand(0).getImm();
6620 unsigned Pred = Inst.getOperand(1).getImm();
6621 // ESB is not predicable (pred must be AL). Without the RAS extension, this
6622 // behaves as any other unallocated hint.
6623 if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
6624 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
6625 "predicable, but condition "
6626 "code specified");
6627 if (Imm8 == 0x14 && Pred != ARMCC::AL)
6628 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
6629 "predicable, but condition "
6630 "code specified");
66296631 break;
6632 }
66306633 }
66316634
66326635 return false;
0 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
1
2 csdb
3 // CHECK: csdb // encoding: [0x9f,0x22,0x03,0xd5]
0 // RUN: not llvm-mc -triple armv8a-none-eabi %s 2>&1 | FileCheck %s
1 // RUN: not llvm-mc -triple thumbv8a-none-eabi %s 2>&1 | FileCheck %s
2
3 it eq
4 csdbeq
5 // CHECK: error: instruction 'csdb' is not predicable, but condition code specified
0 @ RUN: llvm-mc -triple armv8a-none-eabi -show-encoding %s | FileCheck %s --check-prefix=ARM
1 @ RUN: llvm-mc -triple thumbv8a-none-eabi -show-encoding %s | FileCheck %s --check-prefix=THUMB
2 @ RUN: not llvm-mc -triple thumbv6m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
3
4 csdb
5 @ ARM: csdb @ encoding: [0x14,0xf0,0x20,0xe3]
6 @ THUMB: csdb @ encoding: [0xaf,0xf3,0x14,0x80]
7 @ ERROR: error: instruction requires: thumb2
0 # RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s | FileCheck %s
1
2 [0x9f,0x22,0x03,0xd5]
3 # CHECK: csdb
0 # RUN: llvm-mc < %s -triple armv8a-none-eabi -disassemble | FileCheck %s
1
2 [0x14,0xf0,0x20,0xe3]
3 # CHECK: csdb
0 # RUN: llvm-mc < %s -triple thumbv8a-none-eabi -disassemble | FileCheck %s
1
2 [0xaf,0xf3,0x14,0x80]
3 # CHECK: csdb