llvm.org GIT mirror llvm / 19cb35b
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221994 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
17 changed file(s) with 514 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
0 ============================
1 User Guide for R600 Back-end
2 ============================
3
4 Introduction
5 ============
6
7 The R600 back-end provides ISA code generation for AMD GPUs, starting with
8 the R600 family up until the current Sea Islands (GCN Gen 2).
9
10
11 Assembler
12 =========
13
14 The assembler is currently a work in progress and not yet complete. Below
15 are the currently supported features.
16
17 SOPP Instructions
18 -----------------
19
20 Unless otherwise mentioned, all SOPP instructions that with an operand
21 accept a integer operand(s) only. No verification is performed on the
22 operands, so it is up to the programmer to be familiar with the range
23 or acceptable values.
24
25 s_waitcnt
26 ^^^^^^^^^
27
28 s_waitcnt accepts named arguments to specify which memory counter(s) to
29 wait for.
30
31 .. code-block:: nasm
32
33 // Wait for all counters to be 0
34 s_waitcnt 0
35
36 // Equivalent to s_waitcnt 0. Counter names can also be delimited by
37 // '&' or ','.
38 s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0)
39
40 // Wait for vmcnt counter to be 1.
41 s_waitcnt vmcnt(1)
42
234234 WritingAnLLVMPass
235235 HowToUseAttributes
236236 NVPTXUsage
237 R600Usage
237238 StackMaps
238239 InAlloca
239240 BigEndianNEON
315316
316317 :doc:`NVPTXUsage`
317318 This document describes using the NVPTX back-end to compile GPU kernels.
319
320 :doc:`R600Usage`
321 This document describes how to use the R600 back-end.
318322
319323 :doc:`StackMaps`
320324 LLVM support for mapping instruction addresses to the location of
152152 let guessInstructionProperties = 1;
153153 }
154154
155 def AMDGPUAsmParser : AsmParser {
156 // Some of the R600 registers have the same name, so this crashes.
157 // For example T0_XYZW and T0_XY both have the asm name T0.
158 let ShouldEmitMatchRegisterName = 0;
159 }
160
155161 def AMDGPU : Target {
156162 // Pull in Instruction Info:
157163 let InstructionSet = AMDGPUInstrInfo;
164 let AssemblyParsers = [AMDGPUAsmParser];
158165 }
159166
160167 // Dummy Instruction itineraries for pseudo instructions
2121 let AsmString = asm;
2222 let Pattern = pattern;
2323 let Itinerary = NullALU;
24
25 let isCodeGenOnly = 1;
2426
2527 let TSFlags{63} = isRegisterLoad;
2628 let TSFlags{62} = isRegisterStore;
0 //===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
10 #include "llvm/ADT/SmallString.h"
11 #include "llvm/ADT/SmallVector.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29
30 using namespace llvm;
31
32 namespace {
33
34 class AMDGPUAsmParser : public MCTargetAsmParser {
35 MCSubtargetInfo &STI;
36 MCAsmParser &Parser;
37
38
39 /// @name Auto-generated Match Functions
40 /// {
41
42 #define GET_ASSEMBLER_HEADER
43 #include "AMDGPUGenAsmMatcher.inc"
44
45 /// }
46
47 public:
48 AMDGPUAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
49 const MCInstrInfo &_MII,
50 const MCTargetOptions &Options)
51 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
52 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
53 }
54 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
55 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
56 OperandVector &Operands, MCStreamer &Out,
57 uint64_t &ErrorInfo,
58 bool MatchingInlineAsm) override;
59 bool ParseDirective(AsmToken DirectiveID) override;
60 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
61 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
62 SMLoc NameLoc, OperandVector &Operands) override;
63
64 bool parseCnt(int64_t &IntVal);
65 OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
66 };
67
68 class AMDGPUOperand : public MCParsedAsmOperand {
69 enum KindTy {
70 Token,
71 Immediate
72 } Kind;
73
74 public:
75 AMDGPUOperand(enum KindTy K) : MCParsedAsmOperand(), Kind(K) {}
76
77 struct TokOp {
78 const char *Data;
79 unsigned Length;
80 };
81
82 struct ImmOp {
83 int64_t Val;
84 };
85
86 union {
87 TokOp Tok;
88 ImmOp Imm;
89 };
90
91 void addImmOperands(MCInst &Inst, unsigned N) const {
92 Inst.addOperand(MCOperand::CreateImm(getImm()));
93 }
94 void addRegOperands(MCInst &Inst, unsigned N) const {
95 llvm_unreachable("addRegOperands");
96 }
97 StringRef getToken() const {
98 return StringRef(Tok.Data, Tok.Length);
99 }
100 bool isToken() const override {
101 return Kind == Token;
102 }
103
104 bool isImm() const override {
105 return Kind == Immediate;
106 }
107
108 int64_t getImm() const {
109 return Imm.Val;
110 }
111
112 bool isReg() const override {
113 return false;
114 }
115
116 unsigned getReg() const override {
117 return 0;
118 }
119
120 bool isMem() const override {
121 return false;
122 }
123
124 SMLoc getStartLoc() const override {
125 return SMLoc();
126 }
127
128 SMLoc getEndLoc() const override {
129 return SMLoc();
130 }
131
132 void print(raw_ostream &OS) const override { }
133
134 static std::unique_ptr CreateImm(int64_t Val) {
135 auto Op = llvm::make_unique(Immediate);
136 Op->Imm.Val = Val;
137 return Op;
138 }
139
140 static std::unique_ptr CreateToken(StringRef Str, SMLoc Loc) {
141 auto Res = llvm::make_unique(Token);
142 Res->Tok.Data = Str.data();
143 Res->Tok.Length = Str.size();
144 return Res;
145 }
146
147 bool isSWaitCnt() const;
148 };
149
150 }
151
152 bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
153 return true;
154 }
155
156
157 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
158 OperandVector &Operands,
159 MCStreamer &Out,
160 uint64_t &ErrorInfo,
161 bool MatchingInlineAsm) {
162 MCInst Inst;
163
164 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
165 default: break;
166 case Match_Success:
167 Inst.setLoc(IDLoc);
168 Out.EmitInstruction(Inst, STI);
169 return false;
170 case Match_MissingFeature:
171 return Error(IDLoc, "instruction use requires an option to be enabled");
172 case Match_MnemonicFail:
173 return Error(IDLoc, "unrecognized instruction mnemonic");
174 case Match_InvalidOperand: {
175 if (ErrorInfo != ~0ULL) {
176 if (ErrorInfo >= Operands.size())
177 return Error(IDLoc, "too few operands for instruction");
178
179 }
180 return Error(IDLoc, "invalid operand for instruction");
181 }
182 }
183 llvm_unreachable("Implement any new match types added!");
184 }
185
186 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
187 return true;
188 }
189
190 AMDGPUAsmParser::OperandMatchResultTy
191 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
192
193 // Try to parse with a custom parser
194 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
195
196 // If we successfully parsed the operand or if there as an error parsing,
197 // we are done.
198 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
199 return ResTy;
200
201 switch(getLexer().getKind()) {
202 case AsmToken::Integer: {
203 int64_t IntVal;
204 if (getParser().parseAbsoluteExpression(IntVal))
205 return MatchOperand_ParseFail;
206 Operands.push_back(AMDGPUOperand::CreateImm(IntVal));
207 return MatchOperand_Success;
208 }
209 default:
210 return MatchOperand_NoMatch;
211 }
212 }
213
214 bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
215 StringRef Name,
216 SMLoc NameLoc, OperandVector &Operands) {
217 // Add the instruction mnemonic
218 Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc));
219
220 if (getLexer().is(AsmToken::EndOfStatement))
221 return false;
222
223 AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);
224 switch (Res) {
225 case MatchOperand_Success: return false;
226 case MatchOperand_ParseFail: return Error(NameLoc,
227 "Failed parsing operand");
228 case MatchOperand_NoMatch: return Error(NameLoc, "Not a valid operand");
229 }
230 return true;
231 }
232
233 //===----------------------------------------------------------------------===//
234 // s_waitcnt
235 //===----------------------------------------------------------------------===//
236
237 bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
238 StringRef CntName = Parser.getTok().getString();
239 int64_t CntVal;
240
241 Parser.Lex();
242 if (getLexer().isNot(AsmToken::LParen))
243 return true;
244
245 Parser.Lex();
246 if (getLexer().isNot(AsmToken::Integer))
247 return true;
248
249 if (getParser().parseAbsoluteExpression(CntVal))
250 return true;
251
252 if (getLexer().isNot(AsmToken::RParen))
253 return true;
254
255 Parser.Lex();
256 if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma))
257 Parser.Lex();
258
259 int CntShift;
260 int CntMask;
261
262 if (CntName == "vmcnt") {
263 CntMask = 0xf;
264 CntShift = 0;
265 } else if (CntName == "expcnt") {
266 CntMask = 0x7;
267 CntShift = 4;
268 } else if (CntName == "lgkmcnt") {
269 CntMask = 0x7;
270 CntShift = 8;
271 } else {
272 return true;
273 }
274
275 IntVal &= ~(CntMask << CntShift);
276 IntVal |= (CntVal << CntShift);
277 return false;
278 }
279
280 AMDGPUAsmParser::OperandMatchResultTy
281 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
282 // Disable all counters by default.
283 // vmcnt [3:0]
284 // expcnt [6:4]
285 // lgkmcnt [10:8]
286 int64_t CntVal = 0x77f;
287
288 switch(getLexer().getKind()) {
289 default: return MatchOperand_ParseFail;
290 case AsmToken::Integer:
291 // The operand can be an integer value.
292 if (getParser().parseAbsoluteExpression(CntVal))
293 return MatchOperand_ParseFail;
294 break;
295
296 case AsmToken::Identifier:
297 do {
298 if (parseCnt(CntVal))
299 return MatchOperand_ParseFail;
300 } while(getLexer().isNot(AsmToken::EndOfStatement));
301 break;
302 }
303 Operands.push_back(AMDGPUOperand::CreateImm(CntVal));
304 return MatchOperand_Success;
305 }
306
307 bool AMDGPUOperand::isSWaitCnt() const {
308 return isImm();
309 }
310
311 /// Force static initialization.
312 extern "C" void LLVMInitializeR600AsmParser() {
313 RegisterMCAsmParser A(TheAMDGPUTarget);
314 }
315
316 #define GET_REGISTER_MATCHER
317 #define GET_MATCHER_IMPLEMENTATION
318 #include "AMDGPUGenAsmMatcher.inc"
319
0 add_llvm_library(LLVMR600AsmParser
1 AMDGPUAsmParser.cpp
2 )
0 ;===- ./lib/Target/R600/AsmParser/LLVMBuild.txt -------------*- Conf -*--===;
1 ;
2 ; The LLVM Compiler Infrastructure
3 ;
4 ; This file is distributed under the University of Illinois Open Source
5 ; License. See LICENSE.TXT for details.
6 ;
7 ;===------------------------------------------------------------------------===;
8 ;
9 ; This is an LLVMBuild description file for the components in this subdirectory.
10 ;
11 ; For more information on the LLVMBuild system, please see:
12 ;
13 ; http://llvm.org/docs/LLVMBuild.html
14 ;
15 ;===------------------------------------------------------------------------===;
16
17 [component_0]
18 type = Library
19 name = R600AsmParser
20 parent = R600
21 required_libraries = MC MCParser R600Desc R600Info Support
22 add_to_library_groups = R600
0 ##===- lib/Target/R600/AsmParser/Makefile ----------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8 LEVEL = ../../../..
9 LIBRARYNAME = LLVMR600AsmParser
10
11 # Hack: we need to include 'main' R600 target directory to grab private headers
12 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
13
14 include $(LEVEL)/Makefile.common
88 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
99 tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
1010 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
11 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
1112 add_public_tablegen_target(AMDGPUCommonTableGen)
1213
1314 add_llvm_target(R600CodeGen
5354 SITypeRewriter.cpp
5455 )
5556
57 add_subdirectory(AsmParser)
5658 add_subdirectory(InstPrinter)
5759 add_subdirectory(TargetInfo)
5860 add_subdirectory(MCTargetDesc)
1515 ;===------------------------------------------------------------------------===;
1616
1717 [common]
18 subdirectories = InstPrinter MCTargetDesc TargetInfo
18 subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo
1919
2020 [component_0]
2121 type = TargetGroup
2222 name = R600
2323 parent = Target
24 has_asmparser = 1
2425 has_asmprinter = 1
2526
2627 [component_1]
2728 type = Library
2829 name = R600CodeGen
2930 parent = R600
30 required_libraries = Analysis AsmPrinter CodeGen Core IPO MC R600AsmPrinter R600Desc R600Info Scalar SelectionDAG Support Target TransformUtils
31 required_libraries = Analysis AsmPrinter CodeGen Core IPO MC R600AsmParser R600AsmPrinter R600Desc R600Info Scalar SelectionDAG Support Target TransformUtils
3132 add_to_library_groups = R600
1515 AMDGPUGenDAGISel.inc AMDGPUGenSubtargetInfo.inc \
1616 AMDGPUGenMCCodeEmitter.inc AMDGPUGenCallingConv.inc \
1717 AMDGPUGenIntrinsics.inc AMDGPUGenDFAPacketizer.inc \
18 AMDGPUGenAsmWriter.inc
18 AMDGPUGenAsmWriter.inc AMDGPUGenAsmMatcher.inc
1919
20 DIRS = InstPrinter TargetInfo MCTargetDesc
20 DIRS = AsmParser InstPrinter TargetInfo MCTargetDesc
2121
2222 include $(LEVEL)/Makefile.common
3737 let Pattern = pattern;
3838 let Itinerary = itin;
3939
40 // No AsmMatcher support.
41 let isCodeGenOnly = 1;
42
4043 let TSFlags{4} = Trig;
4144 let TSFlags{5} = Op3;
4245
14951495 let mayLoad = 0;
14961496 let mayStore = 0;
14971497 let hasSideEffects = 0;
1498 let isCodeGenOnly = 1;
14981499 }
14991500
15001501 multiclass BranchConditional {
203203 let UseNamedOperandTable = 1;
204204 }
205205
206 class SOPP op, dag ins, string asm, list pattern> :
206 class SOPP op, dag ins, string asm, list pattern = []> :
207207 InstSI <(outs), ins, asm, pattern >, SOPPe {
208208
209209 let mayLoad = 0;
210210 let mayStore = 0;
211211 let hasSideEffects = 0;
212 let isCodeGenOnly = 0;
212213 let SALU = 1;
213214
214215 let UseNamedOperandTable = 1;
3232 ">= AMDGPUSubtarget::SEA_ISLANDS">;
3333 def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;
3434
35 def WAIT_FLAG : InstFlag<"printWaitFlag">;
35 def SWaitMatchClass : AsmOperandClass {
36 let Name = "SWaitCnt";
37 let RenderMethod = "addImmOperands";
38 let ParserMethod = "parseSWaitCntOps";
39 }
40
41 def WAIT_FLAG : InstFlag<"printWaitFlag"> {
42 let ParserMatchClass = SWaitMatchClass;
43 }
3644
3745 let SubtargetPredicate = isSI in {
3846
370378 // SOPP Instructions
371379 //===----------------------------------------------------------------------===//
372380
373 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16", []>;
381 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
374382
375383 let isTerminator = 1 in {
376384
391399 let DisableEncoding = "$scc" in {
392400 def S_CBRANCH_SCC0 : SOPP <
393401 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
394 "s_cbranch_scc0 $simm16", []
402 "s_cbranch_scc0 $simm16"
395403 >;
396404 def S_CBRANCH_SCC1 : SOPP <
397405 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
398 "s_cbranch_scc1 $simm16",
399 []
406 "s_cbranch_scc1 $simm16"
400407 >;
401408 } // End DisableEncoding = "$scc"
402409
403410 def S_CBRANCH_VCCZ : SOPP <
404411 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
405 "s_cbranch_vccz $simm16",
406 []
412 "s_cbranch_vccz $simm16"
407413 >;
408414 def S_CBRANCH_VCCNZ : SOPP <
409415 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
410 "s_cbranch_vccnz $simm16",
411 []
416 "s_cbranch_vccnz $simm16"
412417 >;
413418
414419 let DisableEncoding = "$exec" in {
415420 def S_CBRANCH_EXECZ : SOPP <
416421 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),
417 "s_cbranch_execz $simm16",
418 []
422 "s_cbranch_execz $simm16"
419423 >;
420424 def S_CBRANCH_EXECNZ : SOPP <
421425 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),
422 "s_cbranch_execnz $simm16",
423 []
426 "s_cbranch_execnz $simm16"
424427 >;
425428 } // End DisableEncoding = "$exec"
426429
439442 let mayStore = 1;
440443 }
441444
442 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16",
443 []
444 >;
445 //def S_SETHALT : SOPP_ <0x0000000d, "s_sethalt", []>;
446 //def S_SLEEP : SOPP_ <0x0000000e, "s_sleep", []>;
447 //def S_SETPRIO : SOPP_ <0x0000000f, "s_setprio", []>;
445 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
446 def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
447 def S_SLEEP : SOPP <0x0000000e, (ins i16imm:$simm16), "s_sleep $simm16">;
448 def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">;
448449
449450 let Uses = [EXEC] in {
450451 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "s_sendmsg $simm16",
454455 }
455456 } // End Uses = [EXEC]
456457
457 //def S_SENDMSGHALT : SOPP_ <0x00000011, "s_sendmsghalt", []>;
458 //def S_TRAP : SOPP_ <0x00000012, "s_trap", []>;
459 //def S_ICACHE_INV : SOPP_ <0x00000013, "s_icache_inv", []>;
460 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "s_incperflevel", []>;
461 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "s_decperflevel", []>;
462 //def S_TTRACEDATA : SOPP_ <0x00000016, "s_ttracedata", []>;
458 def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">;
459 def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
460 def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
461 let simm16 = 0;
462 }
463 def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;
464 def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;
465 def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
466 let simm16 = 0;
467 }
463468 } // End hasSideEffects
464469
465470 //===----------------------------------------------------------------------===//
0 if not 'R600' in config.root.targets:
1 config.unsupported = True
0 // RUN: llvm-mc -arch=r600 -mcpu=SI -show-encoding %s | FileCheck %s
1
2 s_nop 1 // CHECK: s_nop 1 ; encoding: [0x01,0x00,0x80,0xbf]
3 s_endpgm // CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
4 s_branch 2 // CHECK: s_branch 2 ; encoding: [0x02,0x00,0x82,0xbf]
5 s_cbranch_scc0 3 // CHECK: s_cbranch_scc0 3 ; encoding: [0x03,0x00,0x84,0xbf]
6 s_cbranch_scc1 4 // CHECK: s_cbranch_scc1 4 ; encoding: [0x04,0x00,0x85,0xbf]
7 s_cbranch_vccz 5 // CHECK: s_cbranch_vccz 5 ; encoding: [0x05,0x00,0x86,0xbf]
8 s_cbranch_vccnz 6 // CHECK: s_cbranch_vccnz 6 ; encoding: [0x06,0x00,0x87,0xbf]
9 s_cbranch_execz 7 // CHECK: s_cbranch_execz 7 ; encoding: [0x07,0x00,0x88,0xbf]
10 s_cbranch_execnz 8 // CHECK: s_cbranch_execnz 8 ; encoding: [0x08,0x00,0x89,0xbf]
11 s_barrier // CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
12
13 //===----------------------------------------------------------------------===//
14 // s_waitcnt
15 //===----------------------------------------------------------------------===//
16
17 s_waitcnt 0
18 // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
19
20 s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)
21 // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
22
23 s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
24 // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
25
26 s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0)
27 // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
28
29 s_waitcnt vmcnt(1)
30 // CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x07,0x8c,0xbf]
31
32 s_waitcnt expcnt(2)
33 // CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x07,0x8c,0xbf]
34
35 s_waitcnt lgkmcnt(3)
36 // CHECK: s_waitcnt lgkmcnt(3) ; encoding: [0x7f,0x03,0x8c,0xbf]
37
38 s_waitcnt vmcnt(0), expcnt(0)
39 // CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x07,0x8c,0xbf]
40
41
42 s_sethalt 9 // CHECK: s_sethalt 9 ; encoding: [0x09,0x00,0x8d,0xbf]
43 s_sleep 10 // CHECK: s_sleep 10 ; encoding: [0x0a,0x00,0x8e,0xbf]
44 s_setprio 1 // CHECK: s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf]
45 s_sendmsg 2 // CHECK: s_sendmsg Gs(nop), [m0] ; encoding: [0x02,0x00,0x90,0xbf]
46 s_sendmsghalt 3 // CHECK: s_sendmsghalt 3 ; encoding: [0x03,0x00,0x91,0xbf]
47 s_trap 4 // CHECK: s_trap 4 ; encoding: [0x04,0x00,0x92,0xbf]
48 s_icache_inv // CHECK: s_icache_inv ; encoding: [0x00,0x00,0x93,0xbf]
49 s_incperflevel 5 // CHECK: s_incperflevel 5 ; encoding: [0x05,0x00,0x94,0xbf]
50 s_decperflevel 6 // CHECK: s_decperflevel 6 ; encoding: [0x06,0x00,0x95,0xbf]
51 s_ttracedata // CHECK: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf]