llvm.org GIT mirror llvm / 19a3e9a
[ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204304 91177308-0d34-0410-b5e6-96231b3b80d8 Hao Liu 5 years ago
2 changed file(s) with 68 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
415415 if (!MO.isReg() || !MO.isUse())
416416 continue;
417417 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
418 !usesRegClass(MO, &ARM::QPRRegClass))
418 !usesRegClass(MO, &ARM::QPRRegClass) &&
419 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
419420 continue;
420421
421422 Defs.push_back(MO.getReg());
535536 InsertPt++;
536537 unsigned Out;
537538
538 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
539 // DPair has the same length as QPR and also has two DPRs as subreg.
540 // Treat DPair as QPR.
541 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
542 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
539543 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
540544 ARM::dsub_0, &ARM::DPRRegClass);
541545 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
568572 default: llvm_unreachable("Unknown preferred lane!");
569573 }
570574
571 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass);
575 // Treat DPair as QPR
576 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
577 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
572578
573579 Out = createImplicitDef(MBB, InsertPt, DL);
574580 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
5555 %i2 = fadd <4 x float> %i1, %i1
5656 ret <4 x float> %i2
5757 }
58
59 ; Test that DPair can be successfully passed as QPR.
60 ; CHECK-ENABLED-LABEL: test_DPair1:
61 ; CHECK-DISABLED-LABEL: test_DPair1:
62 define void @test_DPair1(i32 %vsout, i8* nocapture %out, float %x, float %y) {
63 entry:
64 %0 = insertelement <4 x float> undef, float %x, i32 1
65 %1 = insertelement <4 x float> %0, float %y, i32 0
66 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
67 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[1]
68 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
69 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[1]
70 ; CHECK-DISABLED-NOT: vdup
71 switch i32 %vsout, label %sw.epilog [
72 i32 1, label %sw.bb
73 i32 0, label %sw.bb6
74 ]
75
76 sw.bb: ; preds = %entry
77 %2 = insertelement <4 x float> %1, float 0.000000e+00, i32 0
78 br label %sw.bb6
79
80 sw.bb6: ; preds = %sw.bb, %entry
81 %sum.0 = phi <4 x float> [ %1, %entry ], [ %2, %sw.bb ]
82 %3 = extractelement <4 x float> %sum.0, i32 0
83 %conv = fptoui float %3 to i8
84 store i8 %conv, i8* %out, align 1
85 ret void
86
87 sw.epilog: ; preds = %entry
88 ret void
89 }
90
91 ; CHECK-ENABLED-LABEL: test_DPair2:
92 ; CHECK-DISABLED-LABEL: test_DPair2:
93 define void @test_DPair2(i32 %vsout, i8* nocapture %out, float %x) {
94 entry:
95 %0 = insertelement <4 x float> undef, float %x, i32 0
96 ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d{{[0-9]*}}[0]
97 ; CHECK-DISABLED-NOT: vdup
98 switch i32 %vsout, label %sw.epilog [
99 i32 1, label %sw.bb
100 i32 0, label %sw.bb1
101 ]
102
103 sw.bb: ; preds = %entry
104 %1 = insertelement <4 x float> %0, float 0.000000e+00, i32 0
105 br label %sw.bb1
106
107 sw.bb1: ; preds = %entry, %sw.bb
108 %sum.0 = phi <4 x float> [ %0, %entry ], [ %1, %sw.bb ]
109 %2 = extractelement <4 x float> %sum.0, i32 0
110 %conv = fptoui float %2 to i8
111 store i8 %conv, i8* %out, align 1
112 br label %sw.epilog
113
114 sw.epilog: ; preds = %entry, %sw.bb1
115 ret void
116 }