llvm.org GIT mirror llvm / 194fea7
[GlobalISel][AArch64] Add generic legalization rule for extends This adds a legalization rule for G_ZEXT, G_ANYEXT, and G_SEXT which allows extends whenever the types will fit in registers (or the source is an s1). Update tests. Add GISel checks throughout all of arm64-vabs.ll, where we now select a good portion of the code. Add GISel checks to arm64-subvector-extend.ll, which has a good number of vector extends in it. Differential Revision: https://reviews.llvm.org/D60889 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359222 91177308-0d34-0410-b5e6-96231b3b80d8 Jessica Paquette 9 months ago
6 changed file(s) with 346 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
320320
321321 // Extensions
322322 getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
323 .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32})
324 .legalFor({v8s16, v8s8});
323 .legalIf([=](const LegalityQuery &Query) {
324 unsigned DstSize = Query.Types[0].getSizeInBits();
325
326 // Make sure that we have something that will fit in a register, and
327 // make sure it's a power of 2.
328 if (DstSize < 8 || DstSize > 128 || !isPowerOf2_32(DstSize))
329 return false;
330
331 const LLT &SrcTy = Query.Types[1];
332
333 // Special case for s1.
334 if (SrcTy == s1)
335 return true;
336
337 // Make sure we fit in a register otherwise. Don't bother checking that
338 // the source type is below 128 bits. We shouldn't be allowing anything
339 // through which is wider than the destination in the first place.
340 unsigned SrcSize = SrcTy.getSizeInBits();
341 if (SrcSize < 8 || !isPowerOf2_32(SrcSize))
342 return false;
343
344 return true;
345 });
325346
326347 getActionDefinitionsBuilder(G_TRUNC).alwaysLegal();
327348
226226 %2:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
227227 $q0 = COPY %2(<8 x s16>)
228228 RET_ReallyLR implicit $q0
229
230 ...
231 ---
232 name: test_zext_v4s32_from_v4s16
233 alignment: 2
234 tracksRegLiveness: true
235 machineFunctionInfo: {}
236 body: |
237 bb.0:
238 liveins: $d0
239
240 ; CHECK-LABEL: name: test_zext_v4s32_from_v4s16
241 ; CHECK: liveins: $d0
242 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
243 ; CHECK: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
244 ; CHECK: $q0 = COPY [[ZEXT]](<4 x s32>)
245 ; CHECK: RET_ReallyLR implicit $q0
246 %0:_(<4 x s16>) = COPY $d0
247 %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
248 $q0 = COPY %1(<4 x s32>)
249 RET_ReallyLR implicit $q0
250
251 ...
252 ---
253 name: test_sext_v4s32_from_v4s16
254 alignment: 2
255 tracksRegLiveness: true
256 machineFunctionInfo: {}
257 body: |
258 bb.0:
259 liveins: $d0
260
261 ; CHECK-LABEL: name: test_sext_v4s32_from_v4s16
262 ; CHECK: liveins: $d0
263 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
264 ; CHECK: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
265 ; CHECK: $q0 = COPY [[SEXT]](<4 x s32>)
266 ; CHECK: RET_ReallyLR implicit $q0
267 %0:_(<4 x s16>) = COPY $d0
268 %1:_(<4 x s32>) = G_SEXT %0(<4 x s16>)
269 $q0 = COPY %1(<4 x s32>)
270 RET_ReallyLR implicit $q0
271
272 ...
273 ---
274 name: test_anyext_v4s32_from_v4s16
275 alignment: 2
276 tracksRegLiveness: true
277 machineFunctionInfo: {}
278 body: |
279 bb.0:
280 liveins: $d0
281
282 ; CHECK-LABEL: name: test_anyext_v4s32_from_v4s16
283 ; CHECK: liveins: $d0
284 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
285 ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[COPY]](<4 x s16>)
286 ; CHECK: $q0 = COPY [[ANYEXT]](<4 x s32>)
287 ; CHECK: RET_ReallyLR implicit $q0
288 %0:_(<4 x s16>) = COPY $d0
289 %1:_(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
290 $q0 = COPY %1(<4 x s32>)
291 RET_ReallyLR implicit $q0
292
293 ...
294 ---
295 name: test_zext_v2s64_from_v2s32
296 alignment: 2
297 tracksRegLiveness: true
298 registers:
299 - { id: 0, class: _ }
300 - { id: 1, class: _ }
301 machineFunctionInfo: {}
302 body: |
303 bb.0:
304 liveins: $d0
305
306 ; CHECK-LABEL: name: test_zext_v2s64_from_v2s32
307 ; CHECK: liveins: $d0
308 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
309 ; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
310 ; CHECK: $q0 = COPY [[ZEXT]](<2 x s64>)
311 ; CHECK: RET_ReallyLR implicit $q0
312 %0:_(<2 x s32>) = COPY $d0
313 %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
314 $q0 = COPY %1(<2 x s64>)
315 RET_ReallyLR implicit $q0
316
317 ...
318 ---
319 name: test_sext_v2s64_from_v2s32
320 alignment: 2
321 tracksRegLiveness: true
322 registers:
323 - { id: 0, class: _ }
324 - { id: 1, class: _ }
325 machineFunctionInfo: {}
326 body: |
327 bb.0:
328 liveins: $d0
329
330 ; CHECK-LABEL: name: test_sext_v2s64_from_v2s32
331 ; CHECK: liveins: $d0
332 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
333 ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
334 ; CHECK: $q0 = COPY [[SEXT]](<2 x s64>)
335 ; CHECK: RET_ReallyLR implicit $q0
336 %0:_(<2 x s32>) = COPY $d0
337 %1:_(<2 x s64>) = G_SEXT %0(<2 x s32>)
338 $q0 = COPY %1(<2 x s64>)
339 RET_ReallyLR implicit $q0
340
341 ...
342 ---
343 name: test_anyext_v2s64_from_v2s32
344 alignment: 2
345 tracksRegLiveness: true
346 registers:
347 - { id: 0, class: _ }
348 - { id: 1, class: _ }
349 machineFunctionInfo: {}
350 body: |
351 bb.0:
352 liveins: $d0
353
354 ; CHECK-LABEL: name: test_anyext_v2s64_from_v2s32
355 ; CHECK: liveins: $d0
356 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
357 ; CHECK: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s32>)
358 ; CHECK: $q0 = COPY [[ANYEXT]](<2 x s64>)
359 ; CHECK: RET_ReallyLR implicit $q0
360 %0:_(<2 x s32>) = COPY $d0
361 %1:_(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
362 $q0 = COPY %1(<2 x s64>)
363 RET_ReallyLR implicit $q0
364
365 ...
156156 # DEBUG: .. type index coverage check SKIPPED: no rules defined
157157 #
158158 # DEBUG-NEXT: G_ANYEXT (opcode {{[0-9]+}}): 2 type indices
159 # DEBUG: .. the first uncovered type index: 2, OK
159 # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
160160 #
161161 # DEBUG-NEXT: G_TRUNC (opcode {{[0-9]+}}): 2 type indices
162162 # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
174174 # DEBUG: .. the first uncovered type index: 2, OK
175175 #
176176 # DEBUG-NEXT: G_SEXT (opcode {{[0-9]+}}): 2 type indices
177 # DEBUG: .. the first uncovered type index: 2, OK
177 # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
178178 #
179179 # DEBUG-NEXT: G_ZEXT (opcode {{[0-9]+}}): 2 type indices
180 # DEBUG: .. the first uncovered type index: 2, OK
180 # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
181181 #
182182 # DEBUG-NEXT: G_SHL (opcode {{[0-9]+}}): 2 type indices
183183 # DEBUG:.. type index coverage check SKIPPED: user-defined predicate detected
66 define void @anyext_s64_from_s32() { ret void }
77 define void @anyext_s32_from_s8() { ret void }
88 define void @anyext_v8s16_from_v8s8() { ret void }
9 define void @anyext_v4s32_from_v4s16() { ret void }
10 define void @anyext_v2s64_from_v2s32() { ret void }
911
1012 define void @zext_s64_from_s32() { ret void }
1113 define void @zext_s32_from_s16() { ret void }
1214 define void @zext_s32_from_s8() { ret void }
1315 define void @zext_s16_from_s8() { ret void }
1416 define void @zext_v8s16_from_v8s8() { ret void }
17 define void @zext_v4s32_from_v4s16() { ret void }
18 define void @zext_v2s64_from_v2s32() { ret void }
1519
1620 define void @sext_s64_from_s32() { ret void }
1721 define void @sext_s32_from_s16() { ret void }
1822 define void @sext_s32_from_s8() { ret void }
1923 define void @sext_s16_from_s8() { ret void }
2024 define void @sext_v8s16_from_v8s8() { ret void }
25 define void @sext_v4s32_from_v4s16() { ret void }
26 define void @sext_v2s64_from_v2s32() { ret void }
2127 ...
2228
2329 ---
8995 %1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)
9096 $q0 = COPY %1(<8 x s16>)
9197 RET_ReallyLR implicit $q0
98 ...
99
100 ---
101 name: anyext_v4s32_from_v4s16
102 alignment: 2
103 legalized: true
104 regBankSelected: true
105 tracksRegLiveness: true
106 registers:
107 - { id: 0, class: fpr }
108 - { id: 1, class: fpr }
109 machineFunctionInfo: {}
110 body: |
111 bb.0:
112 liveins: $d0
113
114 ; CHECK-LABEL: name: anyext_v4s32_from_v4s16
115 ; CHECK: liveins: $d0
116 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
117 ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
118 ; CHECK: $q0 = COPY [[USHLLv4i16_shift]]
119 ; CHECK: RET_ReallyLR implicit $q0
120 %0:fpr(<4 x s16>) = COPY $d0
121 %1:fpr(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
122 $q0 = COPY %1(<4 x s32>)
123 RET_ReallyLR implicit $q0
124 ...
125
126 ---
127 name: anyext_v2s64_from_v2s32
128 alignment: 2
129 tracksRegLiveness: true
130 legalized: true
131 regBankSelected: true
132 tracksRegLiveness: true
133 registers:
134 - { id: 0, class: fpr }
135 - { id: 1, class: fpr }
136 machineFunctionInfo: {}
137 body: |
138 bb.0:
139 liveins: $d0
140
141 ; CHECK-LABEL: name: anyext_v2s64_from_v2s32
142 ; CHECK: liveins: $d0
143 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
144 ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
145 ; CHECK: $q0 = COPY [[USHLLv2i32_shift]]
146 ; CHECK: RET_ReallyLR implicit $q0
147 %0:fpr(<2 x s32>) = COPY $d0
148 %1:fpr(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
149 $q0 = COPY %1(<2 x s64>)
150 RET_ReallyLR implicit $q0
151 ...
92152
93153 ---
94154 name: zext_s64_from_s32
212272 ...
213273
214274 ---
275 name: zext_v4s32_from_v4s16
276 alignment: 2
277 legalized: true
278 regBankSelected: true
279 tracksRegLiveness: true
280 registers:
281 - { id: 0, class: fpr }
282 - { id: 1, class: fpr }
283 machineFunctionInfo: {}
284 body: |
285 bb.0:
286 liveins: $d0
287
288 ; CHECK-LABEL: name: zext_v4s32_from_v4s16
289 ; CHECK: liveins: $d0
290 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
291 ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
292 ; CHECK: $q0 = COPY [[USHLLv4i16_shift]]
293 ; CHECK: RET_ReallyLR implicit $q0
294 %0:fpr(<4 x s16>) = COPY $d0
295 %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
296 $q0 = COPY %1(<4 x s32>)
297 RET_ReallyLR implicit $q0
298 ...
299
300 ---
301 name: zext_v2s64_from_v2s32
302 alignment: 2
303 legalized: true
304 regBankSelected: true
305 tracksRegLiveness: true
306 registers:
307 - { id: 0, class: fpr }
308 - { id: 1, class: fpr }
309 machineFunctionInfo: {}
310 body: |
311 bb.0:
312 liveins: $d0
313
314 ; CHECK-LABEL: name: zext_v2s64_from_v2s32
315 ; CHECK: liveins: $d0
316 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
317 ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
318 ; CHECK: $q0 = COPY [[USHLLv2i32_shift]]
319 ; CHECK: RET_ReallyLR implicit $q0
320 %0:fpr(<2 x s32>) = COPY $d0
321 %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
322 $q0 = COPY %1(<2 x s64>)
323 RET_ReallyLR implicit $q0
324 ...
325
326 ---
215327 name: sext_s64_from_s32
216328 legalized: true
217329 regBankSelected: true
331443 RET_ReallyLR implicit $q0
332444
333445 ...
446
447 ---
448 name: sext_v4s32_from_v4s16
449 alignment: 2
450 legalized: true
451 regBankSelected: true
452 tracksRegLiveness: true
453 registers:
454 - { id: 0, class: fpr }
455 - { id: 1, class: fpr }
456 machineFunctionInfo: {}
457 body: |
458 bb.0:
459 liveins: $d0
460
461 ; CHECK-LABEL: name: sext_v4s32_from_v4s16
462 ; CHECK: liveins: $d0
463 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
464 ; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
465 ; CHECK: $q0 = COPY [[SSHLLv4i16_shift]]
466 ; CHECK: RET_ReallyLR implicit $q0
467 %0:fpr(<4 x s16>) = COPY $d0
468 %1:fpr(<4 x s32>) = G_SEXT %0(<4 x s16>)
469 $q0 = COPY %1(<4 x s32>)
470 RET_ReallyLR implicit $q0
471 ...
472
473 ---
474 name: sext_v2s64_from_v2s32
475 alignment: 2
476 legalized: true
477 regBankSelected: true
478 tracksRegLiveness: true
479 registers:
480 - { id: 0, class: fpr }
481 - { id: 1, class: fpr }
482 machineFunctionInfo: {}
483 body: |
484 bb.0:
485 liveins: $d0
486
487 ; CHECK-LABEL: name: sext_v2s64_from_v2s32
488 ; CHECK: liveins: $d0
489 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
490 ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
491 ; CHECK: $q0 = COPY [[SSHLLv2i32_shift]]
492 ; CHECK: RET_ReallyLR implicit $q0
493 %0:fpr(<2 x s32>) = COPY $d0
494 %1:fpr(<2 x s64>) = G_SEXT %0(<2 x s32>)
495 $q0 = COPY %1(<2 x s64>)
496 RET_ReallyLR implicit $q0
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
12
23 ; Test efficient codegen of vector extends up from legal type to 128 bit
34 ; and 256 bit vector types.
56 ;-----
67 ; Vectors of i16.
78 ;-----
9
10 ; FALLBACK-NOT: remark:{{.*}}(in function: func1)
811 define <8 x i16> @func1(<8 x i8> %v0) nounwind {
912 ; CHECK-LABEL: func1:
1013 ; CHECK-NEXT: ushll.8h v0, v0, #0
1316 ret <8 x i16> %r
1417 }
1518
19 ; FALLBACK-NOT: remark:{{.*}}(in function: func2)
1620 define <8 x i16> @func2(<8 x i8> %v0) nounwind {
1721 ; CHECK-LABEL: func2:
1822 ; CHECK-NEXT: sshll.8h v0, v0, #0
4347 ; Vectors of i32.
4448 ;-----
4549
50 ; FALLBACK-NOT: remark:{{.*}}(in function: afunc1)
4651 define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
4752 ; CHECK-LABEL: afunc1:
4853 ; CHECK-NEXT: ushll.4s v0, v0, #0
5156 ret <4 x i32> %r
5257 }
5358
59 ; FALLBACK-NOT: remark:{{.*}}(in function: afunc2)
5460 define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
5561 ; CHECK-LABEL: afunc2:
5662 ; CHECK-NEXT: sshll.4s v0, v0, #0
0 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
1 ; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
2
3 ; FALLBACK-NOT: remark:{{.*}}(<8 x s16>) = G_ZEXT %4:_(<8 x s8>)
1 ; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=FALLBACK,CHECK
2
3 ; FALLBACK-NOT: remark:{{.*}} G_ZEXT
44 ; FALLBACK-NOT: remark:{{.*}} sabdl8h
55 define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
66 ;CHECK-LABEL: sabdl8h:
77 ;CHECK: sabdl.8h
8 ;GISEL-LABEL: sabdl8h:
9 ;GISEL: sabdl.8h
108 %tmp1 = load <8 x i8>, <8 x i8>* %A
119 %tmp2 = load <8 x i8>, <8 x i8>* %B
1210 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
1412 ret <8 x i16> %tmp4
1513 }
1614
15 ; FALLBACK-NOT: remark:{{.*}} sabdl4s
1716 define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
1817 ;CHECK-LABEL: sabdl4s:
1918 ;CHECK: sabdl.4s
2423 ret <4 x i32> %tmp4
2524 }
2625
26 ; FALLBACK-NOT: remark:{{.*}} sabdl2d
2727 define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
2828 ;CHECK-LABEL: sabdl2d:
2929 ;CHECK: sabdl.2d
7070 ret <2 x i64> %tmp4
7171 }
7272
73 ; FALLBACK-NOT: remark:{{.*}} uabdl8h)
7374 define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
7475 ;CHECK-LABEL: uabdl8h:
7576 ;CHECK: uabdl.8h
8081 ret <8 x i16> %tmp4
8182 }
8283
84 ; FALLBACK-NOT: remark:{{.*}} uabdl4s)
8385 define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
8486 ;CHECK-LABEL: uabdl4s:
8587 ;CHECK: uabdl.4s
9092 ret <4 x i32> %tmp4
9193 }
9294
95 ; FALLBACK-NOT: remark:{{.*}} uabdl2d)
9396 define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
9497 ;CHECK-LABEL: uabdl2d:
9598 ;CHECK: uabdl.2d
559562 declare <1 x i64> @llvm.aarch64.neon.abs.v1i64(<1 x i64>) nounwind readnone
560563 declare i64 @llvm.aarch64.neon.abs.i64(i64) nounwind readnone
561564
565 ; FALLBACK-NOT: remark:{{.*}} sabal8h
562566 define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
563567 ;CHECK-LABEL: sabal8h:
564568 ;CHECK: sabal.8h
571575 ret <8 x i16> %tmp5
572576 }
573577
578 ; FALLBACK-NOT: remark:{{.*}} sabal4s
574579 define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
575580 ;CHECK-LABEL: sabal4s:
576581 ;CHECK: sabal.4s
583588 ret <4 x i32> %tmp5
584589 }
585590
591 ; FALLBACK-NOT: remark:{{.*}} sabal2d
586592 define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
587593 ;CHECK-LABEL: sabal2d:
588594 ;CHECK: sabal.2d
638644 ret <2 x i64> %tmp5
639645 }
640646
647 ; FALLBACK-NOT: remark:{{.*}} uabal8h
641648 define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
642649 ;CHECK-LABEL: uabal8h:
643650 ;CHECK: uabal.8h
650657 ret <8 x i16> %tmp5
651658 }
652659
660 ; FALLBACK-NOT: remark:{{.*}} uabal8s
653661 define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
654662 ;CHECK-LABEL: uabal4s:
655663 ;CHECK: uabal.4s
662670 ret <4 x i32> %tmp5
663671 }
664672
673 ; FALLBACK-NOT: remark:{{.*}} uabal2d
665674 define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
666675 ;CHECK-LABEL: uabal2d:
667676 ;CHECK: uabal.2d