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[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764 Differential Revision: https://reviews.llvm.org/D41614 Reviewers: vpykhtin, artem.tamazov, arsenm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322189 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 2 years ago
11 changed file(s) with 100 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
661661 case AMDGPU::FLAT_SCR_LO:
662662 case AMDGPU::FLAT_SCR_HI:
663663 continue;
664
665 case AMDGPU::XNACK_MASK:
666 case AMDGPU::XNACK_MASK_LO:
667 case AMDGPU::XNACK_MASK_HI:
668 llvm_unreachable("xnack_mask registers should not be used");
664669
665670 case AMDGPU::TBA:
666671 case AMDGPU::TBA_LO:
895895 KernelScope.initialize(getContext());
896896 }
897897
898 bool hasXNACK() const {
899 return AMDGPU::hasXNACK(getSTI());
900 }
901
898902 bool isSI() const {
899903 return AMDGPU::isSI(getSTI());
900904 }
15201524 .Case("exec", AMDGPU::EXEC)
15211525 .Case("vcc", AMDGPU::VCC)
15221526 .Case("flat_scratch", AMDGPU::FLAT_SCR)
1527 .Case("xnack_mask", AMDGPU::XNACK_MASK)
15231528 .Case("m0", AMDGPU::M0)
15241529 .Case("scc", AMDGPU::SCC)
15251530 .Case("tba", AMDGPU::TBA)
15261531 .Case("tma", AMDGPU::TMA)
15271532 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
15281533 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
1534 .Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO)
1535 .Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI)
15291536 .Case("vcc_lo", AMDGPU::VCC_LO)
15301537 .Case("vcc_hi", AMDGPU::VCC_HI)
15311538 .Case("exec_lo", AMDGPU::EXEC_LO)
15601567 }
15611568 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) {
15621569 Reg = AMDGPU::FLAT_SCR;
1570 RegWidth = 2;
1571 return true;
1572 }
1573 if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) {
1574 Reg = AMDGPU::XNACK_MASK;
15631575 RegWidth = 2;
15641576 return true;
15651577 }
26162628 case AMDGPU::TMA_LO:
26172629 case AMDGPU::TMA_HI:
26182630 return !isGFX9();
2631 case AMDGPU::XNACK_MASK:
2632 case AMDGPU::XNACK_MASK_LO:
2633 case AMDGPU::XNACK_MASK_HI:
2634 return !isCI() && !isSI() && hasXNACK();
26192635 default:
26202636 break;
26212637 }
689689 switch (Val) {
690690 case 102: return createRegOperand(FLAT_SCR_LO);
691691 case 103: return createRegOperand(FLAT_SCR_HI);
692 // ToDo: no support for xnack_mask_lo/_hi register
693 case 104:
694 case 105: break;
692 case 104: return createRegOperand(XNACK_MASK_LO);
693 case 105: return createRegOperand(XNACK_MASK_HI);
695694 case 106: return createRegOperand(VCC_LO);
696695 case 107: return createRegOperand(VCC_HI);
697696 case 108: assert(!isGFX9()); return createRegOperand(TBA_LO);
721720
722721 switch (Val) {
723722 case 102: return createRegOperand(FLAT_SCR);
723 case 104: return createRegOperand(XNACK_MASK);
724724 case 106: return createRegOperand(VCC);
725725 case 108: assert(!isGFX9()); return createRegOperand(TBA);
726726 case 110: assert(!isGFX9()); return createRegOperand(TMA);
266266 case AMDGPU::FLAT_SCR:
267267 O << "flat_scratch";
268268 return;
269 case AMDGPU::XNACK_MASK:
270 O << "xnack_mask";
271 return;
269272 case AMDGPU::VCC_LO:
270273 O << "vcc_lo";
271274 return;
295298 return;
296299 case AMDGPU::FLAT_SCR_HI:
297300 O << "flat_scratch_hi";
301 return;
302 case AMDGPU::XNACK_MASK_LO:
303 O << "xnack_mask_lo";
304 return;
305 case AMDGPU::XNACK_MASK_HI:
306 O << "xnack_mask_hi";
298307 return;
299308 case AMDGPU::FP_REG:
300309 case AMDGPU::SP_REG:
161161 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT);
162162 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE);
163163 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT);
164
165 // Reserve xnack_mask registers - support is not implemented in Codegen.
166 reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK);
164167
165168 // Reserve Trap Handler registers - support is not implemented in Codegen.
166169 reserveRegisterTuples(Reserved, AMDGPU::TBA);
7474 def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>;
7575 def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>;
7676 def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>;
77
78 def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>;
79 def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>;
80
81 def XNACK_MASK : RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]>,
82 DwarfRegAlias {
83 let Namespace = "AMDGPU";
84 let SubRegIndices = [sub0, sub1];
85 let HWEncoding = 104;
86 }
7787
7888 // Trap handler registers
7989 def TBA_LO : SIReg<"tba_lo", 108>;
402412 // Subset of SReg_32 without M0 for SMRD instructions and alike.
403413 // See comments in SIInstructions.td for more info.
404414 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
405 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
415 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,
406416 TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
407417 SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {
408418 let AllocationPriority = 7;
434444 }
435445
436446 def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
437 (add SGPR_64, VCC, FLAT_SCR, TTMP_64, TBA, TMA)> {
447 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA)> {
438448 let CopyCost = 1;
439449 let AllocationPriority = 8;
440450 }
595595 default:
596596 return false;
597597 }
598 }
599
600 bool hasXNACK(const MCSubtargetInfo &STI) {
601 return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
598602 }
599603
600604 bool isSI(const MCSubtargetInfo &STI) {
277277 }
278278 }
279279
280 bool hasXNACK(const MCSubtargetInfo &STI);
281
280282 bool isSI(const MCSubtargetInfo &STI);
281283 bool isCI(const MCSubtargetInfo &STI);
282284 bool isVI(const MCSubtargetInfo &STI);
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
3
4 // RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -show-encoding %s 2>&1 | FileCheck -check-prefix=XNACKERR %s
5 // RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -show-encoding %s | FileCheck -check-prefix=XNACK %s
6
7 s_mov_b64 xnack_mask, -1
8 // NOSICIVI: error: not a valid operand.
9 // XNACK: s_mov_b64 xnack_mask, -1 ; encoding: [0xc1,0x01,0xe8,0xbe]
10
11 s_mov_b32 xnack_mask_lo, -1
12 // NOSICIVI: error: not a valid operand.
13 // XNACK: s_mov_b32 xnack_mask_lo, -1 ; encoding: [0xc1,0x00,0xe8,0xbe]
14
15 s_mov_b32 xnack_mask_hi, -1
16 // NOSICIVI: error: not a valid operand.
17 // XNACK: s_mov_b32 xnack_mask_hi, -1 ; encoding: [0xc1,0x00,0xe9,0xbe]
18
19 s_mov_b32 xnack_mask, -1
20 // NOSICIVI: error: not a valid operand.
21 // XNACKERR: error: invalid operand for instruction
22
23 s_mov_b64 xnack_mask_lo, -1
24 // NOSICIVI: error: not a valid operand.
25 // XNACKERR: error: invalid operand for instruction
26
27 s_mov_b64 xnack_mask_hi, -1
28 // NOSICIVI: error: not a valid operand.
29 // XNACKERR: error: invalid operand for instruction
1414 # VI: s_mov_b32 s0, 0xfe5163ab ; encoding: [0xff,0x00,0x80,0xbe,0xab,0x63,0x51,0xfe]
1515 0xff 0x00 0x80 0xbe 0xab 0x63 0x51 0xfe
1616
17 # VI: s_mov_b32 xnack_mask_lo, -1 ; encoding: [0xc1,0x00,0xe8,0xbe]
18 0xc1,0x00,0xe8,0xbe
19
20 # VI: s_mov_b32 xnack_mask_hi, -1 ; encoding: [0xc1,0x00,0xe9,0xbe]
21 0xc1,0x00,0xe9,0xbe
22
1723 # VI: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x01,0x82,0xbe]
1824 0x04 0x01 0x82 0xbe
1925
20 # FIXME: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x01,0x82,0xbe]
26 # VI: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x01,0x82,0xbe]
2127 0xc1 0x01 0x82 0xbe
28
29 # VI: s_mov_b64 xnack_mask, -1 ; encoding: [0xc1,0x01,0xe8,0xbe]
30 0xc1,0x01,0xe8,0xbe
2231
2332 # VI: s_mov_b64 s[2:3], 0xffffffff ; encoding: [0xff,0x01,0x82,0xbe,0xff,0xff,0xff,0xff]
2433 0xff 0x01 0x82 0xbe 0xff 0xff 0xff 0xff
209209 # GFX9: v_mad_mix_f32 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04]
210210 0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04
211211
212 # GFX9: v_mad_mix_f32 v5, xnack_mask_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x69,0x04,0x0e,0x04]
213 0x05,0x00,0xa0,0xd3,0x69,0x04,0x0e,0x04
214
212215 # GFX9: v_mad_mix_f32 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04]
213216 0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04
214217
664667
665668 # GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
666669 0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04
670
671 # GFX9: v_add_f64 v[5:6], xnack_mask, v[2:3] ; encoding: [0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00]
672 0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00