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R600/SI: cleanup VGPR encoding Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174656 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 7 years ago
5 changed file(s) with 16 addition(s) and 178 deletion(s). Raw diff Collapse all Expand all
126126 } else {
127127 assert(!"Unknown register class");
128128 }
129 hwReg = RI->getEncodingValue(reg);
129 hwReg = RI->getEncodingValue(reg) & 0xff;
130130 maxUsed = hwReg + width - 1;
131131 if (isSGPR) {
132132 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
2222 #include "llvm/MC/MCRegisterInfo.h"
2323 #include "llvm/MC/MCSubtargetInfo.h"
2424 #include "llvm/Support/raw_ostream.h"
25
26 #define VGPR_BIT(src_idx) (1ULL << (9 * src_idx - 1))
27 #define SI_INSTR_FLAGS_ENCODING_MASK 0xf
28
29 // These must be kept in sync with SIInstructions.td and also the
30 // InstrEncodingInfo array in SIInstrInfo.cpp.
31 //
32 // NOTE: This enum is only used to identify the encoding type within LLVM,
33 // the actual encoding type that is part of the instruction format is different
34 namespace SIInstrEncodingType {
35 enum Encoding {
36 EXP = 0,
37 LDS = 1,
38 MIMG = 2,
39 MTBUF = 3,
40 MUBUF = 4,
41 SMRD = 5,
42 SOP1 = 6,
43 SOP2 = 7,
44 SOPC = 8,
45 SOPK = 9,
46 SOPP = 10,
47 VINTRP = 11,
48 VOP1 = 12,
49 VOP2 = 13,
50 VOP3 = 14,
51 VOPC = 15
52 };
53 }
5425
5526 using namespace llvm;
5627
9061 /// \brief Encoding for when 4 consectuive registers are used
9162 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
9263 SmallVectorImpl &Fixup) const;
93
94 /// \brief Post-Encoder method for VOP instructions
95 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
96
97 private:
98
99 /// \returns this SIInstrEncodingType for this instruction.
100 unsigned getEncodingType(const MCInst &MI) const;
101
102 /// \brief Get then size in bytes of this instructions encoding.
103 unsigned getEncodingBytes(const MCInst &MI) const;
104
105 /// \returns the hardware encoding for a register
106 unsigned getRegBinaryCode(unsigned reg) const;
107
108 /// \brief Generated function that returns the hardware encoding for
109 /// a register
110 unsigned getHWRegNum(unsigned reg) const;
111
11264 };
11365
11466 } // End anonymous namespace
12375 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
12476 SmallVectorImpl &Fixups) const {
12577 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
126 unsigned bytes = getEncodingBytes(MI);
78 unsigned bytes = MCII.get(MI.getOpcode()).getSize();
12779 for (unsigned i = 0; i < bytes; i++) {
12880 OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
12981 }
13385 const MCOperand &MO,
13486 SmallVectorImpl &Fixups) const {
13587 if (MO.isReg()) {
136 return getRegBinaryCode(MO.getReg());
88 return MRI.getEncodingValue(MO.getReg());
13789 } else if (MO.isImm()) {
13890 return MO.getImm();
13991 } else if (MO.isFPImm()) {
162114
163115 unsigned SIMCCodeEmitter::GPRAlign(const MCInst &MI, unsigned OpNo,
164116 unsigned shift) const {
165 unsigned regCode = getRegBinaryCode(MI.getOperand(OpNo).getReg());
166 return regCode >> shift;
167 return 0;
117 unsigned regCode = MRI.getEncodingValue(MI.getOperand(OpNo).getReg());
118 return (regCode & 0xff) >> shift;
168119 }
169120 unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
170121 unsigned OpNo ,
177128 SmallVectorImpl &Fixup) const {
178129 return GPRAlign(MI, OpNo, 2);
179130 }
180
181 //===----------------------------------------------------------------------===//
182 // Post Encoder Callbacks
183 //===----------------------------------------------------------------------===//
184
185 uint64_t SIMCCodeEmitter::VOPPostEncode(const MCInst &MI, uint64_t Value) const{
186 unsigned encodingType = getEncodingType(MI);
187 unsigned numSrcOps;
188 unsigned vgprBitOffset;
189
190 if (encodingType == SIInstrEncodingType::VOP3) {
191 numSrcOps = 3;
192 vgprBitOffset = 32;
193 } else {
194 numSrcOps = 1;
195 vgprBitOffset = 0;
196 }
197
198 // Add one to skip over the destination reg operand.
199 for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
200 const MCOperand &MO = MI.getOperand(opIdx);
201 if (MO.isReg()) {
202 unsigned reg = MI.getOperand(opIdx).getReg();
203 if (AMDGPUMCRegisterClasses[AMDGPU::VReg_32RegClassID].contains(reg) ||
204 AMDGPUMCRegisterClasses[AMDGPU::VReg_64RegClassID].contains(reg)) {
205 Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
206 }
207 } else if (MO.isFPImm()) {
208 union {
209 float f;
210 uint32_t i;
211 } Imm;
212 // XXX: Not all instructions can use inline literals
213 // XXX: We should make sure this is a 32-bit constant
214 Imm.f = MO.getFPImm();
215 Value |= ((uint64_t)Imm.i) << 32;
216 }
217 }
218 return Value;
219 }
220
221 //===----------------------------------------------------------------------===//
222 // Encoding helper functions
223 //===----------------------------------------------------------------------===//
224
225 unsigned SIMCCodeEmitter::getEncodingType(const MCInst &MI) const {
226 return MCII.get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
227 }
228
229 unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
230
231 // These instructions aren't real instructions with an encoding type, so
232 // we need to manually specify their size.
233 switch (MI.getOpcode()) {
234 default: break;
235 case AMDGPU::SI_LOAD_LITERAL_I32:
236 case AMDGPU::SI_LOAD_LITERAL_F32:
237 return 4;
238 }
239
240 unsigned encoding_type = getEncodingType(MI);
241 switch (encoding_type) {
242 case SIInstrEncodingType::EXP:
243 case SIInstrEncodingType::LDS:
244 case SIInstrEncodingType::MUBUF:
245 case SIInstrEncodingType::MTBUF:
246 case SIInstrEncodingType::MIMG:
247 case SIInstrEncodingType::VOP3:
248 return 8;
249 default:
250 return 4;
251 }
252 }
253
254
255 unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
256 switch (reg) {
257 case AMDGPU::M0: return 124;
258 case AMDGPU::SREG_LIT_0: return 128;
259 case AMDGPU::SI_LITERAL_CONSTANT: return 255;
260 default: return MRI.getEncodingValue(reg);
261 }
262 }
263
3333 MachineBasicBlock::iterator MI, DebugLoc DL,
3434 unsigned DestReg, unsigned SrcReg,
3535 bool KillSrc) const;
36
37 /// \returns the encoding type of this instruction.
38 unsigned getEncodingType(const MachineInstr &MI) const;
39
40 /// \returns the size of this instructions encoding in number of bytes.
41 unsigned getEncodingBytes(const MachineInstr &MI) const;
4236
4337 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
4438 int64_t Imm) const;
8074 namespace SIInstrFlags {
8175 enum Flags {
8276 // First 4 bits are the instruction encoding
83 VM_CNT = 1 << 4,
84 EXP_CNT = 1 << 5,
85 LGKM_CNT = 1 << 6
77 VM_CNT = 1 << 0,
78 EXP_CNT = 1 << 1,
79 LGKM_CNT = 1 << 2
8680 };
8781 }
8882
6969 class InstSI pattern> :
7070 AMDGPUInst {
7171
72 field bits<4> EncodingType = 0;
7372 field bits<1> VM_CNT = 0;
7473 field bits<1> EXP_CNT = 0;
7574 field bits<1> LGKM_CNT = 0;
7675
77 let TSFlags{3-0} = EncodingType;
78 let TSFlags{4} = VM_CNT;
79 let TSFlags{5} = EXP_CNT;
80 let TSFlags{6} = LGKM_CNT;
76 let TSFlags{0} = VM_CNT;
77 let TSFlags{1} = EXP_CNT;
78 let TSFlags{2} = LGKM_CNT;
8179 }
8280
8381 class Enc32 pattern> :
8482 InstSI {
8583
8684 field bits<32> Inst;
85 let Size = 4;
8786 }
8887
8988 class Enc64 pattern> :
9089 InstSI {
9190
9291 field bits<64> Inst;
92 let Size = 8;
9393 }
9494
9595 class SIOperand : Operand {
136136 let Inst{47-40} = VSRC1;
137137 let Inst{55-48} = VSRC2;
138138 let Inst{63-56} = VSRC3;
139 let EncodingType = 0; //SIInstrEncodingType::EXP
140139
141140 let EXP_CNT = 1;
142141 }
171170 let Inst{47-40} = VDATA;
172171 let Inst{52-48} = SRSRC;
173172 let Inst{57-53} = SSAMP;
174 let EncodingType = 2; //SIInstrEncodingType::MIMG
175173
176174 let VM_CNT = 1;
177175 let EXP_CNT = 1;
209207 let Inst{54} = SLC;
210208 let Inst{55} = TFE;
211209 let Inst{63-56} = SOFFSET;
212 let EncodingType = 3; //SIInstrEncodingType::MTBUF
213210
214211 let VM_CNT = 1;
215212 let EXP_CNT = 1;
247244 let Inst{54} = SLC;
248245 let Inst{55} = TFE;
249246 let Inst{63-56} = SOFFSET;
250 let EncodingType = 4; //SIInstrEncodingType::MUBUF
251247
252248 let VM_CNT = 1;
253249 let EXP_CNT = 1;
270266 let Inst{21-15} = SDST;
271267 let Inst{26-22} = op;
272268 let Inst{31-27} = 0x18; //encoding
273 let EncodingType = 5; //SIInstrEncodingType::SMRD
274269
275270 let LGKM_CNT = 1;
276271 }
285280 let Inst{15-8} = op;
286281 let Inst{22-16} = SDST;
287282 let Inst{31-23} = 0x17d; //encoding;
288 let EncodingType = 6; //SIInstrEncodingType::SOP1
289283
290284 let mayLoad = 0;
291285 let mayStore = 0;
304298 let Inst{22-16} = SDST;
305299 let Inst{29-23} = op;
306300 let Inst{31-30} = 0x2; // encoding
307 let EncodingType = 7; // SIInstrEncodingType::SOP2
308301
309302 let mayLoad = 0;
310303 let mayStore = 0;
321314 let Inst{15-8} = SSRC1;
322315 let Inst{22-16} = op;
323316 let Inst{31-23} = 0x17e;
324 let EncodingType = 8; // SIInstrEncodingType::SOPC
325317
326318 let DisableEncoding = "$dst";
327319 let mayLoad = 0;
339331 let Inst{22-16} = SDST;
340332 let Inst{27-23} = op;
341333 let Inst{31-28} = 0xb; //encoding
342 let EncodingType = 9; // SIInstrEncodingType::SOPK
343334
344335 let mayLoad = 0;
345336 let mayStore = 0;
357348 let Inst{15-0} = SIMM16;
358349 let Inst{22-16} = op;
359350 let Inst{31-23} = 0x17f; // encoding
360 let EncodingType = 10; // SIInstrEncodingType::SOPP
361351
362352 let mayLoad = 0;
363353 let mayStore = 0;
380370 let Inst{17-16} = op;
381371 let Inst{25-18} = VDST;
382372 let Inst{31-26} = 0x32; // encoding
383 let EncodingType = 11; // SIInstrEncodingType::VINTRP
384373
385374 let neverHasSideEffects = 1;
386375 let mayLoad = 1;
398387 let Inst{24-17} = VDST;
399388 let Inst{31-25} = 0x3f; //encoding
400389
401 let EncodingType = 12; // SIInstrEncodingType::VOP1
402 let PostEncoderMethod = "VOPPostEncode";
403
404390 let mayLoad = 0;
405391 let mayStore = 0;
406392 let hasSideEffects = 0;
419405 let Inst{30-25} = op;
420406 let Inst{31} = 0x0; //encoding
421407
422 let EncodingType = 13; // SIInstrEncodingType::VOP2
423 let PostEncoderMethod = "VOPPostEncode";
424
425408 let mayLoad = 0;
426409 let mayStore = 0;
427410 let hasSideEffects = 0;
450433 let Inst{60-59} = OMOD;
451434 let Inst{63-61} = NEG;
452435
453 let EncodingType = 14; // SIInstrEncodingType::VOP3
454 let PostEncoderMethod = "VOPPostEncode";
455
456436 let mayLoad = 0;
457437 let mayStore = 0;
458438 let hasSideEffects = 0;
479459 let Inst{60-59} = OMOD;
480460 let Inst{63-61} = NEG;
481461
482 let EncodingType = 14; // SIInstrEncodingType::VOP3
483 let PostEncoderMethod = "VOPPostEncode";
484
485462 let mayLoad = 0;
486463 let mayStore = 0;
487464 let hasSideEffects = 0;
498475 let Inst{24-17} = op;
499476 let Inst{31-25} = 0x3e;
500477
501 let EncodingType = 15; //SIInstrEncodingType::VOPC
502 let PostEncoderMethod = "VOPPostEncode";
503478 let DisableEncoding = "$dst";
504479 let mayLoad = 0;
505480 let mayStore = 0;
1111
1212 class SGPR_32 num, string name> : SIReg;
1313
14 class VGPR_32 num, string name> : SIReg;
14 class VGPR_32 num, string name> : SIReg {
15 let HWEncoding{8} = 1;
16 }
1517
1618 // Special Registers
1719 def VCC : SIReg<"VCC", 106>;