llvm.org GIT mirror llvm / 1836fe5
Rename a DebugLoc variable to DbgLoc and a DataLayout to DL. This is quiet a bit less confusing now that TargetData was renamed DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201606 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 5 years ago
6 changed file(s) with 397 addition(s) and 368 deletion(s). Raw diff Collapse all Expand all
5050 MachineRegisterInfo &MRI;
5151 MachineFrameInfo &MFI;
5252 MachineConstantPool &MCP;
53 DebugLoc DL;
53 DebugLoc DbgLoc;
5454 const TargetMachine &TM;
55 const DataLayout &TD;
55 const DataLayout &DL;
5656 const TargetInstrInfo &TII;
5757 const TargetLowering &TLI;
5858 const TargetRegisterInfo &TRI;
8686 void startNewBlock();
8787
8888 /// Return current debug location information.
89 DebugLoc getCurDebugLoc() const { return DL; }
89 DebugLoc getCurDebugLoc() const { return DbgLoc; }
9090
9191 /// Do "fast" instruction selection for function arguments and append machine
9292 /// instructions to the current block. Return true if it is successful.
117117
118118 // No-op casts are trivially coalesced by fast-isel.
119119 if (const CastInst *Cast = dyn_cast(I))
120 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) &&
120 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
121121 !hasTrivialKill(Cast->getOperand(0)))
122122 return false;
123123
191191 // Translate this as an integer zero so that it can be
192192 // local-CSE'd with actual integer zeros.
193193 Reg =
194 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
194 getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getContext())));
195195 } else if (const ConstantFP *CF = dyn_cast(V)) {
196196 if (CF->isNullValue()) {
197197 Reg = TargetMaterializeFloatZero(CF);
228228 Reg = lookUpRegForValue(Op);
229229 } else if (isa(V)) {
230230 Reg = createResultReg(TLI.getRegClassFor(VT));
231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
232232 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
233233 }
234234
334334
335335 FastISel::SavePoint FastISel::enterLocalValueArea() {
336336 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
337 DebugLoc OldDL = DL;
337 DebugLoc OldDL = DbgLoc;
338338 recomputeInsertPt();
339 DL = DebugLoc();
339 DbgLoc = DebugLoc();
340340 SavePoint SP = { OldInsertPt, OldDL };
341341 return SP;
342342 }
347347
348348 // Restore the previous insert position.
349349 FuncInfo.InsertPt = OldInsertPt.InsertPt;
350 DL = OldInsertPt.DL;
350 DbgLoc = OldInsertPt.DL;
351351 }
352352
353353 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
483483 unsigned Field = cast(Idx)->getZExtValue();
484484 if (Field) {
485485 // N = N + Offset
486 TotalOffs += TD.getStructLayout(StTy)->getElementOffset(Field);
486 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
487487 if (TotalOffs >= MaxOffs) {
488488 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
489489 if (N == 0)
502502 if (CI->isZero()) continue;
503503 // N = N + Offset
504504 TotalOffs +=
505 TD.getTypeAllocSize(Ty)*cast(CI)->getSExtValue();
505 DL.getTypeAllocSize(Ty)*cast(CI)->getSExtValue();
506506 if (TotalOffs >= MaxOffs) {
507507 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
508508 if (N == 0)
523523 }
524524
525525 // N = N + Idx * ElementSize;
526 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
526 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
527527 std::pair Pair = getRegForGEPIndex(Idx);
528528 unsigned IdxN = Pair.first;
529529 bool IdxNIsKill = Pair.second;
571571 if (IA->isAlignStack())
572572 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
573573
574 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
574 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
575575 TII.get(TargetOpcode::INLINEASM))
576576 .addExternalSymbol(IA->getAsmString().c_str())
577577 .addImm(ExtraInfo);
642642 if (Op) {
643643 if (Op->isReg()) {
644644 Op->setIsDebug(true);
645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
646646 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
647647 DI->getVariable());
648648 } else
649 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
649 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
650650 TII.get(TargetOpcode::DBG_VALUE))
651651 .addOperand(*Op)
652652 .addImm(0)
666666 if (!V) {
667667 // Currently the optimizer can produce this; insert an undef to
668668 // help debugging. Probably the optimizer should not do this.
669 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
669 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
670670 .addReg(0U).addImm(DI->getOffset())
671671 .addMetadata(DI->getVariable());
672672 } else if (const ConstantInt *CI = dyn_cast(V)) {
673673 if (CI->getBitWidth() > 64)
674 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
674 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
675675 .addCImm(CI).addImm(DI->getOffset())
676676 .addMetadata(DI->getVariable());
677677 else
678 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
678 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
679679 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
680680 .addMetadata(DI->getVariable());
681681 } else if (const ConstantFP *CF = dyn_cast(V)) {
682 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
682 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
683683 .addFPImm(CF).addImm(DI->getOffset())
684684 .addMetadata(DI->getVariable());
685685 } else if (unsigned Reg = lookUpRegForValue(V)) {
686686 // FIXME: This does not handle register-indirect values at offset 0.
687687 bool IsIndirect = DI->getOffset() != 0;
688 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, IsIndirect,
688 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect,
689689 Reg, DI->getOffset(), DI->getVariable());
690690 } else {
691691 // We can't yet handle anything else here because it would require
797797 // Don't attempt a cross-class copy. It will likely fail.
798798 if (SrcClass == DstClass) {
799799 ResultReg = createResultReg(DstClass);
800 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
801 ResultReg).addReg(Op0);
800 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
801 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
802802 }
803803 }
804804
821821 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
822822 return false;
823823
824 DL = I->getDebugLoc();
824 DbgLoc = I->getDebugLoc();
825825
826826 MachineBasicBlock::iterator SavedInsertPt = FuncInfo.InsertPt;
827827
839839 // First, try doing target-independent selection.
840840 if (SelectOperator(I, I->getOpcode())) {
841841 ++NumFastIselSuccessIndependent;
842 DL = DebugLoc();
842 DbgLoc = DebugLoc();
843843 return true;
844844 }
845845 // Remove dead code. However, ignore call instructions since we've flushed
854854 SavedInsertPt = FuncInfo.InsertPt;
855855 if (TargetSelectInstruction(I)) {
856856 ++NumFastIselSuccessTarget;
857 DL = DebugLoc();
857 DbgLoc = DebugLoc();
858858 return true;
859859 }
860860 // Check for dead code and remove as necessary.
862862 if (SavedInsertPt != FuncInfo.InsertPt)
863863 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
864864
865 DL = DebugLoc();
865 DbgLoc = DebugLoc();
866866 return false;
867867 }
868868
870870 /// unless it is the immediate (fall-through) successor, and update
871871 /// the CFG.
872872 void
873 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
873 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
874874
875875 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
876876 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
880880 } else {
881881 // The unconditional branch case.
882882 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
883 SmallVector(), DL);
883 SmallVector(), DbgLoc);
884884 }
885885 FuncInfo.MBB->addSuccessor(MSucc);
886886 }
10951095 MFI(*FuncInfo.MF->getFrameInfo()),
10961096 MCP(*FuncInfo.MF->getConstantPool()),
10971097 TM(FuncInfo.MF->getTarget()),
1098 TD(*TM.getDataLayout()),
1098 DL(*TM.getDataLayout()),
10991099 TII(*TM.getInstrInfo()),
11001100 TLI(*TM.getTargetLowering()),
11011101 TRI(*TM.getRegisterInfo()),
12081208 unsigned ResultReg = createResultReg(RC);
12091209 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12101210
1211 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
1211 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
12121212 return ResultReg;
12131213 }
12141214
12191219 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12201220
12211221 if (II.getNumDefs() >= 1)
1222 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1222 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
12231223 .addReg(Op0, Op0IsKill * RegState::Kill);
12241224 else {
1225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
12261226 .addReg(Op0, Op0IsKill * RegState::Kill);
1227 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1228 ResultReg).addReg(II.ImplicitDefs[0]);
1227 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1228 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
12291229 }
12301230
12311231 return ResultReg;
12391239 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12401240
12411241 if (II.getNumDefs() >= 1)
1242 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1242 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
12431243 .addReg(Op0, Op0IsKill * RegState::Kill)
12441244 .addReg(Op1, Op1IsKill * RegState::Kill);
12451245 else {
1246 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1246 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
12471247 .addReg(Op0, Op0IsKill * RegState::Kill)
12481248 .addReg(Op1, Op1IsKill * RegState::Kill);
1249 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1250 ResultReg).addReg(II.ImplicitDefs[0]);
1249 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1250 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
12511251 }
12521252 return ResultReg;
12531253 }
12611261 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12621262
12631263 if (II.getNumDefs() >= 1)
1264 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1264 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
12651265 .addReg(Op0, Op0IsKill * RegState::Kill)
12661266 .addReg(Op1, Op1IsKill * RegState::Kill)
12671267 .addReg(Op2, Op2IsKill * RegState::Kill);
12681268 else {
1269 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1269 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
12701270 .addReg(Op0, Op0IsKill * RegState::Kill)
12711271 .addReg(Op1, Op1IsKill * RegState::Kill)
12721272 .addReg(Op2, Op2IsKill * RegState::Kill);
1273 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1274 ResultReg).addReg(II.ImplicitDefs[0]);
1273 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1274 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
12751275 }
12761276 return ResultReg;
12771277 }
12841284 const MCInstrDesc &II = TII.get(MachineInstOpcode);
12851285
12861286 if (II.getNumDefs() >= 1)
1287 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1287 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
12881288 .addReg(Op0, Op0IsKill * RegState::Kill)
12891289 .addImm(Imm);
12901290 else {
1291 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1291 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
12921292 .addReg(Op0, Op0IsKill * RegState::Kill)
12931293 .addImm(Imm);
1294 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1295 ResultReg).addReg(II.ImplicitDefs[0]);
1294 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1295 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
12961296 }
12971297 return ResultReg;
12981298 }
13051305 const MCInstrDesc &II = TII.get(MachineInstOpcode);
13061306
13071307 if (II.getNumDefs() >= 1)
1308 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1308 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
13091309 .addReg(Op0, Op0IsKill * RegState::Kill)
13101310 .addImm(Imm1)
13111311 .addImm(Imm2);
13121312 else {
1313 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1313 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
13141314 .addReg(Op0, Op0IsKill * RegState::Kill)
13151315 .addImm(Imm1)
13161316 .addImm(Imm2);
1317 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1318 ResultReg).addReg(II.ImplicitDefs[0]);
1317 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1318 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
13191319 }
13201320 return ResultReg;
13211321 }
13281328 const MCInstrDesc &II = TII.get(MachineInstOpcode);
13291329
13301330 if (II.getNumDefs() >= 1)
1331 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1331 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
13321332 .addReg(Op0, Op0IsKill * RegState::Kill)
13331333 .addFPImm(FPImm);
13341334 else {
1335 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1335 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
13361336 .addReg(Op0, Op0IsKill * RegState::Kill)
13371337 .addFPImm(FPImm);
1338 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1339 ResultReg).addReg(II.ImplicitDefs[0]);
1338 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1339 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
13401340 }
13411341 return ResultReg;
13421342 }
13501350 const MCInstrDesc &II = TII.get(MachineInstOpcode);
13511351
13521352 if (II.getNumDefs() >= 1)
1353 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1353 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
13541354 .addReg(Op0, Op0IsKill * RegState::Kill)
13551355 .addReg(Op1, Op1IsKill * RegState::Kill)
13561356 .addImm(Imm);
13571357 else {
1358 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1358 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
13591359 .addReg(Op0, Op0IsKill * RegState::Kill)
13601360 .addReg(Op1, Op1IsKill * RegState::Kill)
13611361 .addImm(Imm);
1362 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1363 ResultReg).addReg(II.ImplicitDefs[0]);
1362 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1363 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
13641364 }
13651365 return ResultReg;
13661366 }
13741374 const MCInstrDesc &II = TII.get(MachineInstOpcode);
13751375
13761376 if (II.getNumDefs() >= 1)
1377 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1377 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
13781378 .addReg(Op0, Op0IsKill * RegState::Kill)
13791379 .addReg(Op1, Op1IsKill * RegState::Kill)
13801380 .addImm(Imm1).addImm(Imm2);
13811381 else {
1382 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1382 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
13831383 .addReg(Op0, Op0IsKill * RegState::Kill)
13841384 .addReg(Op1, Op1IsKill * RegState::Kill)
13851385 .addImm(Imm1).addImm(Imm2);
1386 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1387 ResultReg).addReg(II.ImplicitDefs[0]);
1386 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1387 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
13881388 }
13891389 return ResultReg;
13901390 }
13961396 const MCInstrDesc &II = TII.get(MachineInstOpcode);
13971397
13981398 if (II.getNumDefs() >= 1)
1399 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
1399 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg).addImm(Imm);
14001400 else {
1401 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
1402 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1403 ResultReg).addReg(II.ImplicitDefs[0]);
1401 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1402 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1403 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
14041404 }
14051405 return ResultReg;
14061406 }
14121412 const MCInstrDesc &II = TII.get(MachineInstOpcode);
14131413
14141414 if (II.getNumDefs() >= 1)
1415 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1415 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
14161416 .addImm(Imm1).addImm(Imm2);
14171417 else {
1418 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2);
1419 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1420 ResultReg).addReg(II.ImplicitDefs[0]);
1418 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1).addImm(Imm2);
1419 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1420 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
14211421 }
14221422 return ResultReg;
14231423 }
14311431 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
14321432 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
14331433 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1434 DL, TII.get(TargetOpcode::COPY), ResultReg)
1434 DbgLoc, TII.get(TargetOpcode::COPY), ResultReg)
14351435 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
14361436 return ResultReg;
14371437 }
14971497
14981498 // Set the DebugLoc for the copy. Prefer the location of the operand
14991499 // if there is one; use the location of the PHI otherwise.
1500 DL = PN->getDebugLoc();
1500 DbgLoc = PN->getDebugLoc();
15011501 if (const Instruction *Inst = dyn_cast(PHIOp))
1502 DL = Inst->getDebugLoc();
1502 DbgLoc = Inst->getDebugLoc();
15031503
15041504 unsigned Reg = getRegForValue(PHIOp);
15051505 if (Reg == 0) {
15071507 return false;
15081508 }
15091509 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
1510 DL = DebugLoc();
1510 DbgLoc = DebugLoc();
15111511 }
15121512 }
15131513
15751575 if (!isa(Add))
15761576 return false;
15771577 // Type size needs to match.
1578 if (TD.getTypeSizeInBits(GEP->getType()) !=
1579 TD.getTypeSizeInBits(Add->getType()))
1578 if (DL.getTypeSizeInBits(GEP->getType()) !=
1579 DL.getTypeSizeInBits(Add->getType()))
15801580 return false;
15811581 // Must be in the same basic block.
15821582 if (isa(Add) &&
303303 // If it's not legal to COPY between the register classes, something
304304 // has gone very wrong before we got here.
305305 unsigned NewOp = createResultReg(RegClass);
306 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
306 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
307307 TII.get(TargetOpcode::COPY), NewOp).addReg(Op));
308308 return NewOp;
309309 }
316316 unsigned ResultReg = createResultReg(RC);
317317 const MCInstrDesc &II = TII.get(MachineInstOpcode);
318318
319 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
319 AddOptionalDefs(
320 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg));
320321 return ResultReg;
321322 }
322323
330331 // for this instruction.
331332 Op0 = constrainOperandRegClass(II, Op0, 1);
332333 if (II.getNumDefs() >= 1) {
333 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
334 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
335 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
336 } else {
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
334338 .addReg(Op0, Op0IsKill * RegState::Kill));
335 } else {
336 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
337 .addReg(Op0, Op0IsKill * RegState::Kill));
338 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
339 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
339340 TII.get(TargetOpcode::COPY), ResultReg)
340341 .addReg(II.ImplicitDefs[0]));
341342 }
355356 Op1 = constrainOperandRegClass(II, Op1, 2);
356357
357358 if (II.getNumDefs() >= 1) {
358 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
359 AddOptionalDefs(
360 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
361 .addReg(Op0, Op0IsKill * RegState::Kill)
362 .addReg(Op1, Op1IsKill * RegState::Kill));
363 } else {
364 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
359365 .addReg(Op0, Op0IsKill * RegState::Kill)
360366 .addReg(Op1, Op1IsKill * RegState::Kill));
361 } else {
362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
363 .addReg(Op0, Op0IsKill * RegState::Kill)
364 .addReg(Op1, Op1IsKill * RegState::Kill));
365 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
367 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
366368 TII.get(TargetOpcode::COPY), ResultReg)
367369 .addReg(II.ImplicitDefs[0]));
368370 }
384386 Op2 = constrainOperandRegClass(II, Op1, 3);
385387
386388 if (II.getNumDefs() >= 1) {
387 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
389 AddOptionalDefs(
390 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
391 .addReg(Op0, Op0IsKill * RegState::Kill)
392 .addReg(Op1, Op1IsKill * RegState::Kill)
393 .addReg(Op2, Op2IsKill * RegState::Kill));
394 } else {
395 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
388396 .addReg(Op0, Op0IsKill * RegState::Kill)
389397 .addReg(Op1, Op1IsKill * RegState::Kill)
390398 .addReg(Op2, Op2IsKill * RegState::Kill));
391 } else {
392 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
393 .addReg(Op0, Op0IsKill * RegState::Kill)
394 .addReg(Op1, Op1IsKill * RegState::Kill)
395 .addReg(Op2, Op2IsKill * RegState::Kill));
396 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
399 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
397400 TII.get(TargetOpcode::COPY), ResultReg)
398401 .addReg(II.ImplicitDefs[0]));
399402 }
411414 // for this instruction.
412415 Op0 = constrainOperandRegClass(II, Op0, 1);
413416 if (II.getNumDefs() >= 1) {
414 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
417 AddOptionalDefs(
418 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
419 .addReg(Op0, Op0IsKill * RegState::Kill)
420 .addImm(Imm));
421 } else {
422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
415423 .addReg(Op0, Op0IsKill * RegState::Kill)
416424 .addImm(Imm));
417 } else {
418 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
419 .addReg(Op0, Op0IsKill * RegState::Kill)
420 .addImm(Imm));
421 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
425 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
422426 TII.get(TargetOpcode::COPY), ResultReg)
423427 .addReg(II.ImplicitDefs[0]));
424428 }
436440 // for this instruction.
437441 Op0 = constrainOperandRegClass(II, Op0, 1);
438442 if (II.getNumDefs() >= 1) {
439 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
443 AddOptionalDefs(
444 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
445 .addReg(Op0, Op0IsKill * RegState::Kill)
446 .addFPImm(FPImm));
447 } else {
448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
440449 .addReg(Op0, Op0IsKill * RegState::Kill)
441450 .addFPImm(FPImm));
442 } else {
443 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
444 .addReg(Op0, Op0IsKill * RegState::Kill)
445 .addFPImm(FPImm));
446 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
447452 TII.get(TargetOpcode::COPY), ResultReg)
448453 .addReg(II.ImplicitDefs[0]));
449454 }
463468 Op0 = constrainOperandRegClass(II, Op0, 1);
464469 Op1 = constrainOperandRegClass(II, Op1, 2);
465470 if (II.getNumDefs() >= 1) {
466 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
471 AddOptionalDefs(
472 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
473 .addReg(Op0, Op0IsKill * RegState::Kill)
474 .addReg(Op1, Op1IsKill * RegState::Kill)
475 .addImm(Imm));
476 } else {
477 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
467478 .addReg(Op0, Op0IsKill * RegState::Kill)
468479 .addReg(Op1, Op1IsKill * RegState::Kill)
469480 .addImm(Imm));
470 } else {
471 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
472 .addReg(Op0, Op0IsKill * RegState::Kill)
473 .addReg(Op1, Op1IsKill * RegState::Kill)
474 .addImm(Imm));
475 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
481 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
476482 TII.get(TargetOpcode::COPY), ResultReg)
477483 .addReg(II.ImplicitDefs[0]));
478484 }
486492 const MCInstrDesc &II = TII.get(MachineInstOpcode);
487493
488494 if (II.getNumDefs() >= 1) {
489 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
495 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
496 ResultReg).addImm(Imm));
497 } else {
498 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
490499 .addImm(Imm));
491 } else {
492 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
493 .addImm(Imm));
494 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
500 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
495501 TII.get(TargetOpcode::COPY), ResultReg)
496502 .addReg(II.ImplicitDefs[0]));
497503 }
505511 const MCInstrDesc &II = TII.get(MachineInstOpcode);
506512
507513 if (II.getNumDefs() >= 1) {
508 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
514 AddOptionalDefs(
515 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
516 .addImm(Imm1)
517 .addImm(Imm2));
518 } else {
519 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
509520 .addImm(Imm1).addImm(Imm2));
510 } else {
511 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
512 .addImm(Imm1).addImm(Imm2));
513 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
521 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
514522 TII.get(TargetOpcode::COPY),
515523 ResultReg)
516524 .addReg(II.ImplicitDefs[0]));
526534 "Cannot yet extract from physregs");
527535
528536 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
529 DL, TII.get(TargetOpcode::COPY), ResultReg)
537 DbgLoc, TII.get(TargetOpcode::COPY), ResultReg)
530538 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
531539 return ResultReg;
532540 }
537545 if (VT == MVT::f64) return 0;
538546
539547 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
540 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
548 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
541549 TII.get(ARM::VMOVSR), MoveReg)
542550 .addReg(SrcReg));
543551 return MoveReg;
547555 if (VT == MVT::i64) return 0;
548556
549557 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
550 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
558 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
551559 TII.get(ARM::VMOVRS), MoveReg)
552560 .addReg(SrcReg));
553561 return MoveReg;
573581 Opc = ARM::FCONSTS;
574582 }
575583 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
576 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
577 DestReg)
578 .addImm(Imm));
584 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
585 TII.get(Opc), DestReg).addImm(Imm));
579586 return DestReg;
580587 }
581588
583590 if (!Subtarget->hasVFP2()) return false;
584591
585592 // MachineConstantPool wants an explicit alignment.
586 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
593 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
587594 if (Align == 0) {
588595 // TODO: Figure out if this is correct.
589 Align = TD.getTypeAllocSize(CFP->getType());
596 Align = DL.getTypeAllocSize(CFP->getType());
590597 }
591598 unsigned Idx = MCP.getConstantPoolIndex(cast(CFP), Align);
592599 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
593600 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
594601
595602 // The extra reg is for addrmode5.
596 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
597 DestReg)
598 .addConstantPoolIndex(Idx)
599 .addReg(0));
603 AddOptionalDefs(
604 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
605 .addConstantPoolIndex(Idx)
606 .addReg(0));
600607 return DestReg;
601608 }
602609
613620 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
614621 &ARM::GPRRegClass;
615622 unsigned ImmReg = createResultReg(RC);
616 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
623 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
617624 TII.get(Opc), ImmReg)
618625 .addImm(CI->getZExtValue()));
619626 return ImmReg;
627634 if (UseImm) {
628635 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
629636 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
630 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
637 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
631638 TII.get(Opc), ImmReg)
632639 .addImm(Imm));
633640 return ImmReg;
641648 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
642649
643650 // MachineConstantPool wants an explicit alignment.
644 unsigned Align = TD.getPrefTypeAlignment(C->getType());
651 unsigned Align = DL.getPrefTypeAlignment(C->getType());
645652 if (Align == 0) {
646653 // TODO: Figure out if this is correct.
647 Align = TD.getTypeAllocSize(C->getType());
654 Align = DL.getTypeAllocSize(C->getType());
648655 }
649656 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
650657
651658 if (isThumb2)
652 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
659 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
653660 TII.get(ARM::t2LDRpci), DestReg)
654661 .addConstantPoolIndex(Idx));
655662 else {
656663 // The extra immediate is for addrmode2.
657664 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
658 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
665 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
659666 TII.get(ARM::LDRcp), DestReg)
660667 .addConstantPoolIndex(Idx)
661668 .addImm(0));
697704 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
698705 break;
699706 }
700 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
701 DestReg).addGlobalAddress(GV, 0, TF));
707 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
708 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
702709 } else {
703710 // MachineConstantPool wants an explicit alignment.
704 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
711 unsigned Align = DL.getPrefTypeAlignment(GV->getType());
705712 if (Align == 0) {
706713 // TODO: Figure out if this is correct.
707 Align = TD.getTypeAllocSize(GV->getType());
714 Align = DL.getTypeAllocSize(GV->getType());
708715 }
709716
710717 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
723730 MachineInstrBuilder MIB;
724731 if (isThumb2) {
725732 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
726 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
727 .addConstantPoolIndex(Idx);
733 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
734 DestReg).addConstantPoolIndex(Idx);
728735 if (RelocM == Reloc::PIC_)
729736 MIB.addImm(Id);
730737 AddOptionalDefs(MIB);
731738 } else {
732739 // The extra immediate is for addrmode2.
733740 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
734 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
735 DestReg)
736 .addConstantPoolIndex(Idx)
737 .addImm(0);
741 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
742 TII.get(ARM::LDRcp), DestReg)
743 .addConstantPoolIndex(Idx)
744 .addImm(0);
738745 AddOptionalDefs(MIB);
739746
740747 if (RelocM == Reloc::PIC_) {
742749 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
743750
744751 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
745 DL, TII.get(Opc), NewDestReg)
752 DbgLoc, TII.get(Opc), NewDestReg)
746753 .addReg(DestReg)
747754 .addImm(Id);
748755 AddOptionalDefs(MIB);
755762 MachineInstrBuilder MIB;
756763 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
757764 if (isThumb2)
758 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
765 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
759766 TII.get(ARM::t2LDRi12), NewDestReg)
760767 .addReg(DestReg)
761768 .addImm(0);
762769 else
763 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
764 NewDestReg)
765 .addReg(DestReg)
766 .addImm(0);
770 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
771 TII.get(ARM::LDRi12), NewDestReg)
772 .addReg(DestReg)
773 .addImm(0);
767774 DestReg = NewDestReg;
768775 AddOptionalDefs(MIB);
769776 }
808815 unsigned ResultReg = createResultReg(RC);
809816 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
810817
811 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
818 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
812819 TII.get(Opc), ResultReg)
813820 .addFrameIndex(SI->second)
814821 .addImm(0));
892899 i != e; ++i, ++GTI) {
893900 const Value *Op = *i;
894901 if (StructType *STy = dyn_cast(*GTI)) {
895 const StructLayout *SL = TD.getStructLayout(STy);
902 const StructLayout *SL = DL.getStructLayout(STy);
896903 unsigned Idx = cast(Op)->getZExtValue();
897904 TmpOffset += SL->getElementOffset(Idx);
898905 } else {
899 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
906 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
900907 for (;;) {
901908 if (const ConstantInt *CI = dyn_cast(Op)) {
902909 // Constant-offset addressing.
982989 (const TargetRegisterClass*)&ARM::GPRRegClass;
983990 unsigned ResultReg = createResultReg(RC);
984991 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
985 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
992 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
986993 TII.get(Opc), ResultReg)
987994 .addFrameIndex(Addr.Base.FI)
988995 .addImm(0));
11331140 if (allocReg)
11341141 ResultReg = createResultReg(RC);
11351142 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1136 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1143 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
11371144 TII.get(Opc), ResultReg);
11381145 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
11391146
11411148 // load. Now we must move from the GRP to the FP register.
11421149 if (needVMOV) {
11431150 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1144 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1151 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
11451152 TII.get(ARM::VMOVSR), MoveReg)
11461153 .addReg(ResultReg));
11471154 ResultReg = MoveReg;
11831190 (const TargetRegisterClass*)&ARM::GPRRegClass);
11841191 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
11851192 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1186 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1193 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
11871194 TII.get(Opc), Res)
11881195 .addReg(SrcReg).addImm(1));
11891196 SrcReg = Res;
12301237 // Unaligned stores need special handling. Floats require word-alignment.
12311238 if (Alignment && Alignment < 4) {
12321239 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1233 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1240 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
12341241 TII.get(ARM::VMOVRS), MoveReg)
12351242 .addReg(SrcReg));
12361243 SrcReg = MoveReg;
12551262
12561263 // Create the base instruction, then add the operands.
12571264 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1258 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1265 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
12591266 TII.get(StrOpc))
12601267 .addReg(SrcReg);
12611268 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
13661373 return false;
13671374
13681375 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1369 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1376 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
13701377 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1371 FastEmitBranch(FBB, DL);
1378 FastEmitBranch(FBB, DbgLoc);
13721379 FuncInfo.MBB->addSuccessor(TBB);
13731380 return true;
13741381 }
13791386 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
13801387 unsigned OpReg = getRegForValue(TI->getOperand(0));
13811388 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1382 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1389 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
13831390 TII.get(TstOpc))
13841391 .addReg(OpReg).addImm(1));
13851392
13901397 }
13911398
13921399 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1393 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1400 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
13941401 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
13951402
1396 FastEmitBranch(FBB, DL);
1403 FastEmitBranch(FBB, DbgLoc);
13971404 FuncInfo.MBB->addSuccessor(TBB);
13981405 return true;
13991406 }
14011408 dyn_cast(BI->getCondition())) {
14021409 uint64_t Imm = CI->getZExtValue();
14031410 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1404 FastEmitBranch(Target, DL);
1411 FastEmitBranch(Target, DbgLoc);
14051412 return true;
14061413 }
14071414
14171424 // the one-bit value left in the virtual register.
14181425 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
14191426 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1420 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1421 .addReg(CmpReg).addImm(1));
1427 AddOptionalDefs(
1428 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1429 .addReg(CmpReg)
1430 .addImm(1));
14221431
14231432 unsigned CCMode = ARMCC::NE;
14241433 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
14271436 }
14281437
14291438 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1430 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1439 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
14311440 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1432 FastEmitBranch(FBB, DL);
1441 FastEmitBranch(FBB, DbgLoc);
14331442 FuncInfo.MBB->addSuccessor(TBB);
14341443 return true;
14351444 }
14391448 if (AddrReg == 0) return false;
14401449
14411450 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1442 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1443 .addReg(AddrReg));
1451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1452 TII.get(Opc)).addReg(AddrReg));
14441453
14451454 const IndirectBrInst *IB = cast(I);
14461455 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
15451554 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
15461555 if (!UseImm) {
15471556 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1548 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1557 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
15491558 .addReg(SrcReg1).addReg(SrcReg2));
15501559 } else {
15511560 MachineInstrBuilder MIB;
1552 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1561 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
15531562 .addReg(SrcReg1);
15541563
15551564 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
15611570 // For floating point we need to move the result to a comparison register
15621571 // that we can then use for branches.
15631572 if (Ty->isFloatTy() || Ty->isDoubleTy())
1564 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1573 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
15651574 TII.get(ARM::FMSTAT)));
15661575 return true;
15671576 }
15891598 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
15901599 unsigned ZeroReg = TargetMaterializeConstant(Zero);
15911600 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1592 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1601 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
15931602 .addReg(ZeroReg).addImm(1)
15941603 .addImm(ARMPred).addReg(ARM::CPSR);
15951604
16091618 if (Op == 0) return false;
16101619
16111620 unsigned Result = createResultReg(&ARM::DPRRegClass);
1612 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1621 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
16131622 TII.get(ARM::VCVTDS), Result)
16141623 .addReg(Op));
16151624 UpdateValueMap(I, Result);
16281637 if (Op == 0) return false;
16291638
16301639 unsigned Result = createResultReg(&ARM::SPRRegClass);
1631 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1640 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
16321641 TII.get(ARM::VCVTSD), Result)
16331642 .addReg(Op));
16341643 UpdateValueMap(I, Result);
16731682 else return false;
16741683
16751684 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1676 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1677 ResultReg)
1678 .addReg(FP));
1685 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1686 TII.get(Opc), ResultReg).addReg(FP));
16791687 UpdateValueMap(I, ResultReg);
16801688 return true;
16811689 }
17001708
17011709 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
17021710 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1703 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1704 ResultReg)
1705 .addReg(Op));
1711 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1712 TII.get(Opc), ResultReg).addReg(Op));
17061713
17071714 // This result needs to be in an integer register, but the conversion only
17081715 // takes place in fp-regs.
17491756
17501757 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
17511758 CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
1752 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1753 .addReg(CondReg).addImm(0));
1759 AddOptionalDefs(
1760 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
1761 .addReg(CondReg)
1762 .addImm(0));
17541763
17551764 unsigned MovCCOpc;
17561765 const TargetRegisterClass *RC;
17681777 if (!UseImm) {
17691778 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
17701779 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1771 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1772 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1780 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1781 ResultReg)
1782 .addReg(Op2Reg)
1783 .addReg(Op1Reg)
1784 .addImm(ARMCC::NE)
1785 .addReg(ARM::CPSR);
17731786 } else {
17741787 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1775 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1776 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1788 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1789 ResultReg)
1790 .addReg(Op1Reg)
1791 .addImm(Imm)
1792 .addImm(ARMCC::EQ)
1793 .addReg(ARM::CPSR);
17771794 }
17781795 UpdateValueMap(I, ResultReg);
17791796 return true;
18621879 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
18631880 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
18641881 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1865 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1882 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
18661883 TII.get(Opc), ResultReg)
18671884 .addReg(SrcReg1).addReg(SrcReg2));
18681885 UpdateValueMap(I, ResultReg);
19041921 if (Op2 == 0) return false;
19051922
19061923 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1907 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1924 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
19081925 TII.get(Opc), ResultReg)
19091926 .addReg(Op1).addReg(Op2));
19101927 UpdateValueMap(I, ResultReg);
20162033
20172034 // Issue CALLSEQ_START
20182035 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2019 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2036 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
20202037 TII.get(AdjStackDown))
20212038 .addImm(NumBytes));
20222039
20612078
20622079 // Now copy/store arg to correct locations.
20632080 if (VA.isRegLoc() && !VA.needsCustom()) {
2064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2065 VA.getLocReg())
2066 .addReg(Arg);
2081 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2082 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
20672083 RegArgs.push_back(VA.getLocReg());
20682084 } else if (VA.needsCustom()) {
20692085 // TODO: We need custom lowering for vector (v2f64) args.
20752091 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
20762092 "We only handle register args!");
20772093
2078 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2094 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
20792095 TII.get(ARM::VMOVRRD), VA.getLocReg())
20802096 .addReg(NextVA.getLocReg(), RegState::Define)
20812097 .addReg(Arg));
21022118 unsigned &NumBytes, bool isVarArg) {
21032119 // Issue CALLSEQ_END
21042120 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2105 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2121 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
21062122 TII.get(AdjStackUp))
21072123 .addImm(NumBytes).addImm(0));
21082124
21192135 MVT DestVT = RVLocs[0].getValVT();
21202136 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
21212137 unsigned ResultReg = createResultReg(DstRC);
2122 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2138 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
21232139 TII.get(ARM::VMOVDRR), ResultReg)
21242140 .addReg(RVLocs[0].getLocReg())
21252141 .addReg(RVLocs[1].getLocReg()));
21402156 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
21412157
21422158 unsigned ResultReg = createResultReg(DstRC);
2143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2159 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2160 TII.get(TargetOpcode::COPY),
21442161 ResultReg).addReg(RVLocs[0].getLocReg());
21452162 UsedRegs.push_back(RVLocs[0].getLocReg());
21462163
22172234 // Avoid a cross-class copy. This is very unlikely.
22182235 if (!SrcRC->contains(DstReg))
22192236 return false;
2220 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2221 DstReg).addReg(SrcReg);
2237 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2238 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
22222239
22232240 // Add register to return instruction.
22242241 RetRegs.push_back(VA.getLocReg());
22252242 }
22262243
22272244 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2228 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2245 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
22292246 TII.get(RetOpc));
22302247 AddOptionalDefs(MIB);
22312248 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
22982315 if (!isTypeLegal(ArgTy, ArgVT)) return false;
22992316
23002317 ISD::ArgFlagsTy Flags;
2301 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2318 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
23022319 Flags.setOrigAlign(OriginalAlignment);
23032320
23042321 Args.push_back(Op);
23232340 // Issue the call.
23242341 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
23252342 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2326 DL, TII.get(CallOpc));
2343 DbgLoc, TII.get(CallOpc));
23272344 // BL / BLX don't take a predicate, but tBL / tBLX do.
23282345 if (isThumb2)
23292346 AddDefaultPred(MIB);
24312448 if (Arg == 0)
24322449 return false;
24332450
2434 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2451 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
24352452 Flags.setOrigAlign(OriginalAlignment);
24362453
24372454 Args.push_back(*i);
24642481 // Issue the call.
24652482 unsigned CallOpc = ARMSelectCallOp(UseReg);
24662483 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2467 DL, TII.get(CallOpc));
2484 DbgLoc, TII.get(CallOpc));
24682485
24692486 unsigned char OpFlags = 0;
24702487
25812598 unsigned Depth = cast(I.getOperand(0))->getZExtValue();
25822599 while (Depth--) {
25832600 DestReg = createResultReg(RC);
2584 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2601 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
25852602 TII.get(LdrOpc), DestReg)
25862603 .addReg(SrcReg).addImm(0));
25872604 SrcReg = DestReg;
26382655 return SelectCall(&I, "memset");
26392656 }
26402657 case Intrinsic::trap: {
2641 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(
2658 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
26422659 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
26432660 return true;
26442661 }
27912808 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
27922809 bool isKill = 1 == Instr;
27932810 MachineInstrBuilder MIB = BuildMI(
2794 *FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg);
2811 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
27952812 if (setsCPSR)
27962813 MIB.addReg(ARM::CPSR, RegState::Define);
27972814 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
28692886 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
28702887 if(ResultReg == 0) return false;
28712888
2872 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2889 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
28732890 TII.get(Opc), ResultReg)
28742891 .addReg(Reg1);
28752892
30303047 // Load value.
30313048 if (isThumb2) {
30323049 DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
3033 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
3050 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
30343051 TII.get(ARM::t2LDRpci), DestReg1)
30353052 .addConstantPoolIndex(Idx));
30363053 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
30383055 // The extra immediate is for addrmode2.
30393056 DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
30403057 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3041 DL, TII.get(ARM::LDRcp), DestReg1)
3058 DbgLoc, TII.get(ARM::LDRcp), DestReg1)
30423059 .addConstantPoolIndex(Idx).addImm(0));
30433060 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
30443061 }
30543071 DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
30553072 GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
30563073 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3057 DL, TII.get(Opc), DestReg2)
3074 DbgLoc, TII.get(Opc), DestReg2)
30583075 .addReg(DestReg1)
30593076 .addReg(GlobalBaseReg);
30603077 if (!UseGOTOFF)
31283145 // Without this, EmitLiveInCopies may eliminate the livein if its only
31293146 // use is a bitcast (which isn't turned into an instruction).
31303147 unsigned ResultReg = createResultReg(RC);
3131 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
3148 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3149 TII.get(TargetOpcode::COPY),
31323150 ResultReg).addReg(DstReg, getKillRegState(true));
31333151 UpdateValueMap(I, ResultReg);
31343152 }
324324 II != IE; ++II, ++GTI) {
325325 const Value *Op = *II;
326326 if (StructType *STy = dyn_cast(*GTI)) {
327 const StructLayout *SL = TD.getStructLayout(STy);
327 const StructLayout *SL = DL.getStructLayout(STy);
328328 unsigned Idx = cast(Op)->getZExtValue();
329329 TmpOffset += SL->getElementOffset(Idx);
330330 } else {
331 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
331 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
332332 for (;;) {
333333 if (const ConstantInt *CI = dyn_cast(Op)) {
334334 // Constant-offset addressing.
406406 // register and continue. This should almost never happen.
407407 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
408408 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
409 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDI8),
409 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
410410 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
411411 Addr.Base.Reg = ResultReg;
412412 Addr.BaseType = Address::RegBase;
498498 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
499499 MFI.getObjectAlignment(Addr.Base.FI));
500500
501 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
501 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
502502 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
503503
504504 // Base reg with offset in range.
505505 } else if (UseOffset) {
506506
507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
508508 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
509509
510510 // Indexed form.
528528 case PPC::LFS: Opc = PPC::LFSX; break;
529529 case PPC::LFD: Opc = PPC::LFDX; break;
530530 }
531 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
531 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
532532 .addReg(Addr.Base.Reg).addReg(IndexReg);
533533 }
534534
614614 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
615615 MFI.getObjectAlignment(Addr.Base.FI));
616616
617 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)).addReg(SrcReg)
618 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
617 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
618 .addReg(SrcReg)
619 .addImm(Addr.Offset)
620 .addFrameIndex(Addr.Base.FI)
621 .addMemOperand(MMO);
619622
620623 // Base reg with offset in range.
621624 } else if (UseOffset)
622 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
625 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
623626 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
624627
625628 // Indexed form.
639642 case PPC::STFS: Opc = PPC::STFSX; break;
640643 case PPC::STFD: Opc = PPC::STFDX; break;
641644 }
642 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
643646 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
644647 }
645648
703706 CondReg))
704707 return false;
705708
706 BuildMI(*BrBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCC))
709 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
707710 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
708 FastEmitBranch(FBB, DL);
711 FastEmitBranch(FBB, DbgLoc);
709712 FuncInfo.MBB->addSuccessor(TBB);
710713 return true;
711714
713716 dyn_cast(BI->getCondition())) {
714717 uint64_t Imm = CI->getZExtValue();
715718 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
716 FastEmitBranch(Target, DL);
719 FastEmitBranch(Target, DbgLoc);
717720 return true;
718721 }
719722
810813 }
811814
812815 if (!UseImm)
813 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
816 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
814817 .addReg(SrcReg1).addReg(SrcReg2);
815818 else
816 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
819 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
817820 .addReg(SrcReg1).addImm(Imm);
818821
819822 return true;
852855
853856 // Round the result to single precision.
854857 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::FRSP), DestReg)
858 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
856859 .addReg(SrcReg);
857860
858861 UpdateValueMap(I, DestReg);
969972 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
970973
971974 // Generate the convert.
972 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
975 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
973976 .addReg(FPReg);
974977
975978 UpdateValueMap(I, DestReg);
10411044 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
10421045 if (InRC == &PPC::F4RCRegClass) {
10431046 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1044 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1047 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
10451048 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
10461049 .addReg(SrcReg).addImm(PPC::F8RCRegClassID);
10471050 SrcReg = TmpReg;
10611064 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
10621065
10631066 // Generate the convert.
1064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1067 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
10651068 .addReg(SrcReg);
10661069
10671070 // Now move the integer value from a float register to an integer register.
11541157 }
11551158
11561159 if (UseImm) {
1157 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1158 .addReg(SrcReg1).addImm(Imm);
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1161 ResultReg)
1162 .addReg(SrcReg1)
1163 .addImm(Imm);
11591164 UpdateValueMap(I, ResultReg);
11601165 return true;
11611166 }
11701175 if (ISDOpcode == ISD::SUB)
11711176 std::swap(SrcReg1, SrcReg2);
11721177
1173 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1178 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
11741179 .addReg(SrcReg1).addReg(SrcReg2);
11751180 UpdateValueMap(I, ResultReg);
11761181 return true;
12101215 NumBytes = CCInfo.getNextStackOffset();
12111216
12121217 // Issue CALLSEQ_START.
1213 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1218 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
12141219 TII.get(TII.getCallFrameSetupOpcode()))
12151220 .addImm(NumBytes);
12161221
12691274 ++NextGPR;
12701275 } else
12711276 ArgReg = NextGPR++;
1272
1273 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1274 ArgReg).addReg(Arg);
1277
1278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1279 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
12751280 RegArgs.push_back(ArgReg);
12761281 }
12771282
12841289 const Instruction *I, CallingConv::ID CC,
12851290 unsigned &NumBytes, bool IsVarArg) {
12861291 // Issue CallSEQ_END.
1287 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1292 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
12881293 TII.get(TII.getCallFrameDestroyOpcode()))
12891294 .addImm(NumBytes).addImm(0);
12901295
13141319 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
13151320 ResultReg = createResultReg(CpyRC);
13161321
1317 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1322 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
13181323 TII.get(TargetOpcode::COPY), ResultReg)
13191324 .addReg(SourcePhysReg);
13201325
13211326 // If necessary, round the floating result to single precision.
13221327 } else if (CopyVT == MVT::f64) {
13231328 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1324 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::FRSP),
1329 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
13251330 ResultReg).addReg(SourcePhysReg);
13261331
13271332 // If only the low half of a general register is needed, generate
13321337 ResultReg = createResultReg(&PPC::GPRCRegClass);
13331338 // Convert physical register from G8RC to GPRC.
13341339 SourcePhysReg -= PPC::X0 - PPC::R0;
1335 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1340 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
13361341 TII.get(TargetOpcode::COPY), ResultReg)
13371342 .addReg(SourcePhysReg);
13381343 }
14391444 if (Arg == 0)
14401445 return false;
14411446
1442 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1447 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
14431448 Flags.setOrigAlign(OriginalAlignment);
14441449
14451450 Args.push_back(*II);
14641469
14651470 // Build direct call with NOP for TOC restore.
14661471 // FIXME: We can and should optimize away the NOP for local calls.
1467 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1472 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14681473 TII.get(PPC::BL8_NOP));
14691474 // Add callee.
14701475 MIB.addGlobalAddress(GV);
15211526 const Constant *C = cast(RV);
15221527 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64);
15231528 unsigned RetReg = ValLocs[0].getLocReg();
1524 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1525 RetReg).addReg(SrcReg);
1529 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1530 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
15261531 RetRegs.push_back(RetReg);
15271532
15281533 } else {
15771582 }
15781583 }
15791584
1580 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1585 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
15811586 TII.get(TargetOpcode::COPY), RetRegs[i])
15821587 .addReg(SrcReg);
15831588 }
15841589 }
15851590 }
15861591
1587 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1592 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
15881593 TII.get(PPC::BLR));
15891594
15901595 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
16141619 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
16151620 Opc = PPC::EXTSW_32_64;
16161621 }
1617 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1622 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
16181623 .addReg(SrcReg);
16191624
16201625 // Unsigned 32-bit extensions use RLWINM.
16261631 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
16271632 MB = 16;
16281633 }
1629 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLWINM),
1634 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
16301635 DestReg)
16311636 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
16321637
16391644 MB = 48;
16401645 else
16411646 MB = 32;
1642 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1647 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
16431648 TII.get(PPC::RLDICL_32_64), DestReg)
16441649 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
16451650 }
16531658 if (AddrReg == 0)
16541659 return false;
16551660
1656 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::MTCTR8))
1661 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
16571662 .addReg(AddrReg);
1658 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCTR8));
1663 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
16591664
16601665 const IndirectBrInst *IB = cast(I);
16611666 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
16831688 // The only interesting case is when we need to switch register classes.
16841689 if (SrcVT == MVT::i64) {
16851690 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1686 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1691 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1692 TII.get(TargetOpcode::COPY),
16871693 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
16881694 SrcReg = ResultReg;
16891695 }
17901796 return 0;
17911797
17921798 // All FP constants are loaded from the constant pool.
1793 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
1799 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
17941800 assert(Align > 0 && "Unexpectedly missing alignment information!");
17951801 unsigned Idx = MCP.getConstantPoolIndex(cast(CFP), Align);
17961802 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
18061812
18071813 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
18081814 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1809 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocCPT),
1815 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
18101816 TmpReg)
18111817 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1812 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1818 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
18131819 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
18141820 } else {
18151821 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1816 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
1822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
18171823 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
18181824 // But for large code model, we must generate a LDtocL followed
18191825 // by the LF[SD].
18201826 if (CModel == CodeModel::Large) {
18211827 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocL),
1828 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
18231829 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
1824 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1830 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
18251831 .addImm(0).addReg(TmpReg2);
18261832 } else
1827 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1833 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
18281834 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
18291835 .addReg(TmpReg)
18301836 .addMemOperand(MMO);
18621868
18631869 // For small code model, generate a simple TOC load.
18641870 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtoc), DestReg)
1866 .addGlobalAddress(GV).addReg(PPC::X2);
1871 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
1872 DestReg)
1873 .addGlobalAddress(GV)
1874 .addReg(PPC::X2);
18671875 else {
18681876 // If the address is an externally defined symbol, a symbol with
18691877 // common or externally available linkage, a function address, or a
18741882 // ADDItocL(ADDIStocHA(%X2, GV), GV)
18751883 // Either way, start with the ADDIStocHA:
18761884 unsigned HighPartReg = createResultReg(RC);
1877 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
1885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
18781886 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
18791887
18801888 // !GVar implies a function address. An external variable is one
18831891 // on the "if" path here.
18841892 if (CModel == CodeModel::Large || !GVar || !GVar->hasInitializer() ||
18851893 GVar->hasCommonLinkage() || GVar->hasAvailableExternallyLinkage())
1886 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocL),
1894 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
18871895 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
18881896 else
18891897 // Otherwise generate the ADDItocL.
1890 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDItocL),
1898 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
18911899 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
18921900 }
18931901
19051913 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
19061914
19071915 if (isInt<16>(Imm))
1908 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1916 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
19091917 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
19101918 .addImm(Imm);
19111919 else if (Lo) {
19121920 // Both Lo and Hi have nonzero bits.
19131921 unsigned TmpReg = createResultReg(RC);
1914 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1922 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
19151923 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
19161924 .addImm(Hi);
1917 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1925 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
19181926 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
19191927 .addReg(TmpReg).addImm(Lo);
19201928 } else
19211929 // Just Hi bits.
1922 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1930 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
19231931 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
19241932 .addImm(Hi);
19251933
19591967 unsigned TmpReg2;
19601968 if (Imm) {
19611969 TmpReg2 = createResultReg(RC);
1962 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLDICR),
1970 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
19631971 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
19641972 } else
19651973 TmpReg2 = TmpReg1;
19671975 unsigned TmpReg3, Hi, Lo;
19681976 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
19691977 TmpReg3 = createResultReg(RC);
1970 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORIS8),
1978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
19711979 TmpReg3).addReg(TmpReg2).addImm(Hi);
19721980 } else
19731981 TmpReg3 = TmpReg2;
19741982
19751983 if ((Lo = Remainder & 0xFFFF)) {
19761984 unsigned ResultReg = createResultReg(RC);
1977 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORI8),
1985 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
19781986 ResultReg).addReg(TmpReg3).addImm(Lo);
19791987 return ResultReg;
19801988 }
19992007 if (isInt<16>(CI->getSExtValue())) {
20002008 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
20012009 unsigned ImmReg = createResultReg(RC);
2002 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg)
2010 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
20032011 .addImm(CI->getSExtValue());
20042012 return ImmReg;
20052013 }
20482056
20492057 if (SI != FuncInfo.StaticAllocaMap.end()) {
20502058 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDI8),
2059 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
20522060 ResultReg).addFrameIndex(SI->second).addImm(0);
20532061 return ResultReg;
20542062 }
228228
229229 ResultReg = createResultReg(RC);
230230 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
231 DL, TII.get(Opc), ResultReg), AM);
231 DbgLoc, TII.get(Opc), ResultReg), AM);
232232 return true;
233233 }
234234
247247 case MVT::i1: {
248248 // Mask out all but lowest bit.
249249 unsigned AndResult = createResultReg(&X86::GR8RegClass);
250 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
250 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
251251 TII.get(X86::AND8ri), AndResult).addReg(ValReg).addImm(1);
252252 ValReg = AndResult;
253253 }
288288 }
289289
290290 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
291 DL, TII.get(Opc)), AM).addReg(ValReg);
291 DbgLoc, TII.get(Opc)), AM).addReg(ValReg);
292292 return true;
293293 }
294294
296296 const X86AddressMode &AM, bool Aligned) {
297297 // Handle 'null' like i32/i64 0.
298298 if (isa(Val))
299 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
299 Val = Constant::getNullValue(DL.getIntPtrType(Val->getContext()));
300300
301301 // If this is a store of a simple constant, fold the constant into the store.
302302 if (const ConstantInt *CI = dyn_cast(Val)) {
317317
318318 if (Opc) {
319319 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
320 DL, TII.get(Opc)), AM)
320 DbgLoc, TII.get(Opc)), AM)
321321 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
322322 CI->getZExtValue());
323323 return true;
427427
428428 LoadReg = createResultReg(RC);
429429 MachineInstrBuilder LoadMI =
430 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
430 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg);
431431 addFullAddress(LoadMI, StubAM);
432432
433433 // Ok, back to normal mode.
546546 i != e; ++i, ++GTI) {
547547 const Value *Op = *i;
548548 if (StructType *STy = dyn_cast(*GTI)) {
549 const StructLayout *SL = TD.getStructLayout(STy);
549 const StructLayout *SL = DL.getStructLayout(STy);
550550 Disp += SL->getElementOffset(cast(Op)->getZExtValue());
551551 continue;
552552 }
553553
554554 // A array/variable index is always of the form i*S where S is the
555555 // constant scale size. See if we can push the scale into immediates.
556 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
556 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
557557 for (;;) {
558558 if (const ConstantInt *CI = dyn_cast(Op)) {
559559 // Constant-offset addressing.
695695 (AM.Base.Reg != 0 || AM.IndexReg != 0))
696696 return false;
697697
698 // Can't handle DLLImport.
698 // Can't handle DbgLocLImport.
699699 if (GV->hasDLLImportStorageClass())
700700 return false;
701701
749749 return false;
750750
751751 unsigned SABIAlignment =
752 TD.getABITypeAlignment(S->getValueOperand()->getType());
752 DL.getABITypeAlignment(S->getValueOperand()->getType());
753753 bool Aligned = S->getAlignment() == 0 || S->getAlignment() >= SABIAlignment;
754754
755755 MVT VT;
863863 // Avoid a cross-class copy. This is very unlikely.
864864 if (!SrcRC->contains(DstReg))
865865 return false;
866 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
866 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
867867 DstReg).addReg(SrcReg);
868868
869869 // Add register to return instruction.
880880 assert(Reg &&
881881 "SRetReturnReg should have been set in LowerFormalArguments()!");
882882 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
883 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
883 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
884884 RetReg).addReg(Reg);
885885 RetRegs.push_back(RetReg);
886886 }
887887
888888 // Now emit the RET.
889889 MachineInstrBuilder MIB =
890 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
890 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
891891 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
892892 MIB.addReg(RetRegs[i], RegState::Implicit);
893893 return true;
960960
961961 // Handle 'null' like i32/i64 0.
962962 if (isa(Op1))
963 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
963 Op1 = Constant::getNullValue(DL.getIntPtrType(Op0->getContext()));
964964
965965 // We have two options: compare with register or immediate. If the RHS of
966966 // the compare is an immediate that we can fold into this compare, use
967967 // CMPri, otherwise use CMPrr.
968968 if (const ConstantInt *Op1C = dyn_cast(Op1)) {
969969 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
970 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
970 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CompareImmOpc))
971971 .addReg(Op0Reg)
972972 .addImm(Op1C->getSExtValue());
973973 return true;
979979
980980 unsigned Op1Reg = getRegForValue(Op1);
981981 if (Op1Reg == 0) return false;
982 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
982 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CompareOpc))
983983 .addReg(Op0Reg)
984984 .addReg(Op1Reg);
985985
10031003
10041004 unsigned EReg = createResultReg(&X86::GR8RegClass);
10051005 unsigned NPReg = createResultReg(&X86::GR8RegClass);
1006 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
1007 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1006 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETEr), EReg);
1007 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
10081008 TII.get(X86::SETNPr), NPReg);
1009 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1009 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
10101010 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
10111011 UpdateValueMap(I, ResultReg);
10121012 return true;
10171017
10181018 unsigned NEReg = createResultReg(&X86::GR8RegClass);
10191019 unsigned PReg = createResultReg(&X86::GR8RegClass);
1020 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg);
1021 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg);
1022 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg)
1020 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETNEr), NEReg);
1021 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETPr), PReg);
1022 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::OR8rr),ResultReg)
10231023 .addReg(PReg).addReg(NEReg);
10241024 UpdateValueMap(I, ResultReg);
10251025 return true;
10591059 if (!X86FastEmitCompare(Op0, Op1, VT))
10601060 return false;
10611061
1062 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
1062 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SetCCOpc), ResultReg);
10631063 UpdateValueMap(I, ResultReg);
10641064 return true;
10651065 }
10961096 }
10971097
10981098 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1099 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovInst), Result32)
1099 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovInst), Result32)
11001100 .addReg(ResultReg);
11011101
11021102 ResultReg = createResultReg(&X86::GR64RegClass);
1103 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::SUBREG_TO_REG),
1103 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::SUBREG_TO_REG),
11041104 ResultReg)
11051105 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
11061106 } else if (DstVT != MVT::i8) {
11801180 if (!X86FastEmitCompare(Op0, Op1, VT))
11811181 return false;
11821182
1183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
1183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
11841184 .addMBB(TrueMBB);
11851185
11861186 if (Predicate == CmpInst::FCMP_UNE) {
11871187 // X86 requires a second branch to handle UNE (and OEQ,
11881188 // which is mapped to UNE above).
1189 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1189 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JP_4))
11901190 .addMBB(TrueMBB);
11911191 }
11921192
1193 FastEmitBranch(FalseMBB, DL);
1193 FastEmitBranch(FalseMBB, DbgLoc);
11941194 FuncInfo.MBB->addSuccessor(TrueMBB);
11951195 return true;
11961196 }
12111211 if (TestOpc) {
12121212 unsigned OpReg = getRegForValue(TI->getOperand(0));
12131213 if (OpReg == 0) return false;
1214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TestOpc))
1214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
12151215 .addReg(OpReg).addImm(1);
12161216
12171217 unsigned JmpOpc = X86::JNE_4;
12201220 JmpOpc = X86::JE_4;
12211221 }
12221222
1223 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(JmpOpc))
1223 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(JmpOpc))
12241224 .addMBB(TrueMBB);
1225 FastEmitBranch(FalseMBB, DL);
1225 FastEmitBranch(FalseMBB, DbgLoc);
12261226 FuncInfo.MBB->addSuccessor(TrueMBB);
12271227 return true;
12281228 }
12351235 unsigned OpReg = getRegForValue(BI->getCondition());
12361236 if (OpReg == 0) return false;
12371237
1238 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
1238 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
12391239 .addReg(OpReg).addImm(1);
1240 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1240 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_4))
12411241 .addMBB(TrueMBB);
1242 FastEmitBranch(FalseMBB, DL);
1242 FastEmitBranch(FalseMBB, DbgLoc);
12431243 FuncInfo.MBB->addSuccessor(TrueMBB);
12441244 return true;
12451245 }
12961296
12971297 unsigned Op1Reg = getRegForValue(I->getOperand(1));
12981298 if (Op1Reg == 0) return false;
1299 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1299 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
13001300 CReg).addReg(Op1Reg);
13011301
13021302 // The shift instruction uses X86::CL. If we defined a super-register
13031303 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
13041304 if (CReg != X86::CL)
1305 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1305 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
13061306 TII.get(TargetOpcode::KILL), X86::CL)
13071307 .addReg(CReg, RegState::Kill);
13081308
13091309 unsigned ResultReg = createResultReg(RC);
1310 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
1310 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg)
13111311 .addReg(Op0Reg);
13121312 UpdateValueMap(I, ResultReg);
13131313 return true;
14081408 return false;
14091409
14101410 // Move op0 into low-order input register.
1411 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1411 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14121412 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg);
14131413 // Zero-extend or sign-extend into high-order input register.
14141414 if (OpEntry.OpSignExtend) {
14151415 if (OpEntry.IsOpSigned)
1416 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1416 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14171417 TII.get(OpEntry.OpSignExtend));
14181418 else {
14191419 unsigned Zero32 = createResultReg(&X86::GR32RegClass);
1420 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1420 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14211421 TII.get(X86::MOV32r0), Zero32);
14221422
14231423 // Copy the zero into the appropriate sub/super/identical physical
14241424 // register. Unfortunately the operations needed are not uniform enough to
14251425 // fit neatly into the table above.
14261426 if (VT.SimpleTy == MVT::i16) {
1427 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1427 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14281428 TII.get(Copy), TypeEntry.HighInReg)
14291429 .addReg(Zero32, 0, X86::sub_16bit);
14301430 } else if (VT.SimpleTy == MVT::i32) {
1431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14321432 TII.get(Copy), TypeEntry.HighInReg)
14331433 .addReg(Zero32);
14341434 } else if (VT.SimpleTy == MVT::i64) {
1435 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1435 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14361436 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg)
14371437 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
14381438 }
14391439 }
14401440 }
14411441 // Generate the DIV/IDIV instruction.
1442 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1442 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14431443 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
14441444 // For i8 remainder, we can't reference AH directly, as we'll end
14451445 // up with bogus copies like %R9B = COPY %AH. Reference AX
14551455 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
14561456 unsigned SourceSuperReg = createResultReg(&X86::GR16RegClass);
14571457 unsigned ResultSuperReg = createResultReg(&X86::GR16RegClass);
1458 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1458 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
14591459 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
14601460
14611461 // Shift AX right by 8 bits instead of using AH.
1462 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SHR16ri),
1462 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SHR16ri),
14631463 ResultSuperReg).addReg(SourceSuperReg).addImm(8);
14641464
14651465 // Now reference the 8-bit subreg of the result.
14691469 // Copy the result out of the physreg if we haven't already.
14701470 if (!ResultReg) {
14711471 ResultReg = createResultReg(TypeEntry.RC);
1472 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Copy), ResultReg)
1472 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), ResultReg)
14731473 .addReg(OpEntry.DivRemResultReg);
14741474 }
14751475 UpdateValueMap(I, ResultReg);
15121512 // If we read more than the lsb, we may see non-zero values whereas lsb
15131513 // is zero. Therefore, we have to truncate Op0Reg to i1 for the select.
15141514 // This is achieved by performing TEST against 1.
1515 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
1515 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
15161516 .addReg(Op0Reg).addImm(1);
15171517 unsigned ResultReg = createResultReg(RC);
1518 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1518 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
15191519 .addReg(Op1Reg).addReg(Op2Reg);
15201520 UpdateValueMap(I, ResultReg);
15211521 return true;
15301530 unsigned OpReg = getRegForValue(V);
15311531 if (OpReg == 0) return false;
15321532 unsigned ResultReg = createResultReg(&X86::FR64RegClass);
1533 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1533 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
15341534 TII.get(X86::CVTSS2SDrr), ResultReg)
15351535 .addReg(OpReg);
15361536 UpdateValueMap(I, ResultReg);
15491549 unsigned OpReg = getRegForValue(V);
15501550 if (OpReg == 0) return false;
15511551 unsigned ResultReg = createResultReg(&X86::FR32RegClass);
1552 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1552 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
15531553 TII.get(X86::CVTSD2SSrr), ResultReg)
15541554 .addReg(OpReg);
15551555 UpdateValueMap(I, ResultReg);
15891589 (const TargetRegisterClass*)&X86::GR16_ABCDRegClass :
15901590 (const TargetRegisterClass*)&X86::GR32_ABCDRegClass;
15911591 unsigned CopyReg = createResultReg(CopyRC);
1592 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1592 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
15931593 CopyReg).addReg(InputReg);
15941594 InputReg = CopyReg;
15951595 }
17171717 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
17181718 // FIXME may need to add RegState::Debug to any registers produced,
17191719 // although ESP/EBP should be the only ones at the moment.
1720 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
1720 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II), AM).
17211721 addImm(0).addMetadata(DI->getVariable());
17221722 return true;
17231723 }
17241724 case Intrinsic::trap: {
1725 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1725 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TRAP));
17261726 return true;
17271727 }
17281728 case Intrinsic::sadd_with_overflow:
17591759 // The call to CreateRegs builds two sequential registers, to store the
17601760 // both the returned values.
17611761 unsigned ResultReg = FuncInfo.CreateRegs(I.getType());
1762 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
1762 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpC), ResultReg)
17631763 .addReg(Reg1).addReg(Reg2);
17641764
17651765 unsigned Opc = X86::SETBr;
17661766 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
17671767 Opc = X86::SETOr;
1768 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg+1);
1768 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1769 ResultReg + 1);
17691770
17701771 UpdateValueMap(&I, ResultReg, 2);
17711772 return true;
18391840 // Without this, EmitLiveInCopies may eliminate the livein if its only
18401841 // use is a bitcast (which isn't turned into an instruction).
18411842 unsigned ResultReg = createResultReg(RC);
1842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1843 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1844 TII.get(TargetOpcode::COPY),
18431845 ResultReg).addReg(DstReg, getKillRegState(true));
18441846 UpdateValueMap(I, ResultReg);
18451847 }
19681970 if (CS.paramHasAttr(AttrInd, Attribute::ByVal)) {
19691971 PointerType *Ty = cast(ArgVal->getType());
19701972 Type *ElementTy = Ty->getElementType();
1971 unsigned FrameSize = TD.getTypeAllocSize(ElementTy);
1973 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
19721974 unsigned FrameAlign = CS.getParamAlignment(AttrInd);
19731975 if (!FrameAlign)
19741976 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
20252027 return false;
20262028 if (ArgVT == MVT::x86mmx)
20272029 return false;
2028 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2030 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
20292031 Flags.setOrigAlign(OriginalAlignment);
20302032
20312033 Args.push_back(ArgReg);
20502052
20512053 // Issue CALLSEQ_START
20522054 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2053 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
2055 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
20542056 .addImm(NumBytes);
20552057
20562058 // Process argument: walk the register/memloc assignments, inserting
21192121 }
21202122
21212123 if (VA.isRegLoc()) {
2122 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2123 VA.getLocReg()).addReg(Arg);
2124 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2125 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
21242126 RegArgs.push_back(VA.getLocReg());
21252127 } else {
21262128 unsigned LocMemOffset = VA.getLocMemOffset();
21542156 // GOT pointer.
21552157 if (Subtarget->isPICStyleGOT()) {
21562158 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
2157 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2158 X86::EBX).addReg(Base);
2159 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2160 TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
21592161 }
21602162
21612163 if (Subtarget->is64Bit() && isVarArg && !isWin64) {
21652167 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
21662168 };
21672169 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri),
2170 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
21692171 X86::AL).addImm(NumXMMRegs);
21702172 }
21712173
21782180 CallOpc = X86::CALL64r;
21792181 else
21802182 CallOpc = X86::CALL32r;
2181 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
2183 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc))
21822184 .addReg(CalleeOp);
21832185
21842186 } else {
22122214 }
22132215
22142216
2215 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc));
2217 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
22162218 if (MemIntName)
22172219 MIB.addExternalSymbol(MemIntName, OpFlags);
22182220 else
22372239 // Issue CALLSEQ_END
22382240 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
22392241 const unsigned NumBytesCallee = computeBytesPoppedByCallee(*Subtarget, CS);
2240 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
2242 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
22412243 .addImm(NumBytes).addImm(NumBytesCallee);
22422244
22432245 // Build info for return calling conv lowering code.
22832285 CopyVT = MVT::f80;
22842286 CopyReg = createResultReg(&X86::RFP80RegClass);
22852287 }
2286 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
2287 CopyReg);
2288 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2289 TII.get(X86::FpPOP_RETVAL), CopyReg);
22882290 } else {
2289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2291 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2292 TII.get(TargetOpcode::COPY),
22902293 CopyReg).addReg(RVLocs[i].getLocReg());
22912294 UsedRegs.push_back(RVLocs[i].getLocReg());
22922295 }
22992302 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
23002303 unsigned MemSize = ResVT.getSizeInBits()/8;
23012304 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
2302 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2305 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
23032306 TII.get(Opc)), FI)
23042307 .addReg(CopyReg);
23052308 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
2306 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2309 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
23072310 TII.get(Opc), ResultReg + i), FI);
23082311 }
23092312 }
24382441
24392442 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
24402443 unsigned ResultReg = createResultReg(RC);
2441 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2444 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
24422445 TII.get(Opc), ResultReg), AM);
24432446 return ResultReg;
24442447 }
24462449 }
24472450
24482451 // MachineConstantPool wants an explicit alignment.
2449 unsigned Align = TD.getPrefTypeAlignment(C->getType());
2452 unsigned Align = DL.getPrefTypeAlignment(C->getType());
24502453 if (Align == 0) {
24512454 // Alignment of vector types. FIXME!
2452 Align = TD.getTypeAllocSize(C->getType());
2455 Align = DL.getTypeAllocSize(C->getType());
24532456 }
24542457
24552458 // x86-32 PIC requires a PIC base register for constant pools.
24692472 // Create the load from the constant pool.
24702473 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
24712474 unsigned ResultReg = createResultReg(RC);
2472 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2475 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
24732476 TII.get(Opc), ResultReg),
24742477 MCPOffset, PICBase, OpFlag);
24752478
24942497 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
24952498 const TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
24962499 unsigned ResultReg = createResultReg(RC);
2497 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2500 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
24982501 TII.get(Opc), ResultReg), AM);
24992502 return ResultReg;
25002503 }
25332536 }
25342537
25352538 unsigned ResultReg = createResultReg(RC);
2536 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
2539 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
25372540 return ResultReg;
25382541 }
25392542
25462549
25472550 const X86InstrInfo &XII = (const X86InstrInfo&)TII;
25482551
2549 unsigned Size = TD.getTypeAllocSize(LI->getType());
2552 unsigned Size = DL.getTypeAllocSize(LI->getType());
25502553 unsigned Alignment = LI->getAlignment();
25512554
25522555 SmallVector AddrOps;
637637
638638 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
639639 if ((*Memo.PhysRegs)[i] != "")
640 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
640 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
641641 << "TII.get(TargetOpcode::COPY), "
642642 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
643643 }
728728
729729 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
730730 if ((*Memo.PhysRegs)[i] != "")
731 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
731 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
732732 << "TII.get(TargetOpcode::COPY), "
733733 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
734734 }